22:
517:
The ARM architecture version 3 introduced a 32-bit PC and separate PSR, as well as a 32-bit address bus, allowing 4 GiB of memory to be addressed. The change in the PC/PSR layout caused incompatibility with code written for previous architectures, so the processor also included a 26-bit compatibility
439:
exploitation of 26-bit mode was limited. The few customers that exploited 26-bit mode eventually adjusted their applications to support 31-bit addressing, and IBM dropped support for 26-bit mode after several years producing models supporting 24-bit, 26-bit, and 31-bit modes. The 26-bit mode is the
479:
In fact, because the program counter is always word-aligned the lowest two bits are always zero which allowed the designers to reuse these two bits to hold the processor's mode bits too. The four modes allowed were USR26, SVC26, IRQ26, FIQ26; contrast this with the 32 possible modes available when
423:
needs continued to grow, IBM and their customers faced challenges directly addressing larger memory sizes. In what ended up being a short-term "emergency" solution, a pair of IBM's second wave of System/370 models, the 3033 and 3081, introduced 26-bit real memory addressing, increasing the
394:
units are those that are 26 bits wide, and thus can represent unsigned values up to 67,108,863. Two examples of computer processors that featured 26-bit memory addressing are certain second generation IBM
402:
models introduced in 1981 (and several subsequent models), which had 26-bit physical addresses but had only the same 24-bit virtual addresses as earlier models, and the first generations of
428:
limit of 16 MB. IBM referred to 26-bit addressing as "extended real addressing," and some subsequent models also included 26-bit support. However, only 2 years later, IBM introduced
514:. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.
435:
Given 26-bit's brief history as the state-of-the-art in memory addressing available in IBM's model range, and given that virtual addresses were still limited to 24 bits,
362:
432:
memory addressing, expanding both physical and virtual addresses to 31 bits, with its System/370-XA models, and even the popular 3081 was upgradeable to XA standard.
533:
ARM architecture version 4 made the support of the 26-bit addressing modes optional, and ARM architecture version 5 onwards has removed them entirely.
355:
51:
348:
295:
499:
response than traditional designs, which would have to do two register loads or saves when calling or returning from a subroutine.
301:
547:
491:
execution, as the
Program Counter and status flags could be saved and restored with a single operation. This resulted in faster
284:
273:
262:
73:
44:
542:
335:
330:
325:
518:
mode which used the old PC/PSR combination. The processor could still address 4 GB in this mode, but could not
315:
252:
94:
444:. All the other addressing modes, including now 64-bit mode, are supported in current model mainframes.
239:
234:
229:
569:
476:(R15), the status flags filling the high 6 bits and the Program Counter taking up the lower 26 bits.
249:
34:
506:
ALU and word-length, processors based on ARM architecture version 1 and 2 had only a 26-bit PC and
38:
30:
424:
System/370's amount of physical memory that could be attached by a factor of 4 from the previous
312:
55:
440:
only addressing mode that IBM removed from its line of mainframe computers descended from the
519:
376:
511:
214:
8:
473:
399:
290:
279:
550:- Details on the architectural changes and converting code between 26-bit and 32-bit.
199:
194:
189:
530:
to utilise the new processors while retaining compatibility with existing software.
503:
488:
481:
453:
429:
425:
391:
184:
179:
174:
169:
164:
159:
154:
144:
134:
129:
124:
119:
465:
457:
420:
224:
114:
109:
104:
553:
548:"Using the Acorn C/C++ Development Environment to write 32-bit RISC OS software"
387:
563:
456:, 26-bit refers to the design used in the original ARM processors where the
507:
480:
the program status was separated from the program counter in more recent
403:
204:
492:
441:
396:
149:
522:
anything above address 0x3FFFFFC (64 MB). This mode was used by
496:
268:
436:
383:
527:
523:
510:, and were consequently limited to 64 MiB of addressable
543:
Differences
Between ARM6 and Earlier ARM Processors
561:
43:but its sources remain unclear because it lacks
556:- Information on converting assembler to 32-bit
554:http://www.heyrick.co.uk/assembler/32bit.html
356:
363:
349:
74:Learn how and when to remove this message
447:
562:
15:
487:This design enabled more efficient
13:
14:
581:
536:
414:
472:) were combined into one 32-bit
89:Computer architecture bit widths
20:
1:
7:
10:
586:
454:ARM processor architecture
409:
466:Processor Status Register
29:This article includes a
58:more precise citations.
313:Decimal floating-point
377:computer architecture
250:Binary floating-point
448:Early ARM processors
400:mainframe computer
31:list of references
502:Despite having a
482:ARM architectures
373:
372:
84:
83:
76:
577:
570:ARM architecture
388:memory addresses
365:
358:
351:
86:
85:
79:
72:
68:
65:
59:
54:this article by
45:inline citations
24:
23:
16:
585:
584:
580:
579:
578:
576:
575:
574:
560:
559:
539:
526:running on the
458:Program Counter
450:
421:data processing
417:
412:
369:
340:
307:
244:
209:
80:
69:
63:
60:
49:
35:related reading
25:
21:
12:
11:
5:
583:
573:
572:
558:
557:
551:
545:
538:
537:External links
535:
449:
446:
416:
415:IBM System/370
413:
411:
408:
371:
370:
368:
367:
360:
353:
345:
342:
341:
339:
338:
333:
328:
322:
319:
318:
309:
308:
306:
305:
299:
293:
288:
282:
277:
271:
266:
259:
256:
255:
246:
245:
243:
242:
237:
232:
227:
221:
218:
217:
211:
210:
208:
207:
202:
197:
192:
187:
182:
177:
172:
167:
162:
157:
152:
147:
142:
137:
132:
127:
122:
117:
112:
107:
101:
98:
97:
91:
90:
82:
81:
39:external links
28:
26:
19:
9:
6:
4:
3:
2:
582:
571:
568:
567:
565:
555:
552:
549:
546:
544:
541:
540:
534:
531:
529:
528:Acorn Risc PC
525:
521:
515:
513:
509:
505:
500:
498:
494:
490:
485:
483:
477:
475:
471:
467:
463:
459:
455:
445:
443:
438:
433:
431:
427:
422:
407:
405:
401:
398:
393:
389:
385:
382:
378:
366:
361:
359:
354:
352:
347:
346:
344:
343:
337:
334:
332:
329:
327:
324:
323:
321:
320:
317:
314:
311:
310:
303:
300:
297:
294:
292:
289:
286:
283:
281:
278:
275:
272:
270:
267:
264:
261:
260:
258:
257:
254:
251:
248:
247:
241:
238:
236:
233:
231:
228:
226:
223:
222:
220:
219:
216:
213:
212:
206:
203:
201:
198:
196:
193:
191:
188:
186:
183:
181:
178:
176:
173:
171:
168:
166:
163:
161:
158:
156:
153:
151:
148:
146:
143:
141:
138:
136:
133:
131:
128:
126:
123:
121:
118:
116:
113:
111:
108:
106:
103:
102:
100:
99:
96:
93:
92:
88:
87:
78:
75:
67:
57:
53:
47:
46:
40:
36:
32:
27:
18:
17:
532:
516:
501:
486:
478:
469:
461:
451:
434:
418:
406:processors.
380:
374:
139:
70:
61:
50:Please help
42:
508:address bus
390:, or other
215:Application
205:bit slicing
56:introducing
495:calls and
493:subroutine
442:System/360
397:System/370
497:interrupt
316:precision
253:precision
64:June 2011
564:Category
474:register
437:software
384:integers
524:RISC OS
520:execute
489:program
452:In the
410:History
52:improve
512:memory
504:32-bit
464:) and
430:31-bit
426:24-bit
381:26-bit
37:, or
392:data
304:(×8)
298:(×4)
287:(×2)
276:(×1)
265:(×½)
470:PSR
419:As
404:ARM
375:In
336:128
302:256
296:128
200:512
195:256
190:128
95:Bit
566::
484:.
462:PC
386:,
379:,
331:64
326:32
291:80
285:64
280:40
274:32
269:24
263:16
240:64
235:32
230:16
185:64
180:60
175:48
170:45
165:36
160:32
155:31
150:30
145:28
140:26
135:24
130:18
125:16
120:12
41:,
33:,
468:(
460:(
364:e
357:t
350:v
225:8
115:8
110:4
105:1
77:)
71:(
66:)
62:(
48:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.