2625:
datawords in memory, which in practice is very often the case. For instance, in DDR1, two adjacent data words will be read from each chip in the same clock cycle and placed in the pre-fetch buffer. Each word will then be transmitted on consecutive rising and falling edges of the clock cycle. Similarly, in DDR2 with a 4n pre-fetch buffer, four consecutive data words are read and placed in buffer while a clock, which is twice faster than the internal clock of DDR, transmits each of the word in consecutive rising and falling edge of the faster external clock
3227:
command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.
2300:
2632:), the IOs will operate 8 times faster than the memory core (each memory access results in a burst of 8 datawords on the IOs). Thus, a 200 MHz memory core is combined with IOs that each operate eight times faster (1600 megabits per second). If the memory has 16 IOs, the total read bandwidth would be 200 MHz x 8 datawords/access x 16 IOs = 25.6 gigabits per second (Gbit/s) or 3.2 gigabytes per second (GB/s). Modules with multiple DRAM chips can provide correspondingly higher bandwidth.
2485:, later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of four, and a requested column address of five, the words would be accessed in the order 5-6-7-4. If the burst length were eight, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length. The interleaved burst mode computes the address using an
2478:
option: sequential or interleaved. Typically, a memory controller will require one or the other. When the burst length is one or two, the burst type does not matter. For a burst length of one, the requested word is the only word accessed. For a burst length of two, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified.
2827:
3655:
1525:
2950:
1798:
cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high. Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.
1601:
3432:
SDRAM's read and write commands specify a channel number to access. Reads and writes may thus be performed independent of the currently active state of the DRAM array, with the equivalent of four full DRAM rows being "open" for access at a time. This is an improvement over the two open rows possible in a standard two-bank SDRAM. (There is actually a 17th "dummy channel" used for some operations.)
1778:
standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 - although the actual meaning of the numbers has changed).
2474:. A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line.
3436:
DRAM array may be precharged while read commands to the channel buffer continue. To write, first the data is written to a channel buffer (typically previous initialized using a
Prefetch command), then a restore command, with the same parameters as the prefetch command, copies a segment of data from the channel to the sense amplifier array.
3548:(GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2023, there are eight successive generations of GDDR:
3444:
cells.) The SRAM bits are designed to be four DRAM bits wide, and are conveniently connected to one of the four DRAM bits they straddle.) Additional commands prefetch a pair of segments to a pair of channels, and an optional command combines prefetch, read, and precharge to reduce the overhead of random reads.
3439:
Unlike a normal SDRAM write, which must be performed to an active (open) row, the VCSDRAM bank must be precharged (closed) when the restore command is issued. An active command immediately after the restore command specifies the DRAM row completes the write to the DRAM array. There is, in addition, a
3435:
To read from VCSDRAM, after the active command, a "prefetch" command is required to copy data from the sense amplifier array to the channel SDRAM. This command specifies a bank, two bits of column address (to select the segment of the row), and four bits of channel number. Once this is performed, the
3357:
Individual devices had 8-bit IDs. The 9th bit of the ID sent in commands was used to address multiple devices. Any aligned power-of-2 sized group could be addressed. If the transmitted msbit was set, all least-significant bits up to and including the least-significant 0 bit of the transmitted address
3124:
in San
Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development - it was originally expected to be released in 2012, and later (during 2010) expected to be released in 2015, before samples were announced in early 2011 and manufacturers
2569:
Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh
2446:
Interrupting a read burst by a write command is possible, but more difficult. It can be done if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data
2435:
A read, burst terminate, or precharge command may be issued at any time after a read command, and will interrupt the read burst after the configured CAS latency. So if a read command is issued on cycle 0, another read command is issued on cycle 2, and the CAS latency is 3, then the first read command
2382:
When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at
1773:
In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally
1591:
means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a
2860:
Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is
2620:
The drawback of the older fast column access method was that a new column address had to be sent for each additional dataword on the row. The address bus had to operate at the same frequency as the data bus. Prefetch architecture simplifies this process by allowing a single address request to result
2573:
SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate. Another is selective refresh, which limits
2378:
command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be
3450:
A 13-bit address bus, as illustrated here, is suitable for a device up to 128 Mbit. It has two banks, each containing 8,192 rows and 8,192 columns. Thus, row addresses are 13 bits, segment addresses are two bits, and eight column address bits are required to select one byte from the 2,048 bits
3226:
SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the
3101:
DDR3 memory chips are being made commercially, and computer systems using them were available from the second half of 2007, with significant usage from 2008 onwards. Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667
3068:
Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25 ns). Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is
2597:
precharge, row access, column access. Row access is the heart of a read operation, as it involves the careful sensing of the tiny signals in DRAM memory cells; it is the slowest phase of memory operation. However, once a row is read, subsequent column accesses to that same row can be very quick, as
2541:
It is possible to refresh a RAM chip by opening and closing (activating and precharging) each row in each bank. However, to simplify the memory controller, SDRAM chips support an "auto refresh" command, which performs these operations to one row in each bank simultaneously. The SDRAM also maintains
3431:
VCM inserts an SRAM cache of 16 "channel" buffers, each 1/4 row "segment" in size, between DRAM banks' sense amplifier rows and the data I/O pins. "Prefetch" and "restore" commands, unique to VCSDRAM, copy data between the DRAM's sense amplifier row and the channel buffers, while the equivalent of
3038:
interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR
1816:
appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from
3209:
SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its
2986:
A module built out of 100 MHz SDRAM chips is not necessarily capable of operating at 100 MHz. The PC100 standard specifies the capabilities of the memory module as a whole. PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory.
2532:
Later (double data rate) SDRAM standards use more mode register bits, and provide additional mode registers called "extended mode registers". The register number is encoded on the bank address pins during the load mode register command. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit
2520:
M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the
3443:
Although normally a segment is restored to the same memory address as it was prefetched from, the channel buffers may also be used for very efficient copying or clearing of large, aligned memory blocks. (The use of quarter-row segments is driven by the fact that DRAM cells are narrower than SRAM
3064:
DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be
2450:
Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output on a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient
1797:
clock enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock
3049:
Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available.
2624:
In a prefetch buffer architecture, when a memory access occurs to a row the buffer grabs a set of adjacent data words on the row and reads them out ("bursts" them) in rapid-fire sequence on the IO pins, without the need for individual column address requests. This assumes the CPU wants adjacent
2477:
Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a four-word burst access to any column address from four to seven will return words four to seven. The ordering, however, depends on the requested address, and the configured burst type
3086:
DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words. This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. To maintain 800–1600 M transfers/s (both edges of a
2506:
Single data rate SDRAM has a single 10-bit programmable mode register. Later double-data-rate SDRAM standards add additional mode registers, addressed using the bank address pins. For SDR SDRAM, the bank address pins and address lines A10 and above are ignored, but should be zero during a mode
1777:
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100
2527:
M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will
2320:
command activates an idle bank. It presents a two-bit bank address (BA0–BA1) and a 13-bit row address (A0–A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of
2554:
As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM. The CKE input is sampled each rising edge of the clock, and if it is low, the following rising edge of the clock is ignored for all purposes other than checking CKE. As long as CKE is low, it is
2489:
operation between the counter and the address. Using the same starting address of five, a four-word burst would return words in the order 5-4-7-6. An eight-word burst would be 5-4-7-6-1-0-3-2. Although more confusing to humans, this can be easier to implement in hardware, and is preferred by
3395:
Additional commands (with CMD5 set) opened and closed rows without a data transfer, performed refresh operations, read or wrote configuration registers, and performed other maintenance operations. Most of these commands supported an additional 4-bit sub-ID (sent as 5 bits, using the same
2447:
are delayed by two cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command but must be lowered for the cycle of the write command (assuming the write command is intended to have an effect).
2370:
command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency. Subsequent words of the burst will be produced in time for subsequent rising clock edges.
2616:
Traditional DRAM architectures have long supported fast column access to bits on an open row. For an 8-bit-wide memory chip with a 2,048 bit wide row, accesses to any of the 256 datawords (2048/8) on the row can be very quick, provided no intervening accesses to other rows occur.
1763: Hz) to 5 ns for DDR-400, but remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.
2407:
The no operation command is always permitted, while the load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect. The auto refresh command also requires that all banks be idle, and takes a refresh cycle time
2497:
If the requested column address is at the start of a block, both burst modes (sequential and interleaved) return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order.
3214:
and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400 MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like
3180:
In March 2017, JEDEC announced a DDR5 standard is under development, but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.
3200:
was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR SDRAM.
2307:
As an example, a 512 MB SDRAM DIMM (which contains 512 MB), might be made of eight or nine SDRAM chips, each containing 512 Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM
3125:
began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.
1574:
that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called
2561:
If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval
3033:
While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a
3065:
doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips.
3069:
now available at a clock rate of 533 MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available.
2864:
Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns), respectively denoted PC66, PC100, and PC133. Clock rates up to 200 MHz were available. It operates at a voltage of 3.3 V.
2470:. To transfer a 64-byte cache line requires eight consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform eight-word
5997:
Kalter, H. L.; Stapper, C. H.; Barth, J. E.; Dilorenzo, J.; Drake, C. E.; Fifield, J. A.; Kelley, G. A.; Lewis, S. C.; van der Hoeven, W. B.; Jankosky, J. A. (1990). "A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC".
2442:
Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst.
2542:
an internal counter, which iterates over all possible rows. The memory controller must simply issue a sufficient number of auto refresh commands (one per row, 8192 in the example we have been using) every refresh interval (t
1616:
The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.
2849:, single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin
3014:
form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066 GB per second (=1.066 GB/s). (1 GB/s = one billion bytes per second) PC133 is
3415:
because VCM was not nearly as expensive as RDRAM was. A Virtual
Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, so support for both depends only on the capabilities of the
1774:
increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
1735:
There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM (1 MHz =
3396:
multiple-destination encoding as the primary ID) which could be used to distinguish devices that were assigned the same primary ID because they were connected in parallel and always read/written at the same time.
1885:
SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward.
7765:
3094:. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a
2398:
command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.
2312:
internally contains four independent 16 MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.
2578:(LPDDR) and LPDDR2 is "deep power down" mode, which invalidates the memory and requires a full reinitialization to exit from. This is activated by sending a "burst terminate" command while lowering CKE.
3154:
validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since, as of 2009, current DRAM chips were only beginning to migrate to a 50 nm process. In
January 2011,
6334:
7640:
7264:
3072:
Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100 MHz) has somewhat higher latency than DDR-400 (internal clock rate 200 MHz).
6051:
The first commercial synchronous DRAM, the
Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.
2363:
commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0–A9, A11).
3358:
were ignored for "is this addressed to me?" purposes. (If the ID8 bit is actually considered less significant than ID0, the unicast address matching becomes a special case of this pattern.)
1770:, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.
2427:
When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands.
2868:
This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate). But this type is also faster than its predecessors
1894:
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.
1681:
to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for
3411:, but released as an open standard with no licensing fees. It is pin-compatible with standard SDRAM, but the commands are different. The technology was a potential competitor of
1666:
due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective
3136:
per second. They were expected to be introduced at frequency rates of 2133 MHz, estimated to rise to a potential 4266 MHz and lowered voltage of 1.05 V by 2013.
7088:
3440:
17th "dummy channel" which allows writes to the currently open row. It may not be read from, but may be prefetched to, written to, and restored to the sense amplifier array.
7733:
7489:
7675:
3627:. It is designed to be used in conjunction with high-performance graphics accelerators and network devices. The first HBM memory chip was produced by SK Hynix in 2013.
3102:
and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common. Performance up to DDR3-2800 (PC3 22400 modules) are available.
7776:
3039:
interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM.
7891:
1761:
2968:. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin
2570:
mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.
17:
2340:
before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an
2628:
The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency. In an 8n prefetch architecture (such as
2390:
Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time t
7989:
7296:
7201:
3447:
The above are the JEDEC-standardized commands. Earlier chips did not support the dummy channel or pair prefetch, and use a different encoding for precharge.
1562:
interface, in which input control signals have a direct effect on internal functions delayed only by the trip across its semiconductor pathways. SDRAM has a
6695:
6818:
6436:
2593:
The prefetch architecture takes advantage of the specific characteristics of memory accesses to DRAM. Typical DRAM memory operations involve three phases:
7994:
7984:
6338:
2895:. PC66 is Synchronous DRAM operating at a clock frequency of 66.66 MHz, on a 64-bit bus, at a voltage of 3.3 V. PC66 is available in 168-pin
7515:
2574:
self-refresh to a portion of the DRAM array. The fraction which is refreshed is configured using an extended mode register. The third, implemented in
7338:
6943:
1662:
SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous
6642:
6519:
2907:
2439:
If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5.
6109:
7707:
7614:
7585:
7058:
6726:
3475:(writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike
3459:
Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It is designed for graphics-related tasks such as
2387:, which must elapse before that row is fully "closed" and so the bank is idle in order to receive another activate command on that bank.
3158:
announced the completion and release for testing of a 30 nm 2048 MB DDR4 DRAM module. It has a maximum bandwidth of 2.13
2352:
command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.
7918:
8309:
2436:
will begin bursting data out during cycles 3 and 4, then the results from the second read command will appear beginning with cycle 5.
1786:
All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly
1566:
interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by
5082:
2999:
2965:
2892:
2609:
wide, so internally 2,048 bits are read into 2,048 separate sense amplifiers during the row access phase. Row accesses might take 50
2594:
7378:
1806:
chip select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.
637:
5748:
4916:
7560:
6384:
3006:
operating at a clock frequency of 133 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC133 is available in 168-pin
6600:
6567:
6482:
4532:
4345:
4191:
1511:
6359:
1052:
6410:
6500:
3816:
3612:
2705:
6207:
1585:
fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.
7432:
3399:
There were a number of 8-bit control registers and 32-bit status registers to control various device timing parameters.
2566:, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings.
2514:
M9: Write burst mode. If 0, writes use the read burst length and mode. If 1, all writes are non-burst (single location).
6852:
6298:
1261:
213:
6669:
258:
6792:
5981:
5954:
5927:
2336:
commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or t
1000:
943:
263:
7833:
6316:
6268:
3046:
for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.
2558:
If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again.
2420:.) The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, t
8340:
5113:
3715:
111:
7190:
1581:, allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an
1326:
986:
930:
6440:
2379:
done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line.
8021:
6255:
3425:
3147:
prefetch as DDR3. Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.
1012:
681:
493:
89:
6225:
2454:
If the read command includes auto-precharge, the precharge begins the same cycle as the interrupting command.
7802:
7324:
1876:, this selects one of eight commands. It generally distinguishes read-like commands from write-like commands.
1592:
fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.
1361:
6461:
8170:
8030:
7940:
6782:
5895:
3476:
2841:
48LC32M8A2 SDRAM chips. They run at 133 MHz (7.5 ns clock period) and have 8-bit wide data buses.
2793:
2777:
2747:
712:
607:
508:
7490:"Samsung Electronics Announces Industry's First 8Gb LPDDR5 DRAM for 5G and AI-powered Mobile Applications"
669:
7525:
7125:
2510:
The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle.
2276:
DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer
6970:
6280:
3384:
A notable omission from the specification was per-byte write enables; it was designed for systems with
2903:
form factors. The theoretical bandwidth is 533 MB/s. (1 MB/s = one million bytes per second)
2383:
the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, t
1628:
RAM and presented their results at the
International Solid-State Circuits Convention in 1990. In 1998,
1504:
1301:
1200:
1072:
702:
691:
7892:"Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems"
7641:"Samsung Announces the World's First 222 MHz 32Mbit SGRAM for 3D Graphics and Networking Applications"
6932:
3098:
of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).
800:
7265:"Samsung Develops the Industry's Fastest DDR3 SRAM for High Performance EDP and Network Applications"
6994:
6152:
5877:
2546:= 64 ms is a common value). All banks must be idle (closed, precharged) when this command is issued.
2251:
The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)
2226:
Auto refresh: refresh one row of each bank, using an internal counter. All banks must be precharged.
563:
498:
393:
6633:
3636:
2524:
M3: Burst type. 0 - requests sequential burst ordering, while 1 requests interleaved burst ordering.
1655:) the same year and mass-produced in 1993. By 2000, SDRAM had replaced virtually all other types of
5894:
A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in
3545:
2613:, depending on the speed of the DRAM, whereas column accesses off an open row are less than 10 ns.
2286:
controls it, during which the other control lines are used as row address bits 16, 15 and 14. When
1373:
1356:
845:
131:
5919:
Microprocessor: Prolegomenes - Calculation and
Storage Functions - Calculation Models and Computer
3087:
400–800 MHz clock), the internal RAM array has to perform 100–200 M fetches per second.
7555:
3421:
1368:
1185:
908:
313:
148:
126:
106:
59:
8299:
3189:
In addition to DDR, there were several other proposed memory technologies to succeed SDR SDRAM.
2257:
All SDRAM generations (SDR and DDRx) use essentially the same commands, with the changes being:
6903:
5882:
3620:
2869:
2482:
2471:
1241:
458:
328:
268:
7047:
6192:
2528:
continue until interrupted. Full-row bursts are only permitted with the sequential burst type.
590:
8122:
7865:
7738:
7645:
7463:
7458:
7406:
7401:
7343:
7269:
6939:
5682:
5086:
4561:
3794:
3608:
3603:
3507:
3502:μPD481850, introduced in December 1994. The earliest known commercial device to use SGRAM is
3483:, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the
3121:
3091:
1667:
1497:
744:
662:
448:
253:
233:
223:
79:
44:
7978:
1739:
8283:
7156:
6544:
6007:
3918:
2976:
2961:
2888:
1588:
1571:
1547:
where the operation of its external pin interface is coordinated by an externally supplied
1440:
1308:
1087:
1047:
970:
583:
488:
378:
273:
136:
116:
99:
94:
8314:
7370:
3644:
8:
7772:
7711:
7680:
7191:"EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP"
7161:
7093:
6823:
5262:
3906:
3866:
3752:
3616:
3591:
3219:, SLDRAM uses a double-pumped bus, giving it an effective speed of 400, 600, or 800
3016:
2980:
2873:
1712:
1648:
1605:
1346:
1037:
975:
960:
827:
779:
632:
443:
141:
6011:
3668:
Please help update this article to reflect recent events or newly available information.
8154:
8014:
7318:
3515:
3511:
2831:
1701:
1673:
Today, virtually all SDRAM is manufactured in compliance with standards established by
1582:
1555:
1446:
1411:
1057:
483:
468:
413:
408:
398:
373:
298:
7999:
2533:
extended mode register No. 1 (EMR1), and a 5-bit extended mode register No. 2 (EMR2).
7547:
7520:
6177:
6041:
5977:
5950:
5923:
5707:
3417:
3163:
2838:
1852:, column address strobe. This is also not a strobe, rather a command bit. Along with
1720:
1697:
1123:
1118:
1042:
1007:
861:
839:
738:
697:
600:
438:
163:
6609:
6576:
6240:
3640:
6363:
6015:
3533:
3132:
or less, compared to the 1.5 V of DDR3 chips, and have in excess of 2 billion
3035:
2726:
2586:
DDR SDRAM employs prefetch architecture to allow quick and easy access to multiple
1724:
1633:
1625:
1458:
1452:
1378:
1341:
1331:
1296:
1108:
1062:
1030:
805:
788:
473:
433:
193:
178:
74:
64:
7089:"Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option"
3230:
The basic read/write command consisted of (beginning with CA9 of the first word):
8106:
7970:
Everything you always wanted to know about SDRAM (memory), but were afraid to ask
6856:
6414:
6036:
5971:
5944:
5917:
3484:
3368:
CMD4=1 to open (activate) the specified row; CMD4=0 to use the currently open row
2876:(FPM-RAM) which took typically two or three clocks to transfer one word of data.
1351:
1178:
1165:
856:
851:
707:
574:
553:
528:
388:
308:
238:
208:
183:
69:
40:
6520:"DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond"
8335:
7834:"Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand"
3460:
2931:
2322:
2273:
DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"
1678:
1663:
1470:
1388:
1231:
888:
750:
686:
558:
543:
523:
518:
463:
428:
383:
333:
323:
318:
303:
198:
188:
121:
7734:"Samsung Electronics Develops Industry's First Ultra-Fast GDDR4 Graphics DRAM"
2299:
8329:
8260:
8175:
8007:
6975:
6096:
5824:
5028:
4444:
4439:
4169:
3871:
3583:
GDDR was initially known as DDR SGRAM. It was commercially introduced as a 16
3480:
3211:
3133:
2927:
1476:
1103:
1098:
1067:
822:
732:
548:
538:
533:
513:
348:
338:
218:
203:
6849:
2279:
7860:
7676:"Samsung Electronics Announces JEDEC-Compliant 256Mb GDDR2 for 3D Graphics"
7301:
6660:
5584:
5558:
4872:
4818:
4790:
2923:
2915:
2486:
1705:
1548:
1423:
1417:
1383:
1251:
1206:
1190:
1082:
878:
873:
833:
795:
478:
453:
353:
288:
243:
228:
7239:
7022:
6878:
6462:"Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology"
8220:
8215:
8210:
8205:
8200:
8195:
3464:
3095:
2125:
Write with auto precharge: as above, and precharge (close row) when done
1787:
1767:
1577:
1544:
1482:
1434:
868:
403:
343:
248:
6754:
2249:
Load mode register: A0 through A9 are loaded to configure the DRAM chip.
2073:
Read with auto precharge: as above, and precharge (close row) when done
1817:
the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.
8190:
8093:
8088:
8083:
8078:
4275:
3537:
3527:
3468:
3389:
3175:
3117:
3111:
3081:
3059:
2943:
2854:
2834:
2826:
2803:
2785:
2758:
2663:
2657:
2651:
2645:
2610:
2575:
2555:
permissible to change the clock rate, or even stop the clock entirely.
2467:
1690:
1686:
1077:
903:
657:
423:
418:
293:
158:
84:
31:
7969:
2598:
the sense amplifiers also act as latches. For reference, a row of a 1
2412:
to return the chip to the idle state. (This time is usually equal to t
2270:
Additional extended mode registers (selected by the bank address bits)
1524:
8250:
8073:
7973:
7838:
7807:
5148:
5020:
4021:
3747:
3541:
3385:
3216:
3028:
3003:
2949:
2715:
2639:
2587:
2463:
2424:
before the row is fully open and can accept read and write commands.
1682:
1637:
1464:
1429:
1266:
1195:
1093:
964:
955:
652:
595:
363:
283:
7919:"Samsung fires up its foundries for mass production of GDDR6 memory"
6019:
3166:
technology and draws 40% less power than an equivalent DDR3 module.
8245:
8050:
8045:
7130:
5888:
5639:
3624:
3472:
1716:
1652:
1393:
1336:
1271:
1226:
1211:
981:
950:
923:
898:
756:
642:
368:
278:
173:
168:
5896:
High-Performance DRAM System Design
Constraints and Considerations
3377:
CMD1=1 to close the row after this access; CMD1=0 to leave it open
8278:
8142:
7895:
7870:
7743:
7685:
7650:
7493:
7468:
7411:
7348:
7274:
7166:
7098:
6907:
6828:
6701:
6136:
Micron, General DDR SDRAM Functionality, Technical Note, TN-46-05
5154:
4208:
3742:
3587:
3495:
3155:
3151:
3011:
2973:
2900:
2666:'s prefetch buffer size is 8n; there is an additional mode of 16n
2660:'s prefetch buffer size is 8n (eight datawords per memory access)
2654:'s prefetch buffer size is 8n (eight datawords per memory access)
2599:
1644:
1629:
1291:
1281:
1276:
1236:
1138:
1133:
1113:
918:
893:
883:
674:
7941:"Samsung Begins Producing The Fastest GDDR6 Memory In The World"
2648:'s prefetch buffer size is 4n (four datawords per memory access)
1700:
varieties, for systems that require greater scalability such as
8232:
8117:
7803:"Micron Begins to Sample GDDR5X Memory, Unveils Specs of Chips"
7054:
5829:
5701:
5159:
5118:
5033:
4908:
4678:
4283:
4213:
3980:
3720:
3577:
3573:
3565:
3521:
3518:
model released in
December 1995, using the NEC μPD481850 chip.
3159:
2911:
2642:'s prefetch buffer size is 2n (two datawords per memory access)
2635:
Each generation of SDRAM has a different prefetch buffer size:
2200:
Precharge all: deactivate (close) the current row of all banks
2174:
Precharge: deactivate (close) the current row of selected bank
1558:(ICs) produced from the early 1970s to the early 1990s used an
1286:
1246:
1128:
1017:
815:
358:
7305:. 4 November 2003. Archived from the original on July 10, 2019
6819:"Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs"
2021:
Burst terminate: stop a burst read or burst write in progress
1600:
8240:
8185:
8180:
8147:
8132:
8112:
8100:
7995:
PC SDRAM Serial
Presence Detect (SPD) Specification, Rev 1.2B
6504:
6388:
5872:
5868:
5864:
5860:
5856:
5852:
5815:
5549:
5509:
5463:
5405:
5334:
5144:
4546:
4359:
4199:
3789:
3569:
3561:
3557:
3553:
3549:
3412:
3371:
CMD3=1 to transfer an 8-word burst; CMD3=0 for a 4-word burst
3197:
3143:
double the internal prefetch width again, but uses the same 8
2919:
2491:
1674:
1567:
1221:
1158:
1153:
1148:
810:
767:
761:
647:
627:
612:
6411:"Samsung hints to DDR4 with first validated 40 nm DRAM"
3666:. The reason given is: Advances in DDR5 need to be included.
30:"PC100" redirects here. For the Japanese home computer, see
8273:
8268:
8137:
8127:
7197:
7126:"Samsung Demonstrates World's First DDR 3 Memory Prototype"
5996:
5848:
5740:
5256:
5164:
4864:
4384:
4204:
3764:
3503:
3220:
3210:
name to Advanced Memory International, Inc.) SLDRAM was an
3129:
3007:
2969:
2896:
2850:
2629:
2602:
2325:
the dynamic (capacitive) memory storage cells of that row.
1656:
1609:
1216:
503:
153:
6385:"JEDEC Announces Key Attributes of Upcoming DDR4 Standard"
5942:
3090:
Again, with every doubling, the downside is the increased
2148:
Active (activate): open a row for read and write commands
1711:
Today, the world's largest manufacturers of SDRAM include
7591:
6788:
6732:
5190:
5101:
3827:
3703:
3499:
3408:
3407:
VCM was a proprietary type of SDRAM that was designed by
2606:
2099:
Write: write a burst of data to the currently active row
2047:
Read: read a burst of data from the currently active row
1659:
in modern computers, because of its greater performance.
1621:
1256:
1143:
913:
6483:"Samsung develops DDR4 memory, up to 40% more efficient"
6335:"Next-Generation DDR4 Memory to Reach 4.266GHz - Report"
2861:
never required for a read and a write at the same time.
1570:, the clock signal controls the stepping of an internal
8029:
6631:
6501:"JEDEC DDR5 & NVDIMM-P Standards Under Development"
6317:"heise online - IT-News, Nachrichten und Hintergründe"
2934:. It was superseded by the PC100 and PC133 standards.
2267:
Wider mode registers (DDR2 and up use 13 bits, A0–A12)
1836:
a strobe, but rather simply a command bit. Along with
7433:"Samsung 50nm 2GB DDR3 chips are industry's smallest"
7339:"Samsung Shows Industry's First 2-Gigabit DDR2 SDRAM"
5891:- Flash website built by Tel-Aviv University students
3402:
1790:, which are sampled on the rising edge of the clock:
1742:
622:
2983:
with PC66 and was superseded by the PC133 standard.
2521:
clock frequency to translate that limit into cycles.
6662:
128M-BIT VirtualChannel SDRAM preliminary datasheet
6565:
6031:
6029:
3454:
3392:, which always write in multiples of a cache line.
7151:
7149:
6299:"IDF: "DDR3 won't catch up with DDR2 during 2009""
6256:"G.SKILL Announces DDR3 Memory Kit For Ivy Bridge"
6146:
6144:
6142:
5898:, a master thesis from the University of Maryland.
3380:CMD0 selects the DCLK pair to use (DCLK1 or DCLK0)
2581:
1755:
1677:, an electronics industry association that adopts
6208:"Pipe Dreams: Six P35-DDR3 Motherboards Compared"
6205:
3691:Synchronous dynamic random-access memory (SDRAM)
3204:
2517:M8, M7: Operating mode. Reserved, and must be 00.
2261:Additional address bits to support larger devices
8327:
7391:ATI engineers by way of Beyond 3D's Dave Baumann
6253:
6026:
3498:HM5283206, introduced in November 1994, and the
2590:located on a common physical row in the memory.
1832:, row address strobe. Despite the name, this is
7146:
6377:
6362:(in German). hardware-infos.com. Archived from
6337:. Xbitlabs.com. August 16, 2010. Archived from
6153:"The outlook for DRAMs in consumer electronics"
6139:
1902:The SDR SDRAM commands are defined as follows:
7990:133 MHz PC133 SDRAM SO-DIMM Specification
7670:
7668:
7615:"16M-BIT SYNCHRONOUS GRAPHICS RAM: μPD4811650"
6511:
3611:(HBM) is a high-performance RAM interface for
3597:
2960:is a standard for internal removable computer
2774:Internal operations are at 1/2 the clock rate.
2290:is high, other commands are the same as above.
8015:
7827:
7825:
7234:
7232:
7230:
7228:
7226:
7224:
7222:
6873:
6871:
6869:
6867:
6865:
6241:"Super Talent & TEAM: DDR3-1600 Is Here!"
5803:
5725:
5689:
5447:
5413:
5240:
5176:
5133:
4695:
4006:
3966:
3350:5 or 4 bits spare for row or column expansion
2998:is a computer memory standard defined by the
2328:Once the row has been activated or "opened",
2294:
1505:
7394:
7083:
7081:
7079:
6927:
6925:
6813:
6811:
6809:
6690:
6688:
6608:(data sheet), pp. 32–33, archived from
3522:Graphics double data rate SDRAM (GDDR SDRAM)
3234:SLDRAM Read, write or row op request packet
2430:
7665:
7331:
7185:
7183:
7017:
7015:
6598:
5969:
3330:
3310:
3302:
3299:
3293:
3279:
2815:point-to-point (single module per channel)
8022:
8008:
7822:
7516:"Samsung Unleashes a Roomy DDR4 256GB RAM"
7219:
6896:
6862:
6777:
6775:
6721:
6719:
6238:
6049:(15–21). Hayden Publishing Company. 1993.
5970:Jacob, B.; Ng, S. W.; Wang, D. T. (2008).
5885:- EEPROM with timing data on SDRAM modules
3544:designed to be used as the main memory of
3361:A read/write command had the msbit clear:
2914:-based PCs. It also features in the Beige
1512:
1498:
7076:
6922:
6806:
6685:
6635:HYB39V64x0yT 64MBit Virtual Channel SDRAM
6569:HYSL8M18D600A 600 Mb/s/pin 8M x 18 SLDRAM
6542:
5915:
5083:Synchronous graphics random-access memory
3223:. (1 MT/s = 1000^2 transfers per second)
2466:will generally access memory in units of
7910:
7612:
7180:
7012:
6602:SLD4M18DR400 400 Mb/s/pin 4M x 18 SLDRAM
6075:
6073:
6071:
6069:
6067:
6065:
6063:
6061:
6059:
3487:nature of other video RAM technologies.
2948:
2825:
2298:
1599:
1533:Synchronous dynamic random-access memory
1523:
18:Synchronous Dynamic Random Access Memory
7916:
7363:
7120:
7118:
7116:
6989:
6987:
6985:
6772:
6716:
6408:
6110:"Nanya 256 Mb DDR SDRAM Datasheet"
5943:B. Jacob; S. W. Ng; D. T. Wang (2008).
2853:that read or write 64 (non-ECC) or 72 (
2402:
1880:
14:
8328:
7831:
7800:
7402:"Our Proud Heritage from 2000 to 2009"
6999:STOL (Semiconductor Technology Online)
6437:"DDR3 Will be Cheaper, Faster in 2009"
6434:
6409:Gruener, Wolfgang (February 4, 2009).
6150:
3192:
2887:refers to internal removable computer
2830:The 64 MB of sound memory on the
2282:of the activate command. A new signal
1889:
8003:
7459:"Our Proud Heritage from 2010 to Now"
6517:
6056:
5922:. John Wiley & Sons. p. 59.
5122:
5112:
3724:
3714:
3490:The earliest known SGRAM memory are 8
3374:CMD2=1 for a write, CMD2=0 for a read
1860:, this selects one of eight commands.
1844:, this selects one of eight commands.
1053:Vision Electronic Recording Apparatus
7371:"ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資"
7113:
6982:
6360:"IDF: DDR4 memory targeted for 2012"
6000:IEEE Journal of Solid-State Circuits
5126:
3728:
3648:
3637:Random-access memory § Timeline
3494:Mbit chips dating back to 1994: the
3420:. In the late 1990s, a number of PC
3184:
2942:For the Japanese home computer, see
2451:time, three cycles may be required.
7619:NEC Device Technology International
7548:"Hitachi HM5283206FP10 8Mbit SGRAM"
6859:page 118 "High-Bandwidth DRAM"
6658:
24:
7524:. 6 September 2018. Archived from
6566:Hyundai Electronics (1997-12-20),
6254:Jennifer Johnson (24 April 2012).
6226:"AMD to Adopt DDR3 in Three Years"
6206:Thomas Soderstrom (June 5, 2007).
3403:Virtual channel memory (VCM) SDRAM
2549:
1821:
1781:
214:Data validation and reconciliation
25:
8352:
7963:
5973:Memory Systems: Cache, DRAM, Disk
5946:Memory Systems: Cache, DRAM, Disk
3327:
3324:
3321:
3313:
2457:
2222:
2219:
2216:
2196:
2190:
2170:
2017:
2014:
2011:
1991:
1988:
1985:
1965:
1962:
1959:
1956:
1953:
1950:
1624:invented DDR SDRAM, they built a
264:Distributed file system for cloud
7917:Killian, Zak (18 January 2018).
7801:Shilov, Anton (March 29, 2016).
7381:from the original on 2016-08-13.
5976:. Morgan Kaufmann. p. 333.
5949:. Morgan Kaufmann. p. 324.
5851:(graphics DDR) and its subtypes
5076:
3653:
3455:Synchronous Graphics RAM (SGRAM)
2926:. It is also used in many early
2501:
112:Areal density (computer storage)
7985:PC SDRAM Specification, Rev 1.7
7933:
7884:
7853:
7832:Shilov, Anton (July 19, 2017).
7794:
7782:from the original on 2022-01-24
7758:
7726:
7700:
7633:
7606:
7578:
7566:from the original on 2003-07-16
7540:
7508:
7482:
7451:
7425:
7385:
7297:"Elpida ships 2GB DDR2 modules"
7289:
7257:
7207:from the original on 2017-02-27
7064:from the original on 2019-06-21
7040:
6961:
6949:from the original on 2019-06-21
6843:
6784:NEC Application Specific Memory
6747:
6675:from the original on 2013-12-03
6652:
6648:from the original on 2018-11-12
6625:
6592:
6559:
6536:
6493:
6475:
6454:
6439:. dailytech.com. Archived from
6435:Jansen, Ng (January 20, 2009).
6428:
6402:
6352:
6327:
6309:
6291:
6273:
6262:
6247:
6232:
6218:
6199:
6185:
6170:
3296:
3285:
3282:
3276:
3128:The DDR4 chips run at 1.2
3116:DDR4 SDRAM is the successor to
2832:Sound Blaster X-Fi Fatality Pro
2582:DDR SDRAM prefetch architecture
2536:
2462:A modern microprocessor with a
2239:
2236:
2233:
2230:
2213:
2210:
2207:
2204:
2193:
2187:
2184:
2181:
2178:
2167:
2161:
2158:
2155:
2152:
2138:
2135:
2132:
2129:
2118:
2112:
2109:
2106:
2103:
2092:
2086:
2083:
2080:
2077:
2066:
2060:
2057:
2054:
2051:
2040:
2034:
2031:
2028:
2025:
2008:
2005:
2002:
1999:
1982:
1979:
1976:
1973:
1969:Command inhibit (no operation)
1947:
931:Programmable metallization cell
6281:"DDR4 not expected until 2015"
6130:
6102:
5990:
5963:
5936:
5909:
3645:Transistor count § Memory
3424:chipsets (such as the popular
3205:Synchronous-link DRAM (SLDRAM)
2953:DIMM: 168 pins and two notches
2670:
494:Persistence (computer science)
13:
1:
8304:
6632:Siemens Semiconductor Group,
6413:. tgdaily.com. Archived from
5902:
3514:, starting with the Japanese
1362:Electronic quantum holography
8031:Dynamic random-access memory
7981:, May 2011, Hardware Secrets
6978:. February 1996. p. 40.
6575:(data sheet), archived from
6239:Wesly Fink (July 20, 2007).
6151:Graham, Allan (2007-01-12).
3641:Flash memory § Timeline
3471:. It adds functions such as
3428:) included VCSDRAM support.
3347:10 or 11 bits of row address
3042:DDR SDRAM (sometimes called
713:Video RAM (dual-ported DRAM)
509:Non-RAID drive architectures
7:
7766:"K4W1G1646G-BC08 Datasheet"
5842:
3630:
3598:High Bandwidth Memory (HBM)
3540:) is a type of specialized
2930:systems with a 66 MHz
2845:Originally simply known as
2303:SDRAM memory module, zoomed
2264:Additional bank select bits
1897:
1868:, write enable. Along with
1696:SDRAM is also available in
10:
8357:
6599:SLDRAM Inc. (1998-07-09),
6518:Smith, Ryan (2020-07-14).
3634:
3601:
3525:
3451:(256 bytes) in a segment.
3173:
3109:
3079:
3057:
3026:
2941:
2906:This standard was used by
2798:Much longer CAS latencies
2295:Construction and operation
2248:
2225:
2199:
2173:
2147:
2124:
2098:
2072:
2046:
2020:
1994:
1968:
1595:
1302:Holographic Versatile Disc
1201:Compact Disc Digital Audio
1073:Magnetic-tape data storage
692:Content-addressable memory
29:
8292:
8259:
8231:
8163:
8059:
8038:
7979:Understanding RAM Timings
7323:: CS1 maint: unfit URL (
5878:List of device bandwidths
5660:
5653:
5650:
5643:
5638:
5530:
5523:
5520:
5399:
5392:
5389:
5382:
5379:
5373:
5366:
5363:
5009:
5006:
4827:
4824:
4804:
4797:
4794:
4769:
4766:
4728:
4656:
4649:
4646:
4528:
4411:
4408:
4373:
4341:
4230:
4227:
4122:
4119:
4052:
4049:
3779:
3662:This section needs to be
3546:graphics processing units
3120:. It was revealed at the
2802:
2784:
2765:"Burst terminate" removed
2757:
2714:
2688:
2683:
2680:
2494:for its microprocessors.
2431:Interrupting a read burst
2280:DDR4 changes the encoding
2245:
2144:
1730:
1647:) followed soon after by
499:Persistent data structure
394:Digital rights management
6904:"KM48SL2000-7 Datasheet"
6543:Dean Kent (1998-10-24),
6099:based on powers of 1024.
3685:
3353:7 bits of column address
2990:
2937:
2891:standard defined by the
2767:4 units used in parallel
2621:in multiple data words.
1374:DNA digital data storage
1357:Holographic data storage
846:Solid-state hybrid drive
132:Network-attached storage
8341:South Korean inventions
7556:Smithsonian Institution
6968:"Ultra 64 Tech Specs".
3169:
3105:
3075:
3053:
2879:
1812:data mask. (The letter
1537:synchronous dynamic RAM
1369:5D optical data storage
1186:3D optical data storage
909:Universal Flash Storage
314:Replication (computing)
259:Distributed file system
149:Single-instance storage
127:Direct-attached storage
107:Continuous availability
27:Type of computer memory
7708:"K4D553238F Datasheet"
7613:Takeuchi, Kei (1998).
7375:pc.watch.impress.co.jp
6933:"MSM5718C50/MD5764802"
5883:Serial presence detect
3344:3 bits of bank address
3022:
2954:
2870:extended data out DRAM
2842:
2821:
2304:
1757:
1756:{\displaystyle 10^{6}}
1613:
1529:
1242:Nintendo optical discs
459:Storage virtualization
329:Information repository
269:Distributed data store
7866:Samsung Semiconductor
7739:Samsung Semiconductor
7646:Samsung Semiconductor
7464:Samsung Semiconductor
7407:Samsung Semiconductor
7344:Samsung Semiconductor
7270:Samsung Semiconductor
6791:. Fall 1995. p.
6464:. Samsung. 2011-01-04
6193:"What is DDR memory?"
5094:Date of introduction
5087:High Bandwidth Memory
3696:Date of introduction
3609:High Bandwidth Memory
3604:High Bandwidth Memory
3122:Intel Developer Forum
3019:with PC100 and PC66.
2952:
2829:
2302:
1766:Another limit is the
1758:
1608:SDRAM ICs on a PC100
1603:
1527:
745:Mellon optical memory
733:Williams–Kilburn tube
449:Locality of reference
254:Clustered file system
80:Memory access pattern
7587:UPD4811650 Datasheet
6341:on December 19, 2010
6178:"SDRAM Part Catalog"
3162:at 1.2 V, uses
2962:random-access memory
2403:Command interactions
1881:Bank selection (BAn)
1740:
1572:finite-state machine
1441:Magnetic-core memory
1088:Digital Data Storage
1048:Quadruplex videotape
489:In-memory processing
379:Information transfer
274:Distributed database
137:Storage area network
117:Block (data storage)
7773:Samsung Electronics
7712:Samsung Electronics
7681:Samsung Electronics
7439:. 29 September 2008
7351:. 20 September 2004
7162:Samsung Electronics
7094:Samsung Electronics
6831:. 17 September 1998
6824:Samsung Electronics
6728:μPD481850 Datasheet
6697:HM5283206 Datasheet
6228:. 28 November 2005.
6037:"Electronic Design"
6012:1990IJSSC..25.1118K
5090:
3692:
3592:Samsung Electronics
3426:VIA KX133 and KT133
3338:9 bits of device ID
3235:
3193:Rambus DRAM (RDRAM)
3017:backward compatible
2981:backward compatible
2874:fast page mode DRAM
2677:
2481:For the sequential
1890:Addressing (A10/An)
1713:Samsung Electronics
1649:Hyundai Electronics
1556:integrated circuits
1528:SDRAM memory module
1038:Phonograph cylinder
976:Electrochemical RAM
828:Solid-state storage
444:Memory segmentation
142:Block-level storage
8155:Hybrid Memory Cube
7898:. January 18, 2018
7746:. October 26, 2005
7200:. April 21, 2003.
7134:. 17 February 2005
7101:. 10 February 1999
6855:2015-02-06 at the
6704:. 11 November 1994
5916:P. Darche (2020).
5081:
3690:
3512:video game console
3233:
3150:In February 2009,
3002:. PC133 refers to
2955:
2857:) bits at a time.
2843:
2837:is built from two
2790:Access is ≥8 words
2763:Access is ≥4 words
2723:Access is ≥2 words
2676:SDRAM feature map
2675:
2305:
1753:
1626:dual-edge clocking
1620:In the late 1980s
1614:
1530:
1447:Plated-wire memory
1412:Paper data storage
1058:Magnetic recording
484:In-memory database
469:Memory-mapped file
414:Volume boot record
409:Master boot record
399:Volume (computing)
374:Data communication
299:Data deduplication
8323:
8322:
7947:. 18 January 2018
7775:. November 2010.
7277:. 29 January 2003
7057:. 12 March 1998.
6942:. February 1999.
6940:Oki Semiconductor
6850:ISSCC 2014 Trends
6735:. 6 December 1994
6546:RAM Guide: SLDRAM
6503:(Press release).
6489:. 4 January 2011.
6387:(Press release).
6287:. 16 August 2010.
6182:070928 micron.com
6159:. AspenCore Media
6042:Electronic Design
5840:
5839:
5074:
5073:
3683:
3682:
3418:memory controller
3341:6 bits of command
3335:
3334:
3185:Failed successors
3164:pseudo open drain
2964:, defined by the
2819:
2818:
2394:delay between an
2255:
2254:
1721:Micron Technology
1522:
1521:
1119:8 mm video format
1043:Phonograph record
862:Flash Core Module
840:Solid-state drive
739:Delay-line memory
698:Computational RAM
601:Scratchpad memory
439:Disk partitioning
164:Unstructured data
90:Secondary storage
16:(Redirected from
8348:
8315:Transistor count
8024:
8017:
8010:
8001:
8000:
7957:
7956:
7954:
7952:
7937:
7931:
7930:
7928:
7926:
7914:
7908:
7907:
7905:
7903:
7888:
7882:
7881:
7879:
7877:
7857:
7851:
7850:
7848:
7846:
7829:
7820:
7819:
7817:
7815:
7798:
7792:
7791:
7789:
7787:
7781:
7770:
7762:
7756:
7755:
7753:
7751:
7730:
7724:
7723:
7721:
7719:
7704:
7698:
7697:
7695:
7693:
7688:. 28 August 2003
7672:
7663:
7662:
7660:
7658:
7637:
7631:
7630:
7628:
7626:
7610:
7604:
7603:
7601:
7599:
7582:
7576:
7575:
7573:
7571:
7565:
7552:
7544:
7538:
7537:
7535:
7533:
7528:on June 21, 2019
7512:
7506:
7505:
7503:
7501:
7486:
7480:
7479:
7477:
7475:
7455:
7449:
7448:
7446:
7444:
7429:
7423:
7422:
7420:
7418:
7398:
7392:
7389:
7383:
7382:
7367:
7361:
7360:
7358:
7356:
7335:
7329:
7328:
7322:
7314:
7312:
7310:
7293:
7287:
7286:
7284:
7282:
7261:
7255:
7254:
7252:
7250:
7240:"History: 2000s"
7236:
7217:
7216:
7214:
7212:
7206:
7195:
7187:
7178:
7177:
7175:
7173:
7153:
7144:
7143:
7141:
7139:
7122:
7111:
7110:
7108:
7106:
7085:
7074:
7073:
7071:
7069:
7063:
7052:
7044:
7038:
7037:
7035:
7033:
7023:"History: 1990s"
7019:
7010:
7009:
7007:
7005:
6991:
6980:
6979:
6965:
6959:
6958:
6956:
6954:
6948:
6937:
6929:
6920:
6919:
6917:
6915:
6900:
6894:
6893:
6891:
6889:
6879:"History: 2010s"
6875:
6860:
6847:
6841:
6840:
6838:
6836:
6815:
6804:
6803:
6801:
6799:
6779:
6770:
6769:
6767:
6765:
6751:
6745:
6744:
6742:
6740:
6723:
6714:
6713:
6711:
6709:
6692:
6683:
6682:
6681:
6680:
6674:
6667:
6656:
6650:
6649:
6647:
6640:
6629:
6623:
6622:
6621:
6620:
6614:
6607:
6596:
6590:
6589:
6588:
6587:
6581:
6574:
6563:
6557:
6556:
6555:
6554:
6549:, Tom's Hardware
6540:
6534:
6533:
6531:
6530:
6515:
6509:
6508:
6507:. 30 March 2017.
6497:
6491:
6490:
6479:
6473:
6472:
6470:
6469:
6458:
6452:
6451:
6449:
6448:
6443:on June 22, 2009
6432:
6426:
6425:
6423:
6422:
6406:
6400:
6399:
6397:
6396:
6381:
6375:
6374:
6372:
6371:
6356:
6350:
6349:
6347:
6346:
6331:
6325:
6324:
6313:
6307:
6306:
6295:
6289:
6288:
6285:semiaccurate.com
6277:
6271:
6269:DDR4 PDF page 23
6266:
6260:
6259:
6251:
6245:
6244:
6236:
6230:
6229:
6222:
6216:
6215:
6203:
6197:
6196:
6189:
6183:
6181:
6174:
6168:
6167:
6165:
6164:
6148:
6137:
6134:
6128:
6127:
6125:
6124:
6114:
6106:
6100:
6077:
6054:
6053:
6033:
6024:
6023:
5994:
5988:
5987:
5967:
5961:
5960:
5940:
5934:
5933:
5913:
5805:
5727:
5691:
5449:
5415:
5242:
5178:
5135:
5128:
5110:Manufacturer(s)
5091:
5080:
4697:
4008:
3968:
3730:
3712:Manufacturer(s)
3693:
3689:
3678:
3675:
3669:
3657:
3656:
3649:
3586:
3534:double data rate
3493:
3236:
3232:
3036:double data rate
2814:
2771:
2742:
2737:
2701:
2684:Feature changes
2678:
2674:
2605:device is 2,048
2507:register write.
2289:
2285:
1925:
1920:
1915:
1910:
1905:
1904:
1875:
1871:
1866:
1859:
1855:
1850:
1843:
1839:
1830:
1804:
1762:
1760:
1759:
1754:
1752:
1751:
1725:Nanya Technology
1643:
1636:SDRAM, known as
1634:double data rate
1514:
1507:
1500:
1459:Thin-film memory
1453:Core rope memory
1379:Universal memory
1342:Millipede memory
1332:Racetrack memory
1297:Ultra HD Blu-ray
1109:Linear Tape-Open
1063:Magnetic storage
1031:Analog recording
474:Software entropy
434:Disk aggregation
194:Data degradation
179:Data compression
75:Memory hierarchy
65:Memory coherence
37:
36:
21:
8356:
8355:
8351:
8350:
8349:
8347:
8346:
8345:
8326:
8325:
8324:
8319:
8288:
8255:
8227:
8159:
8107:Fast Cycle DRAM
8055:
8034:
8028:
7972:, August 2010,
7966:
7961:
7960:
7950:
7948:
7939:
7938:
7934:
7924:
7922:
7915:
7911:
7901:
7899:
7890:
7889:
7885:
7875:
7873:
7859:
7858:
7854:
7844:
7842:
7830:
7823:
7813:
7811:
7799:
7795:
7785:
7783:
7779:
7768:
7764:
7763:
7759:
7749:
7747:
7732:
7731:
7727:
7717:
7715:
7706:
7705:
7701:
7691:
7689:
7674:
7673:
7666:
7656:
7654:
7639:
7638:
7634:
7624:
7622:
7611:
7607:
7597:
7595:
7594:. December 1997
7584:
7583:
7579:
7569:
7567:
7563:
7550:
7546:
7545:
7541:
7531:
7529:
7514:
7513:
7509:
7499:
7497:
7496:. July 17, 2018
7488:
7487:
7483:
7473:
7471:
7457:
7456:
7452:
7442:
7440:
7431:
7430:
7426:
7416:
7414:
7400:
7399:
7395:
7390:
7386:
7369:
7368:
7364:
7354:
7352:
7337:
7336:
7332:
7316:
7315:
7308:
7306:
7295:
7294:
7290:
7280:
7278:
7263:
7262:
7258:
7248:
7246:
7238:
7237:
7220:
7210:
7208:
7204:
7193:
7189:
7188:
7181:
7171:
7169:
7155:
7154:
7147:
7137:
7135:
7124:
7123:
7114:
7104:
7102:
7087:
7086:
7077:
7067:
7065:
7061:
7050:
7046:
7045:
7041:
7031:
7029:
7021:
7020:
7013:
7003:
7001:
6993:
6992:
6983:
6974:. No. 14.
6971:Next Generation
6967:
6966:
6962:
6952:
6950:
6946:
6935:
6931:
6930:
6923:
6913:
6911:
6902:
6901:
6897:
6887:
6885:
6877:
6876:
6863:
6857:Wayback Machine
6848:
6844:
6834:
6832:
6817:
6816:
6807:
6797:
6795:
6781:
6780:
6773:
6763:
6761:
6753:
6752:
6748:
6738:
6736:
6725:
6724:
6717:
6707:
6705:
6694:
6693:
6686:
6678:
6676:
6672:
6665:
6657:
6653:
6645:
6638:
6630:
6626:
6618:
6616:
6612:
6605:
6597:
6593:
6585:
6583:
6579:
6572:
6564:
6560:
6552:
6550:
6541:
6537:
6528:
6526:
6516:
6512:
6499:
6498:
6494:
6481:
6480:
6476:
6467:
6465:
6460:
6459:
6455:
6446:
6444:
6433:
6429:
6420:
6418:
6417:on May 24, 2009
6407:
6403:
6394:
6392:
6383:
6382:
6378:
6369:
6367:
6358:
6357:
6353:
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6332:
6328:
6315:
6314:
6310:
6297:
6296:
6292:
6279:
6278:
6274:
6267:
6263:
6252:
6248:
6237:
6233:
6224:
6223:
6219:
6204:
6200:
6191:
6190:
6186:
6176:
6175:
6171:
6162:
6160:
6149:
6140:
6135:
6131:
6122:
6120:
6112:
6108:
6107:
6103:
6097:binary prefixes
6078:
6057:
6035:
6034:
6027:
6020:10.1109/4.62132
5995:
5991:
5984:
5968:
5964:
5957:
5941:
5937:
5930:
5914:
5910:
5905:
5845:
5079:
3688:
3679:
3673:
3670:
3667:
3658:
3654:
3647:
3633:
3606:
3600:
3590:memory chip by
3584:
3530:
3524:
3491:
3457:
3405:
3311:Row (continued)
3207:
3195:
3187:
3178:
3172:
3114:
3108:
3084:
3078:
3062:
3056:
3031:
3025:
2993:
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2940:
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2812:
2808:
2797:
2791:
2775:
2773:
2769:
2768:
2766:
2764:
2753:
2740:
2735:
2731:
2710:
2699:
2695:
2673:
2584:
2565:
2552:
2550:Low power modes
2545:
2539:
2504:
2460:
2433:
2423:
2419:
2415:
2411:
2405:
2393:
2386:
2344:command, and a
2339:
2297:
2287:
2283:
2250:
1923:
1918:
1913:
1908:
1900:
1892:
1883:
1873:
1869:
1864:
1857:
1853:
1848:
1841:
1837:
1828:
1824:
1822:Command signals
1802:
1784:
1782:Control signals
1747:
1743:
1741:
1738:
1737:
1733:
1641:
1598:
1518:
1489:
1488:
1407:
1399:
1398:
1352:Patterned media
1322:
1314:
1313:
1181:
1171:
1170:
1166:Hard disk drive
1033:
1023:
1022:
1003:
992:
991:
946:
936:
935:
857:IBM FlashSystem
852:USB flash drive
791:
774:
773:
728:
720:
719:
708:Dual-ported RAM
586:
569:
568:
529:Cloud computing
389:Copy protection
309:Data redundancy
239:Shared resource
209:Data validation
184:Data corruption
159:Structured data
70:Cache coherence
55:
41:Computer memory
35:
28:
23:
22:
15:
12:
11:
5:
8354:
8344:
8343:
8338:
8321:
8320:
8318:
8317:
8312:
8307:
8305:SDRAM timeline
8302:
8296:
8294:
8290:
8289:
8287:
8286:
8281:
8276:
8271:
8265:
8263:
8261:Memory modules
8257:
8256:
8254:
8253:
8248:
8243:
8237:
8235:
8229:
8228:
8226:
8225:
8224:
8223:
8218:
8213:
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8203:
8198:
8193:
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8178:
8173:
8167:
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8150:
8145:
8140:
8135:
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8115:
8110:
8104:
8098:
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8096:
8091:
8086:
8081:
8071:
8065:
8063:
8057:
8056:
8054:
8053:
8048:
8042:
8040:
8036:
8035:
8027:
8026:
8019:
8012:
8004:
7998:
7997:
7992:
7987:
7982:
7976:
7965:
7964:External links
7962:
7959:
7958:
7932:
7909:
7883:
7852:
7821:
7793:
7757:
7725:
7699:
7664:
7653:. 12 July 1999
7632:
7605:
7577:
7539:
7521:Tom's Hardware
7507:
7481:
7450:
7424:
7393:
7384:
7362:
7330:
7288:
7256:
7218:
7179:
7145:
7112:
7075:
7048:"Direct RDRAM"
7039:
7011:
6981:
6960:
6921:
6895:
6861:
6842:
6805:
6771:
6746:
6715:
6684:
6651:
6624:
6591:
6558:
6535:
6510:
6492:
6474:
6453:
6427:
6401:
6376:
6351:
6326:
6308:
6290:
6272:
6261:
6246:
6231:
6217:
6212:Tom's Hardware
6198:
6184:
6169:
6138:
6129:
6101:
6055:
6025:
5989:
5982:
5962:
5955:
5935:
5928:
5907:
5906:
5904:
5901:
5900:
5899:
5892:
5889:SDRAM Tutorial
5886:
5880:
5875:
5844:
5841:
5838:
5837:
5835:
5832:
5827:
5822:
5819:
5812:
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5735:
5728:
5722:
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5719:
5716:
5713:
5710:
5705:
5698:
5695:
5694:MT58K256M32JA
5692:
5686:
5685:
5680:
5673:
5666:
5662:
5661:
5659:
5652:
5649:
5642:
5637:
5636:SGRAM (GDDR3)
5634:
5631:
5624:
5620:
5619:
5617:
5614:
5611:
5604:
5601:
5600:SGRAM (GDDR3)
5598:
5595:
5592:
5588:
5587:
5582:
5579:
5578:SGRAM (GDDR5)
5576:
5573:
5566:
5562:
5561:
5556:
5553:
5546:
5543:
5536:
5532:
5531:
5529:
5522:
5519:
5512:
5507:
5506:SGRAM (GDDR4)
5504:
5501:
5494:
5490:
5489:
5487:
5480:
5477:
5470:
5467:
5460:
5457:
5450:
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5443:
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5422:
5419:
5416:
5410:
5409:
5401:
5400:
5398:
5391:
5388:
5381:
5378:
5377:SGRAM (GDDR2)
5375:
5372:
5365:
5361:
5360:
5358:
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5348:
5341:
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5331:
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5289:
5285:
5284:
5282:
5275:
5272:
5265:
5260:
5253:
5250:
5243:
5241:September 1998
5237:
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4549:
4544:
4543:Sony, Toshiba
4541:
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4525:
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4516:
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4507:
4504:
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4396:
4393:
4390:
4387:
4382:
4379:
4371:
4370:
4368:
4365:
4362:
4357:
4356:Sony, Toshiba
4354:
4351:
4348:
4343:
4339:
4338:
4336:
4329:
4326:
4319:
4316:
4313:
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3990:
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3807:
3804:
3797:
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3723:
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3710:
3707:
3700:
3697:
3687:
3684:
3681:
3680:
3661:
3659:
3652:
3632:
3629:
3602:Main article:
3599:
3596:
3526:Main article:
3523:
3520:
3461:texture memory
3456:
3453:
3404:
3401:
3382:
3381:
3378:
3375:
3372:
3369:
3366:
3355:
3354:
3351:
3348:
3345:
3342:
3339:
3333:
3332:
3329:
3326:
3323:
3320:
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3312:
3309:
3305:
3304:
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3298:
3295:
3292:
3288:
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3281:
3278:
3275:
3271:
3270:
3267:
3264:
3261:
3258:
3255:
3252:
3249:
3246:
3243:
3240:
3206:
3203:
3194:
3191:
3186:
3183:
3174:Main article:
3171:
3168:
3134:data transfers
3110:Main article:
3107:
3104:
3080:Main article:
3077:
3074:
3058:Main article:
3055:
3052:
3027:Main article:
3024:
3021:
2992:
2989:
2939:
2936:
2881:
2878:
2872:(EDO-RAM) and
2823:
2820:
2817:
2816:
2810:
2806:
2800:
2799:
2788:
2782:
2781:
2761:
2755:
2754:
2752:
2751:
2744:
2738:
2733:
2729:
2727:Double clocked
2724:
2720:
2718:
2712:
2711:
2709:
2708:
2702:
2697:
2692:
2690:
2686:
2685:
2682:
2672:
2669:
2668:
2667:
2661:
2655:
2649:
2643:
2583:
2580:
2563:
2551:
2548:
2543:
2538:
2535:
2530:
2529:
2525:
2522:
2518:
2515:
2503:
2500:
2459:
2458:Burst ordering
2456:
2432:
2429:
2421:
2417:
2413:
2409:
2404:
2401:
2391:
2384:
2337:
2296:
2293:
2292:
2291:
2277:
2274:
2271:
2268:
2265:
2262:
2253:
2252:
2247:
2244:
2241:
2238:
2235:
2232:
2228:
2227:
2224:
2221:
2218:
2215:
2212:
2209:
2206:
2202:
2201:
2198:
2195:
2192:
2189:
2186:
2183:
2180:
2176:
2175:
2172:
2169:
2166:
2163:
2160:
2157:
2154:
2150:
2149:
2146:
2143:
2140:
2137:
2134:
2131:
2127:
2126:
2123:
2120:
2117:
2114:
2111:
2108:
2105:
2101:
2100:
2097:
2094:
2091:
2088:
2085:
2082:
2079:
2075:
2074:
2071:
2068:
2065:
2062:
2059:
2056:
2053:
2049:
2048:
2045:
2042:
2039:
2036:
2033:
2030:
2027:
2023:
2022:
2019:
2016:
2013:
2010:
2007:
2004:
2001:
1997:
1996:
1993:
1990:
1987:
1984:
1981:
1978:
1975:
1971:
1970:
1967:
1964:
1961:
1958:
1955:
1952:
1949:
1945:
1944:
1941:
1935:
1932:
1926:
1921:
1916:
1911:
1899:
1896:
1891:
1888:
1882:
1879:
1878:
1877:
1861:
1845:
1823:
1820:
1819:
1818:
1807:
1799:
1783:
1780:
1750:
1746:
1732:
1729:
1679:open standards
1664:burst EDO DRAM
1597:
1594:
1520:
1519:
1517:
1516:
1509:
1502:
1494:
1491:
1490:
1487:
1486:
1480:
1474:
1471:Twistor memory
1468:
1462:
1456:
1450:
1444:
1438:
1432:
1427:
1421:
1415:
1408:
1405:
1404:
1401:
1400:
1397:
1396:
1391:
1389:Quantum memory
1386:
1381:
1376:
1371:
1366:
1365:
1364:
1354:
1349:
1344:
1339:
1334:
1329:
1323:
1321:In development
1320:
1319:
1316:
1315:
1312:
1311:
1306:
1305:
1304:
1299:
1294:
1289:
1284:
1279:
1274:
1269:
1264:
1259:
1254:
1249:
1244:
1239:
1234:
1232:Super Video CD
1229:
1224:
1219:
1214:
1209:
1204:
1198:
1193:
1182:
1177:
1176:
1173:
1172:
1169:
1168:
1163:
1162:
1161:
1156:
1151:
1146:
1141:
1136:
1131:
1126:
1121:
1116:
1111:
1106:
1101:
1096:
1091:
1085:
1080:
1075:
1070:
1065:
1055:
1050:
1045:
1040:
1034:
1029:
1028:
1025:
1024:
1021:
1020:
1015:
1010:
1004:
998:
997:
994:
993:
990:
989:
984:
979:
973:
968:
958:
953:
947:
942:
941:
938:
937:
934:
933:
928:
927:
926:
921:
916:
911:
906:
901:
896:
891:
889:MultiMediaCard
886:
881:
876:
866:
865:
864:
859:
854:
849:
843:
837:
825:
820:
819:
818:
813:
803:
798:
792:
787:
786:
783:
782:
776:
775:
772:
771:
765:
759:
754:
751:Selectron tube
748:
742:
736:
729:
726:
725:
722:
721:
718:
717:
716:
715:
705:
700:
695:
689:
684:
679:
678:
677:
667:
666:
665:
660:
655:
650:
645:
640:
635:
630:
625:
620:
615:
605:
604:
603:
598:
591:Hardware cache
587:
582:
581:
578:
577:
571:
570:
567:
566:
561:
556:
551:
546:
544:Edge computing
541:
536:
531:
526:
524:Grid computing
521:
519:Bank switching
516:
511:
506:
501:
496:
491:
486:
481:
476:
471:
466:
464:Virtual memory
461:
456:
451:
446:
441:
436:
431:
429:Disk mirroring
426:
421:
416:
411:
406:
401:
396:
391:
386:
384:Temporary file
381:
376:
371:
366:
361:
356:
351:
346:
341:
336:
334:Knowledge base
331:
326:
324:Storage record
321:
319:Memory refresh
316:
311:
306:
304:Data structure
301:
296:
291:
286:
281:
276:
271:
266:
261:
256:
251:
246:
241:
236:
231:
226:
221:
216:
211:
206:
201:
199:Data integrity
196:
191:
189:Data cleansing
186:
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122:Object storage
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8300:DRAM timeline
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7921:. Tech Report
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6910:. August 1992
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6615:on 2012-04-26
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6582:on 2012-04-26
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5177:December 1994
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5134:November 1994
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3971:Direct RDRAM
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3674:December 2023
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2928:Intel Celeron
2925:
2924:PowerBook G3s
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2908:Intel Pentium
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2063:
2050:
2043:
2037:
2024:
1998:
1995:No operation
1972:
1946:
1942:
1940:
1936:
1933:
1931:
1927:
1922:
1917:
1912:
1907:
1906:
1903:
1895:
1887:
1867:
1862:
1851:
1846:
1835:
1831:
1826:
1825:
1815:
1811:
1808:
1805:
1800:
1796:
1793:
1792:
1791:
1789:
1779:
1775:
1771:
1769:
1764:
1748:
1744:
1728:
1726:
1722:
1718:
1714:
1709:
1707:
1703:
1699:
1694:
1692:
1688:
1684:
1680:
1676:
1671:
1669:
1665:
1660:
1658:
1654:
1650:
1646:
1639:
1635:
1631:
1627:
1623:
1618:
1611:
1607:
1602:
1593:
1590:
1586:
1584:
1580:
1579:
1573:
1569:
1565:
1561:
1557:
1552:
1550:
1546:
1542:
1538:
1534:
1526:
1515:
1510:
1508:
1503:
1501:
1496:
1495:
1493:
1492:
1484:
1481:
1478:
1477:Bubble memory
1475:
1472:
1469:
1466:
1463:
1460:
1457:
1454:
1451:
1448:
1445:
1442:
1439:
1436:
1433:
1431:
1428:
1425:
1422:
1419:
1416:
1413:
1410:
1409:
1403:
1402:
1395:
1392:
1390:
1387:
1385:
1382:
1380:
1377:
1375:
1372:
1370:
1367:
1363:
1360:
1359:
1358:
1355:
1353:
1350:
1348:
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1343:
1340:
1338:
1335:
1333:
1330:
1328:
1325:
1324:
1318:
1317:
1310:
1307:
1303:
1300:
1298:
1295:
1293:
1290:
1288:
1285:
1283:
1280:
1278:
1275:
1273:
1270:
1268:
1265:
1263:
1260:
1258:
1255:
1253:
1250:
1248:
1245:
1243:
1240:
1238:
1235:
1233:
1230:
1228:
1225:
1223:
1220:
1218:
1215:
1213:
1210:
1208:
1205:
1202:
1199:
1197:
1194:
1192:
1189:
1188:
1187:
1184:
1183:
1180:
1175:
1174:
1167:
1164:
1160:
1157:
1155:
1152:
1150:
1147:
1145:
1142:
1140:
1137:
1135:
1132:
1130:
1127:
1125:
1122:
1120:
1117:
1115:
1112:
1110:
1107:
1105:
1104:Cassette tape
1102:
1100:
1099:Videocassette
1097:
1095:
1092:
1089:
1086:
1084:
1081:
1079:
1076:
1074:
1071:
1069:
1068:Magnetic tape
1066:
1064:
1061:
1060:
1059:
1056:
1054:
1051:
1049:
1046:
1044:
1041:
1039:
1036:
1035:
1032:
1027:
1026:
1019:
1016:
1014:
1011:
1009:
1006:
1005:
1002:
996:
995:
988:
985:
983:
980:
977:
974:
972:
969:
966:
962:
959:
957:
954:
952:
949:
948:
945:
940:
939:
932:
929:
925:
922:
920:
917:
915:
912:
910:
907:
905:
902:
900:
897:
895:
892:
890:
887:
885:
882:
880:
877:
875:
872:
871:
870:
867:
863:
860:
858:
855:
853:
850:
847:
844:
841:
838:
835:
832:
831:
829:
826:
824:
823:ROM cartridge
821:
817:
814:
812:
809:
808:
807:
804:
802:
799:
797:
794:
793:
790:
785:
784:
781:
778:
777:
769:
766:
763:
760:
758:
755:
752:
749:
746:
743:
740:
737:
734:
731:
730:
724:
723:
714:
711:
710:
709:
706:
704:
701:
699:
696:
693:
690:
688:
685:
683:
680:
676:
673:
672:
671:
668:
664:
661:
659:
656:
654:
651:
649:
646:
644:
641:
639:
636:
634:
631:
629:
626:
624:
621:
619:
616:
614:
611:
610:
609:
606:
602:
599:
597:
594:
593:
592:
589:
588:
585:
580:
579:
576:
573:
572:
565:
562:
560:
557:
555:
552:
550:
549:Dew computing
547:
545:
542:
540:
539:Fog computing
537:
535:
534:Cloud storage
532:
530:
527:
525:
522:
520:
517:
515:
514:Memory paging
512:
510:
507:
505:
502:
500:
497:
495:
492:
490:
487:
485:
482:
480:
477:
475:
472:
470:
467:
465:
462:
460:
457:
455:
452:
450:
447:
445:
442:
440:
437:
435:
432:
430:
427:
425:
422:
420:
417:
415:
412:
410:
407:
405:
402:
400:
397:
395:
392:
390:
387:
385:
382:
380:
377:
375:
372:
370:
367:
365:
362:
360:
357:
355:
352:
350:
349:File deletion
347:
345:
342:
340:
339:Computer file
337:
335:
332:
330:
327:
325:
322:
320:
317:
315:
312:
310:
307:
305:
302:
300:
297:
295:
292:
290:
287:
285:
282:
280:
277:
275:
272:
270:
267:
265:
262:
260:
257:
255:
252:
250:
247:
245:
242:
240:
237:
235:
232:
230:
227:
225:
222:
220:
219:Data recovery
217:
215:
212:
210:
207:
205:
204:Data security
202:
200:
197:
195:
192:
190:
187:
185:
182:
180:
177:
175:
172:
170:
167:
165:
162:
160:
157:
155:
152:
150:
147:
143:
140:
138:
135:
134:
133:
130:
128:
125:
123:
120:
118:
115:
113:
110:
108:
105:
101:
100:floating-gate
98:
97:
96:
93:
91:
88:
86:
83:
81:
78:
76:
73:
71:
68:
66:
63:
61:
58:
57:
51:
50:
46:
42:
39:
38:
33:
19:
8103:(Mobile DDR)
8068:
8060:
8039:Asynchronous
7949:. Retrieved
7944:
7935:
7923:. Retrieved
7912:
7900:. Retrieved
7886:
7874:. Retrieved
7864:
7855:
7843:. Retrieved
7837:
7812:. Retrieved
7806:
7796:
7784:. Retrieved
7760:
7748:. Retrieved
7737:
7728:
7716:. Retrieved
7714:. March 2005
7702:
7690:. Retrieved
7679:
7655:. Retrieved
7644:
7635:
7623:. Retrieved
7618:
7608:
7596:. Retrieved
7586:
7580:
7568:. Retrieved
7554:
7542:
7530:. Retrieved
7526:the original
7519:
7510:
7498:. Retrieved
7484:
7472:. Retrieved
7462:
7453:
7441:. Retrieved
7436:
7427:
7415:. Retrieved
7405:
7396:
7387:
7374:
7365:
7353:. Retrieved
7342:
7333:
7307:. Retrieved
7302:The Inquirer
7300:
7291:
7279:. Retrieved
7268:
7259:
7247:. Retrieved
7243:
7209:. Retrieved
7170:. Retrieved
7160:
7136:. Retrieved
7129:
7103:. Retrieved
7092:
7066:. Retrieved
7042:
7030:. Retrieved
7026:
7002:. Retrieved
6998:
6969:
6963:
6951:. Retrieved
6912:. Retrieved
6898:
6886:. Retrieved
6882:
6845:
6833:. Retrieved
6822:
6796:. Retrieved
6783:
6762:. Retrieved
6758:
6749:
6737:. Retrieved
6727:
6706:. Retrieved
6696:
6677:, retrieved
6661:
6659:NEC (1999),
6654:
6634:
6627:
6617:, retrieved
6610:the original
6601:
6594:
6584:, retrieved
6577:the original
6568:
6561:
6551:, retrieved
6545:
6538:
6527:. Retrieved
6523:
6513:
6495:
6486:
6477:
6466:. Retrieved
6456:
6445:. Retrieved
6441:the original
6430:
6419:. Retrieved
6415:the original
6404:
6393:. Retrieved
6391:. 2011-08-22
6379:
6368:. Retrieved
6364:the original
6354:
6343:. Retrieved
6339:the original
6329:
6321:heise online
6320:
6311:
6302:
6293:
6284:
6275:
6264:
6249:
6243:. Anandtech.
6234:
6220:
6211:
6201:
6187:
6172:
6161:. Retrieved
6156:
6132:
6121:. Retrieved
6119:. April 2003
6116:
6104:
6092:
6088:
6084:
6080:
6050:
6046:
6040:
6003:
5999:
5992:
5972:
5965:
5945:
5938:
5918:
5911:
5834:225 mm
5804:January 2018
5793:
5792:
5771:
5770:
5757:
5756:
5731:
5730:
5718:140 mm
5676:
5675:
5669:
5668:
5655:
5654:
5645:
5644:
5627:
5626:
5616:100 mm
5607:
5606:
5569:
5568:
5539:
5538:
5525:
5524:
5515:
5514:
5497:
5496:
5483:
5482:
5473:
5472:
5453:
5452:
5448:October 2005
5431:
5430:
5394:
5393:
5384:
5383:
5368:
5367:
5354:
5353:
5344:
5343:
5324:
5323:
5313:280 mm
5304:
5303:
5297:SGRAM (SDR)
5278:
5277:
5268:
5267:
5246:
5245:
5233:280 mm
5227:350 nm
5221:SGRAM (SDR)
5205:280 mm
5196:
5195:
5187:SGRAM (SDR)
5085:(SGRAM) and
5065:
5064:
5039:
5038:
5011:
5010:
4997:
4996:
4975:
4974:
4961:
4960:
4939:
4938:
4925:
4924:
4902:
4901:
4895:
4894:
4881:
4880:
4851:
4850:
4829:
4828:
4799:
4798:
4778:
4777:
4771:
4770:
4759:
4758:
4737:
4736:
4723:
4722:
4701:
4700:
4687:
4686:
4672:
4671:
4665:
4664:
4651:
4650:
4629:
4628:
4615:
4614:
4593:
4592:
4582:
4581:
4519:
4518:
4497:
4496:
4483:
4482:
4473:
4472:
4453:
4452:
4429:
4428:
4419:
4418:
4399:
4398:
4375:
4374:
4332:
4331:
4322:
4321:
4306:
4305:
4292:
4291:
4269:
4268:
4258:
4257:
4248:
4247:
4232:
4231:
4221:279 mm
4178:
4177:
4150:
4149:
4140:
4139:
4124:
4123:
4110:
4109:
4100:
4099:
4080:
4079:
4070:
4069:
4054:
4053:
4040:
4039:
4030:
4029:
4012:
4011:
3996:
3995:
3986:
3985:
3959:325 mm
3950:
3949:
3924:
3923:
3912:
3911:
3894:
3893:
3880:
3879:
3854:
3853:
3843:
3842:
3833:
3832:
3809:325 mm
3800:
3799:
3770:
3769:
3758:
3757:
3671:
3663:
3607:
3582:
3531:
3489:
3465:framebuffers
3458:
3449:
3446:
3442:
3438:
3434:
3430:
3406:
3398:
3394:
3383:
3360:
3356:
3294:Command code
3229:
3225:
3208:
3196:
3188:
3179:
3149:
3144:
3140:
3138:
3127:
3115:
3100:
3089:
3085:
3071:
3067:
3063:
3048:
3043:
3041:
3032:
3010:and 144-pin
2995:
2994:
2985:
2977:form factors
2972:and 144-pin
2957:
2956:
2916:Power Mac G3
2905:
2899:and 144-pin
2884:
2883:
2867:
2863:
2859:
2846:
2844:
2741:2.5 - 7.5 ns
2634:
2627:
2623:
2619:
2615:
2592:
2585:
2572:
2568:
2560:
2557:
2553:
2540:
2537:Auto refresh
2531:
2509:
2505:
2496:
2487:exclusive or
2480:
2476:
2461:
2453:
2449:
2445:
2441:
2438:
2434:
2426:
2406:
2395:
2389:
2381:
2375:
2373:
2367:
2365:
2360:
2356:
2354:
2349:
2345:
2341:
2333:
2329:
2327:
2317:
2315:
2309:
2306:
2256:
1938:
1929:
1901:
1893:
1884:
1863:
1847:
1833:
1827:
1813:
1809:
1801:
1794:
1785:
1776:
1772:
1765:
1734:
1710:
1706:workstations
1695:
1672:
1661:
1619:
1615:
1587:
1576:
1563:
1560:asynchronous
1559:
1553:
1549:clock signal
1540:
1536:
1532:
1531:
1424:Punched tape
1418:Punched card
1384:Time crystal
1252:Hyper CD-ROM
1191:Optical disc
1083:Tape library
1018:FeFET memory
999:Early-stage
879:CompactFlash
874:Memory Stick
834:Flash memory
796:Diode matrix
780:Non-volatile
617:
564:Kryder's law
554:Amdahl's law
479:Software rot
454:Logical disk
354:File copying
289:Data storage
244:File sharing
229:Data cluster
45:data storage
8061:Synchronous
6006:(5): 1118.
5808:K4ZAF325BM
5786:20 nm
5712:20 nm
5594:K4W1G1646G
5440:77 mm
5418:K4D553238F
5291:KM4132G112
5215:μPD4811650
5169:58 mm
5107:SDRAM type
5058:10 nm
4990:20 nm
4954:20 nm
4844:40 nm
4835:16384 Mbit
4752:50 nm
4743:16384 Mbit
4716:50 nm
4644:60 nm
4608:80 nm
4575:90 nm
4562:Xenos eDRAM
4554:86 mm
4533:EE+GS eDRAM
4512:80 nm
4392:90 nm
4367:86 mm
4346:EE+GS eDRAM
3872:150 nm
3783:MSM5718C50
3738:KM48SL2000
3709:SDRAM type
3615:SDRAM from
3508:PlayStation
3473:bit masking
3469:video cards
3467:, found on
3422:northbridge
3096:CAS latency
2979:. PC100 is
2770:1.25 - 5 ns
2671:Generations
2468:cache lines
1768:CAS latency
1632:released a
1583:interleaved
1564:synchronous
1483:Floppy disk
1435:Drum memory
869:Memory card
836:is used in:
770:(2002–2010)
735:(1946–1947)
559:Moore's law
404:Boot sector
344:Object file
249:File system
60:Memory cell
8330:Categories
7925:18 January
6679:2012-07-17
6619:2011-12-27
6586:2011-12-27
6553:2011-01-01
6529:2020-07-15
6468:2011-03-13
6447:2009-06-17
6421:2009-06-16
6395:2011-01-06
6370:2009-06-16
6345:2011-01-03
6163:2021-04-13
6123:2015-08-02
5903:References
5749:20 nm
5690:March 2016
5633:4096 Mbit
5597:1024 Mbit
5585:40 nm
5575:2048 Mbit
5559:60 nm
5545:1024 Mbit
5414:March 2005
5181:μPD481850
5138:HM5283206
5100:Capacity (
5097:Chip name
5017:8192 Mbit
4945:8192 Mbit
4873:30 nm
4861:2048 Mbit
4809:2048 Mbit
4707:8192 Mbit
4696:April 2008
4635:1024 Mbit
4503:2048 Mbit
4463:1024 Mbit
4160:1024 Mbit
3967:March 1998
3937:MD5764802
3900:1024 Mbit
3867:Mitsubishi
3860:1024 Mbit
3702:Capacity (
3699:Chip name
3635:See also:
3613:3D-stacked
3538:GDDR SDRAM
3528:GDDR SDRAM
3390:ECC memory
3176:DDR5 SDRAM
3118:DDR3 SDRAM
3112:DDR4 SDRAM
3082:DDR3 SDRAM
3060:DDR2 SDRAM
2944:NEC PC-100
2835:sound card
2664:DDR5 SDRAM
2658:DDR4 SDRAM
2652:DDR3 SDRAM
2646:DDR2 SDRAM
2588:data words
2576:Mobile DDR
2483:burst mode
2323:refreshing
1788:active low
1698:registered
1691:DDR3 SDRAM
1640:, chip (64
1589:Pipelining
1406:Historical
1078:Tape drive
904:SmartMedia
727:Historical
424:Disk image
419:Disk array
294:Data store
95:MOS memory
85:Memory map
32:NEC PC-100
8310:Bandwidth
8251:XDR2 DRAM
8074:DDR SDRAM
7974:AnandTech
7839:AnandTech
7808:AnandTech
7437:SlashGear
7319:cite news
7157:"History"
6524:AnandTech
6117:intel.com
5726:June 2016
5503:512 Mbit
5459:256 Mbit
5421:256 Mbit
5374:256 Mbit
5330:128 Mbit
5049:128 Gbit
4599:512 Mbit
4409:512 Mbit
4312:256 Mbit
4238:288 Mbit
4130:128 Mbit
4090:128 Mbit
4007:June 1998
3817:N64 RDRAM
3594:in 1998.
3542:DDR SDRAM
3532:Graphics
3516:SCPH-5000
3485:dual-port
3280:Device ID
3217:DDR SDRAM
3139:DDR4 did
3029:DDR SDRAM
3004:SDR SDRAM
2772:per cycle
2743:per cycle
2640:DDR SDRAM
1668:bandwidth
1638:DDR SDRAM
1543:) is any
1465:Disk pack
1430:Plugboard
1267:DVD-Video
1196:LaserDisc
1094:Videotape
965:3D XPoint
956:Memristor
596:CPU cache
364:Core dump
284:Data bank
234:Directory
8246:XDR DRAM
8164:Graphics
8051:EDO DRAM
8046:FPM DRAM
7945:Wccftech
7777:Archived
7561:Archived
7379:Archived
7202:Archived
7131:Phys.org
7059:Archived
6995:"Memory"
6944:Archived
6853:Archived
6670:archived
6643:archived
6487:TechSpot
5843:See also
5821:Samsung
5811:16 Gbit
5783:Samsung
5777:64 Gbit
5745:Samsung
5737:32 Gbit
5640:SK Hynix
5603:Samsung
5469:Samsung
5427:Samsung
5380:Samsung
5340:Samsung
5300:Samsung
5294:32 Mbit
5252:16 Mbit
5218:16 Mbit
5055:Samsung
5025:Samsung
4987:Samsung
4981:12 Gbit
4951:Samsung
4913:Samsung
4749:Samsung
4713:Samsung
4605:Samsung
4566:80 Mbit
4537:32 Mbit
4509:Samsung
4389:Samsung
4381:72 Mbit
4350:32 Mbit
4280:Samsung
4196:32 Mbit
4192:GS eDRAM
4166:Samsung
4136:Samsung
4096:Samsung
4066:Hyundai
4060:64 Mbit
4026:Samsung
4018:64 Mbit
3974:72 Mbit
3940:64 Mbit
3821:36 Mbit
3786:18 Mbit
3631:Timeline
3625:SK Hynix
2918:, early
2792:Signal:
2776:Signal:
2746:Signal:
2704:Signal:
1943:Command
1898:Commands
1717:SK Hynix
1653:SK Hynix
1394:UltraRAM
1272:DVD card
1227:Video CD
1212:CD Video
982:Nano-RAM
951:Memistor
924:XQD card
899:SIM card
757:Dekatron
643:XDR DRAM
638:EDO DRAM
575:Volatile
369:Hex dump
279:Database
174:Metadata
169:Big data
8279:UniDIMM
8143:HBM-PIM
8109:(FCRAM)
7951:16 July
7902:15 July
7896:Samsung
7876:16 July
7871:Samsung
7845:29 June
7814:16 July
7786:10 July
7744:Samsung
7718:10 July
7692:26 June
7686:Samsung
7657:10 July
7651:Samsung
7625:10 July
7598:10 July
7570:10 July
7532:4 April
7494:Samsung
7474:25 June
7469:Samsung
7443:25 June
7417:25 June
7412:Samsung
7355:25 June
7349:Samsung
7309:25 June
7281:25 June
7275:Samsung
7249:4 April
7244:az5miao
7211:26 June
7172:19 June
7167:Samsung
7138:23 June
7105:23 June
7099:Samsung
7068:21 June
7032:4 April
7027:az5miao
7004:25 June
6953:21 June
6914:19 June
6908:Samsung
6888:4 April
6883:az5miao
6835:23 June
6829:Samsung
6798:21 June
6764:10 July
6755:"PU-18"
6739:10 July
6708:10 July
6702:Hitachi
6008:Bibcode
5814:SGRAM (
5700:SGRAM (
5697:8 Gbit
5548:SGRAM (
5462:SGRAM (
5404:SGRAM (
5333:SGRAM (
5263:Samsung
5255:SGRAM (
5184:8 Mbit
5155:Hitachi
5141:8 Mbit
5114:Process
5061:FinFET
4984:LPDDR4
4948:LPDDR4
4209:Toshiba
3907:Hyundai
3753:Samsung
3716:Process
3664:updated
3617:Samsung
3536:SDRAM (
3496:Hitachi
3331:Column
3156:Samsung
3152:Samsung
3092:latency
3012:SO-DIMM
2974:SO-DIMM
2901:SO-DIMM
2813:≤ 1.2 V
2794:SSTL_15
2780:(1.8V)
2778:SSTL_18
2736:= 2.5 V
2700:= 3.3 V
2595:bitline
2366:When a
1702:servers
1630:Samsung
1612:package
1606:Hyundai
1596:History
1479:(~1970)
1473:(~1968)
1455:(1960s)
1292:Blu-ray
1282:MiniDVD
1277:DVD-RAM
1237:Mini CD
1179:Optical
1139:U-matic
1134:MicroMV
1114:Betamax
978:(ECRAM)
919:MicroP2
894:SD card
884:PC Card
675:1T-SRAM
633:QDRSRAM
224:Storage
54:General
8233:Rambus
8118:RLDRAM
8033:(DRAM)
7750:8 July
7500:8 July
7055:Rambus
6759:PSXDEV
6079:Here,
5980:
5953:
5926:
5830:FinFET
5708:Micron
5702:GDDR5X
5581:Hynix
5555:Hynix
5160:350 nm
5119:MOSFET
5089:(HBM)
5034:FinFET
5021:LPDDR5
4909:LPDDR4
4869:Hynix
4841:Hynix
4815:Hynix
4787:Hynix
4683:Hynix
4679:LPDDR2
4641:Hynix
4569:eDRAM
4540:eDRAM
4469:Hynix
4445:110 nm
4440:Elpida
4415:Hynix
4353:eDRAM
4318:Hynix
4284:100 nm
4244:Hynix
4241:RDRAM
4214:180 nm
4170:140 nm
3981:Rambus
3977:RDRAM
3943:RDRAM
3824:RDRAM
3721:MOSFET
3643:, and
3585:
3578:GDDR6W
3574:GDDR6X
3566:GDDR5X
3492:
3386:caches
3365:CMD5=0
3160:Gbit/s
2920:iBooks
2912:AMD K6
2889:memory
2839:Micron
2796:(1.5V)
2750:(2.5V)
2748:SSTL_2
2689:SDRAM
2472:bursts
2396:active
2342:active
2318:active
2122:column
2096:column
2070:column
2044:column
1731:Timing
1723:, and
1642:
1604:Eight
1485:(1971)
1467:(1962)
1461:(1962)
1449:(1957)
1443:(1949)
1437:(1932)
1426:(1725)
1420:(1725)
1414:(1725)
1287:HD DVD
1247:CD-ROM
1203:(CDDA)
1129:MiniDV
848:(SSHD)
830:(SSS)
816:EEPROM
764:(2009)
753:(1952)
747:(1951)
741:(1947)
359:Backup
8336:SDRAM
8293:Lists
8241:RDRAM
8221:GDDR7
8216:GDDR6
8211:GDDR5
8206:GDDR4
8201:GDDR3
8196:GDDR2
8186:SGRAM
8181:MDRAM
8148:HBM3E
8133:HBM2E
8113:eDRAM
8101:LPDDR
8069:SDRAM
7861:"HBM"
7780:(PDF)
7769:(PDF)
7564:(PDF)
7551:(PDF)
7205:(PDF)
7194:(PDF)
7062:(PDF)
7051:(PDF)
6947:(PDF)
6936:(PDF)
6673:(PDF)
6666:(PDF)
6646:(PDF)
6639:(PDF)
6613:(PDF)
6606:(PDF)
6580:(PDF)
6573:(PDF)
6505:JEDEC
6389:JEDEC
6303:Alphr
6113:(PDF)
6091:, or
5873:GDDR7
5869:GDDR6
5865:GDDR5
5861:GDDR4
5857:GDDR3
5853:GDDR2
5825:10 nm
5816:GDDR6
5789:CMOS
5780:HBM2
5767:2017
5753:CMOS
5715:CMOS
5665:2013
5651:CMOS
5623:2012
5613:CMOS
5591:2010
5565:2009
5550:GDDR5
5535:2007
5521:CMOS
5510:Hynix
5493:2005
5479:CMOS
5464:GDDR4
5437:CMOS
5406:GDDR3
5390:CMOS
5364:2003
5350:CMOS
5335:GDDR2
5320:2002
5310:CMOS
5288:1999
5274:CMOS
5230:CMOS
5212:1997
5202:CMOS
5145:SGRAM
5123:Area
5052:DDR4
5029:10 nm
5007:2018
4993:CMOS
4971:2015
4957:CMOS
4935:2014
4921:CMOS
4917:20 nm
4891:2013
4877:CMOS
4847:CMOS
4838:DDR3
4825:2011
4819:40 nm
4812:DDR3
4795:CMOS
4791:44 nm
4784:DDR3
4767:2009
4755:CMOS
4746:DDR3
4733:2008
4719:CMOS
4710:DDR3
4661:2008
4647:CMOS
4638:DDR2
4625:2006
4611:CMOS
4602:DDR3
4578:CMOS
4551:CMOS
4547:65 nm
4529:2005
4515:CMOS
4506:DDR2
4493:2004
4479:CMOS
4466:DDR2
4449:CMOS
4425:CMOS
4412:DDR2
4395:CMOS
4364:CMOS
4360:90 nm
4342:2003
4328:CMOS
4302:2002
4288:CMOS
4254:CMOS
4228:2001
4218:CMOS
4200:eDRAM
4188:2000
4174:CMOS
4146:CMOS
4120:1999
4106:CMOS
4076:CMOS
4050:1998
4036:CMOS
3992:CMOS
3956:CMOS
3934:1998
3890:1997
3876:CMOS
3839:CMOS
3806:CMOS
3790:RDRAM
3780:1996
3735:1992
3725:Area
3686:SDRAM
3570:GDDR6
3562:GDDR5
3558:GDDR4
3554:GDDR3
3550:GDDR2
3510:(PS)
3413:RDRAM
3286:CMD5
3198:RDRAM
3000:JEDEC
2996:PC133
2991:PC133
2966:JEDEC
2958:PC100
2938:PC100
2893:JEDEC
2851:DIMMs
2847:SDRAM
2706:LVTTL
2681:Type
2492:Intel
2464:cache
2376:write
2361:write
2355:Both
2350:write
2334:write
1675:JEDEC
1651:(now
1578:banks
1568:JEDEC
1554:DRAM
1541:SDRAM
1347:ECRAM
1327:CBRAM
1262:DVD+R
1222:CD-RW
1159:D-VHS
1154:VHS-C
1149:S-VHS
1090:(DDS)
1013:ReRAM
1008:FeRAM
1001:NVRAM
987:CBRAM
944:NVRAM
842:(SSD)
811:EPROM
768:Z-RAM
762:T-RAM
694:(CAM)
682:ReRAM
648:RDRAM
628:LPDDR
623:SGRAM
618:SDRAM
613:eDRAM
47:types
8284:CAMM
8274:DIMM
8269:SIMM
8191:GDDR
8176:WRAM
8171:VRAM
8138:HBM3
8128:HBM2
8094:DDR5
8089:DDR4
8084:DDR3
8079:DDR2
7953:2019
7927:2018
7904:2019
7878:2019
7847:2019
7816:2019
7788:2019
7752:2019
7720:2019
7694:2019
7659:2019
7627:2019
7621:(48)
7600:2019
7572:2019
7534:2022
7502:2019
7476:2019
7445:2019
7419:2019
7357:2019
7325:link
7311:2019
7283:2019
7251:2022
7213:2019
7198:Sony
7174:2019
7140:2019
7107:2019
7070:2019
7034:2022
7006:2019
6955:2019
6916:2019
6890:2022
6837:2019
6800:2019
6766:2019
6741:2019
6710:2019
5978:ISBN
5951:ISBN
5924:ISBN
5871:and
5849:GDDR
5741:HBM2
5257:GDDR
5224:NEC
5165:CMOS
5102:bits
4865:DDR4
4572:NEC
4385:DDR3
4315:SDR
4276:DDR2
4205:Sony
4163:DDR
4133:DDR
4093:SDR
4063:DDR
3946:Oki
3903:SDR
3863:SDR
3765:CMOS
3743:Mbit
3704:bits
3623:and
3588:Mbit
3576:and
3504:Sony
3481:WRAM
3479:and
3477:VRAM
3463:and
3388:and
3303:Row
3300:Bank
3297:CMD0
3269:CA0
3239:FLAG
3221:MT/s
3170:DDR5
3106:DDR4
3076:DDR3
3054:DDR2
3044:DDR1
3008:DIMM
2970:DIMM
2922:and
2910:and
2897:DIMM
2885:PC66
2880:PC66
2804:DDR4
2786:DDR3
2759:DDR2
2716:DDR1
2630:DDR3
2607:bits
2603:DDR3
2600:Gbit
2368:read
2359:and
2357:read
2346:read
2332:and
2330:read
2316:The
2310:chip
2246:mode
2165:bank
2142:bank
2116:bank
2090:bank
2064:bank
2038:bank
1872:and
1856:and
1840:and
1704:and
1689:and
1687:DDR2
1657:DRAM
1645:Mbit
1610:DIMM
1545:DRAM
1337:NRAM
1309:WORM
1217:CD-R
971:MRAM
806:PROM
801:MROM
703:VRAM
687:QRAM
670:SRAM
658:GDDR
608:DRAM
504:RAID
154:Data
43:and
8123:HBM
7592:NEC
6793:359
6789:NEC
6733:NEC
6157:EDN
6016:doi
5683:HBM
5191:NEC
5149:SDR
5127:Ref
4022:DDR
3919:SOI
3828:NEC
3795:Oki
3748:SDR
3741:16
3729:Ref
3621:AMD
3506:'s
3500:NEC
3409:NEC
3283:ID0
3277:ID8
3266:CA1
3263:CA2
3260:CA3
3257:CA4
3254:CA5
3251:CA6
3248:CA7
3245:CA8
3242:CA9
3141:not
3023:DDR
2932:FSB
2855:ECC
2822:SDR
2564:REF
2544:REF
2422:RCD
2414:RCD
2410:RFC
2392:RAS
2348:or
2338:RCD
2288:ACT
2284:ACT
2243:0 0
2145:row
1934:A10
1919:CAS
1914:RAS
1874:CAS
1870:RAS
1854:RAS
1849:CAS
1838:CAS
1834:not
1829:RAS
1810:DQM
1795:CKE
1683:DDR
1622:IBM
1539:or
1257:DVD
1144:VHS
961:PCM
914:SxS
789:ROM
663:HBM
653:DDR
584:RAM
8332::
7943:.
7894:.
7869:.
7863:.
7836:.
7824:^
7805:.
7771:.
7742:.
7736:.
7710:.
7684:.
7678:.
7667:^
7649:.
7643:.
7617:.
7590:.
7559:.
7553:.
7518:.
7492:.
7467:.
7461:.
7435:.
7410:.
7404:.
7377:.
7373:.
7347:.
7341:.
7321:}}
7317:{{
7299:.
7273:.
7267:.
7242:.
7221:^
7196:.
7182:^
7165:.
7159:.
7148:^
7128:.
7115:^
7097:.
7091:.
7078:^
7053:.
7025:.
7014:^
6997:.
6984:^
6938:.
6924:^
6906:.
6881:.
6864:^
6827:.
6821:.
6808:^
6787:.
6774:^
6757:.
6731:.
6718:^
6700:.
6687:^
6668:,
6641:,
6522:.
6485:.
6319:.
6301:.
6283:.
6210:.
6155:.
6141:^
6115:.
6087:,
6083:,
6058:^
6047:41
6045:.
6039:.
6028:^
6014:.
6004:25
6002:.
5867:,
5863:,
5859:,
5855:,
5818:)
5704:)
5552:)
5466:)
5408:)
5337:)
5259:)
5151:)
5104:)
4207:,
3706:)
3639:,
3619:,
3580:.
3572:,
3568:,
3564:,
3560:,
3556:,
3552:,
3319:0
3314:0
3308:0
3291:0
3274:1
2811:cc
2734:cc
2698:cc
2611:ns
2418:RP
2416:+t
2385:RP
2374:A
1928:BA
1924:WE
1909:CS
1865:WE
1858:WE
1842:WE
1803:CS
1745:10
1727:.
1719:,
1715:,
1708:.
1693:.
1685:,
1670:.
1551:.
1207:CD
1124:DV
8023:e
8016:t
8009:v
7955:.
7929:.
7906:.
7880:.
7849:.
7818:.
7790:.
7754:.
7722:.
7696:.
7661:.
7629:.
7602:.
7574:.
7536:.
7504:.
7478:.
7447:.
7421:.
7359:.
7327:)
7313:.
7285:.
7253:.
7215:.
7176:.
7142:.
7109:.
7072:.
7036:.
7008:.
6957:.
6918:.
6892:.
6839:.
6802:.
6768:.
6743:.
6712:.
6532:.
6471:.
6450:.
6424:.
6398:.
6373:.
6348:.
6323:.
6305:.
6258:.
6214:.
6195:.
6180:.
6166:.
6126:.
6093:T
6089:G
6085:M
6081:K
6022:.
6018::
6010::
5986:.
5959:.
5932:.
5794:?
5772:?
5758:?
5732:?
5677:?
5670:?
5656:?
5646:?
5628:?
5608:?
5570:?
5540:?
5526:?
5516:?
5498:?
5484:?
5474:?
5454:?
5432:?
5395:?
5385:?
5369:?
5355:?
5345:?
5325:?
5305:?
5279:?
5269:?
5247:?
5197:?
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5066:?
5040:?
5012:?
4998:?
4976:?
4962:?
4940:?
4926:?
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4896:?
4882:?
4852:?
4830:?
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4101:?
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4031:?
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3844:?
3834:?
3801:?
3771:?
3759:?
3676:)
3672:(
3328:0
3325:0
3322:0
3145:n
3130:V
2946:.
2809:V
2732:V
2696:V
2562:t
2408:t
2240:L
2237:L
2234:L
2231:L
2223:x
2220:x
2217:x
2214:H
2211:L
2208:L
2205:L
2197:x
2194:H
2191:x
2188:L
2185:H
2182:L
2179:L
2171:x
2168:L
2162:L
2159:H
2156:L
2153:L
2139:H
2136:H
2133:L
2130:L
2119:H
2113:L
2110:L
2107:H
2104:L
2093:L
2087:L
2084:L
2081:H
2078:L
2067:H
2061:H
2058:L
2055:H
2052:L
2041:L
2035:H
2032:L
2029:H
2026:L
2018:x
2015:x
2012:x
2009:L
2006:H
2003:H
2000:L
1992:x
1989:x
1986:x
1983:H
1980:H
1977:H
1974:L
1966:x
1963:x
1960:x
1957:x
1954:x
1951:x
1948:H
1939:n
1937:A
1930:n
1814:Q
1749:6
1535:(
1513:e
1506:t
1499:v
967:)
963:(
34:.
20:)
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