Synchronous dynamic random-access memory

2614:

datawords in memory, which in practice is very often the case. For instance, in DDR1, two adjacent data words will be read from each chip in the same clock cycle and placed in the pre-fetch buffer. Each word will then be transmitted on consecutive rising and falling edges of the clock cycle. Similarly, in DDR2 with a 4n pre-fetch buffer, four consecutive data words are read and placed in buffer while a clock, which is twice faster than the internal clock of DDR, transmits each of the word in consecutive rising and falling edge of the faster external clock

3644: 3216:

command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.

2289: 2621:), the IOs will operate 8 times faster than the memory core (each memory access results in a burst of 8 datawords on the IOs). Thus, a 200 MHz memory core is combined with IOs that each operate eight times faster (1600 megabits per second). If the memory has 16 IOs, the total read bandwidth would be 200 MHz x 8 datawords/access x 16 IOs = 25.6 gigabits per second (Gbit/s) or 3.2 gigabytes per second (GB/s). Modules with multiple DRAM chips can provide correspondingly higher bandwidth. 2474:, later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of four, and a requested column address of five, the words would be accessed in the order 5-6-7-4. If the burst length were eight, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length. The interleaved burst mode computes the address using an 2467:

option: sequential or interleaved. Typically, a memory controller will require one or the other. When the burst length is one or two, the burst type does not matter. For a burst length of one, the requested word is the only word accessed. For a burst length of two, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified.

2816: 1514: 2939: 1787:

cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high. Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.

1590: 3421:

SDRAM's read and write commands specify a channel number to access. Reads and writes may thus be performed independent of the currently active state of the DRAM array, with the equivalent of four full DRAM rows being "open" for access at a time. This is an improvement over the two open rows possible in a standard two-bank SDRAM. (There is actually a 17th "dummy channel" used for some operations.)

1767:

standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 - although the actual meaning of the numbers has changed).

2463:. A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line. 3425:

DRAM array may be precharged while read commands to the channel buffer continue. To write, first the data is written to a channel buffer (typically previous initialized using a Prefetch command), then a restore command, with the same parameters as the prefetch command, copies a segment of data from the channel to the sense amplifier array.

3537:(GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2023, there are eight successive generations of GDDR: 3433:

cells.) The SRAM bits are designed to be four DRAM bits wide, and are conveniently connected to one of the four DRAM bits they straddle.) Additional commands prefetch a pair of segments to a pair of channels, and an optional command combines prefetch, read, and precharge to reduce the overhead of random reads.

3428:

Unlike a normal SDRAM write, which must be performed to an active (open) row, the VCSDRAM bank must be precharged (closed) when the restore command is issued. An active command immediately after the restore command specifies the DRAM row completes the write to the DRAM array. There is, in addition, a

3424:

To read from VCSDRAM, after the active command, a "prefetch" command is required to copy data from the sense amplifier array to the channel SDRAM. This command specifies a bank, two bits of column address (to select the segment of the row), and four bits of channel number. Once this is performed, the

3346:

Individual devices had 8-bit IDs. The 9th bit of the ID sent in commands was used to address multiple devices. Any aligned power-of-2 sized group could be addressed. If the transmitted msbit was set, all least-significant bits up to and including the least-significant 0 bit of the transmitted address

3113:

in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development - it was originally expected to be released in 2012, and later (during 2010) expected to be released in 2015, before samples were announced in early 2011 and manufacturers

2558:

Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh

2435:

Interrupting a read burst by a write command is possible, but more difficult. It can be done if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data

2424:

A read, burst terminate, or precharge command may be issued at any time after a read command, and will interrupt the read burst after the configured CAS latency. So if a read command is issued on cycle 0, another read command is issued on cycle 2, and the CAS latency is 3, then the first read command

2371:

When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at

1762:

In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally

1580:

means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a

2849:

Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is

2609:

The drawback of the older fast column access method was that a new column address had to be sent for each additional dataword on the row. The address bus had to operate at the same frequency as the data bus. Prefetch architecture simplifies this process by allowing a single address request to result

2562:

SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate. Another is selective refresh, which limits

2367:

command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be

3439:

A 13-bit address bus, as illustrated here, is suitable for a device up to 128 Mbit. It has two banks, each containing 8,192 rows and 8,192 columns. Thus, row addresses are 13 bits, segment addresses are two bits, and eight column address bits are required to select one byte from the 2,048 bits

3215:

SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the

3090:

DDR3 memory chips are being made commercially, and computer systems using them were available from the second half of 2007, with significant usage from 2008 onwards. Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667

3057:

Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25 ns). Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is

2586:

precharge, row access, column access. Row access is the heart of a read operation, as it involves the careful sensing of the tiny signals in DRAM memory cells; it is the slowest phase of memory operation. However, once a row is read, subsequent column accesses to that same row can be very quick, as

2530:

It is possible to refresh a RAM chip by opening and closing (activating and precharging) each row in each bank. However, to simplify the memory controller, SDRAM chips support an "auto refresh" command, which performs these operations to one row in each bank simultaneously. The SDRAM also maintains

3420:

VCM inserts an SRAM cache of 16 "channel" buffers, each 1/4 row "segment" in size, between DRAM banks' sense amplifier rows and the data I/O pins. "Prefetch" and "restore" commands, unique to VCSDRAM, copy data between the DRAM's sense amplifier row and the channel buffers, while the equivalent of

3027:

interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR

1805:

appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from

3198:

SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its

2975:

A module built out of 100 MHz SDRAM chips is not necessarily capable of operating at 100 MHz. The PC100 standard specifies the capabilities of the memory module as a whole. PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory.

2521:

Later (double data rate) SDRAM standards use more mode register bits, and provide additional mode registers called "extended mode registers". The register number is encoded on the bank address pins during the load mode register command. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit

2509:

M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the

3432:

Although normally a segment is restored to the same memory address as it was prefetched from, the channel buffers may also be used for very efficient copying or clearing of large, aligned memory blocks. (The use of quarter-row segments is driven by the fact that DRAM cells are narrower than SRAM

3053:

DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be

2439:

Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output on a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient

1786:

clock enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock

3038:

Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available.

2613:

In a prefetch buffer architecture, when a memory access occurs to a row the buffer grabs a set of adjacent data words on the row and reads them out ("bursts" them) in rapid-fire sequence on the IO pins, without the need for individual column address requests. This assumes the CPU wants adjacent

2466:

Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a four-word burst access to any column address from four to seven will return words four to seven. The ordering, however, depends on the requested address, and the configured burst type

3075:

DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words. This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. To maintain 800–1600 M transfers/s (both edges of a

2495:

Single data rate SDRAM has a single 10-bit programmable mode register. Later double-data-rate SDRAM standards add additional mode registers, addressed using the bank address pins. For SDR SDRAM, the bank address pins and address lines A10 and above are ignored, but should be zero during a mode

1766:

SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100

2516:

M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will

2309:

command activates an idle bank. It presents a two-bit bank address (BA0–BA1) and a 13-bit row address (A0–A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of

2543:

As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM. The CKE input is sampled each rising edge of the clock, and if it is low, the following rising edge of the clock is ignored for all purposes other than checking CKE. As long as CKE is low, it is

2478:

operation between the counter and the address. Using the same starting address of five, a four-word burst would return words in the order 5-4-7-6. An eight-word burst would be 5-4-7-6-1-0-3-2. Although more confusing to humans, this can be easier to implement in hardware, and is preferred by

3384:

Additional commands (with CMD5 set) opened and closed rows without a data transfer, performed refresh operations, read or wrote configuration registers, and performed other maintenance operations. Most of these commands supported an additional 4-bit sub-ID (sent as 5 bits, using the same

2436:

are delayed by two cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command but must be lowered for the cycle of the write command (assuming the write command is intended to have an effect).

2359:

command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency. Subsequent words of the burst will be produced in time for subsequent rising clock edges.

2605:

Traditional DRAM architectures have long supported fast column access to bits on an open row. For an 8-bit-wide memory chip with a 2,048 bit wide row, accesses to any of the 256 datawords (2048/8) on the row can be very quick, provided no intervening accesses to other rows occur.

1752: Hz) to 5 ns for DDR-400, but remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly. 2396:

The no operation command is always permitted, while the load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect. The auto refresh command also requires that all banks be idle, and takes a refresh cycle time

2486:

If the requested column address is at the start of a block, both burst modes (sequential and interleaved) return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order.

3203:

and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400 MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like

3169:

In March 2017, JEDEC announced a DDR5 standard is under development, but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.

3189:

was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR SDRAM.

2296:

As an example, a 512 MB SDRAM DIMM (which contains 512 MB), might be made of eight or nine SDRAM chips, each containing 512 Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM

3114:

began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.

1563:

that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called

2550:

If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval

3022:

While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a

3054:

doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips.

3058:

now available at a clock rate of 533 MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available.

2853:

Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns), respectively denoted PC66, PC100, and PC133. Clock rates up to 200 MHz were available. It operates at a voltage of 3.3 V.

2459:. To transfer a 64-byte cache line requires eight consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform eight-word 5986:

Kalter, H. L.; Stapper, C. H.; Barth, J. E.; Dilorenzo, J.; Drake, C. E.; Fifield, J. A.; Kelley, G. A.; Lewis, S. C.; van der Hoeven, W. B.; Jankosky, J. A. (1990). "A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC".

2431:

Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst.

2531:

an internal counter, which iterates over all possible rows. The memory controller must simply issue a sufficient number of auto refresh commands (one per row, 8192 in the example we have been using) every refresh interval (t

1605:

The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.

2838:, single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin 3003:

form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066 GB per second (=1.066 GB/s). (1 GB/s = one billion bytes per second) PC133 is

3404:

because VCM was not nearly as expensive as RDRAM was. A Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, so support for both depends only on the capabilities of the

1763:

increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.

1724:

There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM (1 MHz =

3385:

multiple-destination encoding as the primary ID) which could be used to distinguish devices that were assigned the same primary ID because they were connected in parallel and always read/written at the same time.

1874:

SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward.

7754: 3083:. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a 2387:

command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.

2301:

internally contains four independent 16 MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.

2567:(LPDDR) and LPDDR2 is "deep power down" mode, which invalidates the memory and requires a full reinitialization to exit from. This is activated by sending a "burst terminate" command while lowering CKE. 3143:

validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since, as of 2009, current DRAM chips were only beginning to migrate to a 50 nm process. In January 2011,

6323: 7629: 7253: 3061:

Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100 MHz) has somewhat higher latency than DDR-400 (internal clock rate 200 MHz).

6040:

The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.

2352:

commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0–A9, A11).

3347:

were ignored for "is this addressed to me?" purposes. (If the ID8 bit is actually considered less significant than ID0, the unicast address matching becomes a special case of this pattern.)

1759:, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM. 2416:

When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands.

2857:

This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate). But this type is also faster than its predecessors

1883:

Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.

1670:

to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for

3400:, but released as an open standard with no licensing fees. It is pin-compatible with standard SDRAM, but the commands are different. The technology was a potential competitor of 1655:

due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective

3125:

per second. They were expected to be introduced at frequency rates of 2133 MHz, estimated to rise to a potential 4266 MHz and lowered voltage of 1.05 V by 2013.

7077: 3429:

17th "dummy channel" which allows writes to the currently open row. It may not be read from, but may be prefetched to, written to, and restored to the sense amplifier array.

7722: 7478: 7664: 3616:. It is designed to be used in conjunction with high-performance graphics accelerators and network devices. The first HBM memory chip was produced by SK Hynix in 2013. 3091:

and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common. Performance up to DDR3-2800 (PC3 22400 modules) are available.

7765: 3028:

interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM.

7880: 1750: 2957:. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin 2559:

mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.

2329:

before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an

2617:

The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency. In an 8n prefetch architecture (such as

2379:

Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time t

7978: 7285: 7190: 3436:

The above are the JEDEC-standardized commands. Earlier chips did not support the dummy channel or pair prefetch, and use a different encoding for precharge.

1551:

interface, in which input control signals have a direct effect on internal functions delayed only by the trip across its semiconductor pathways. SDRAM has a

6684: 6807: 6425: 2582:

The prefetch architecture takes advantage of the specific characteristics of memory accesses to DRAM. Typical DRAM memory operations involve three phases:

7983: 7973: 6327: 2884:. PC66 is Synchronous DRAM operating at a clock frequency of 66.66 MHz, on a 64-bit bus, at a voltage of 3.3 V. PC66 is available in 168-pin 7504: 2563:

self-refresh to a portion of the DRAM array. The fraction which is refreshed is configured using an extended mode register. The third, implemented in

7327: 6932: 1651:

SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous

6631: 6508: 2896: 2428:

If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5.

6098: 7696: 7603: 7574: 7047: 6715: 3464:(writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike 3448:

Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It is designed for graphics-related tasks such as

2376:, which must elapse before that row is fully "closed" and so the bank is idle in order to receive another activate command on that bank. 3147:

announced the completion and release for testing of a 30 nm 2048 MB DDR4 DRAM module. It has a maximum bandwidth of 2.13

2341:

command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.

7907: 8298: 2425:

will begin bursting data out during cycles 3 and 4, then the results from the second read command will appear beginning with cycle 5.

1775:

All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly

1555:

interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by

5071: 2988: 2954: 2881: 2598:

wide, so internally 2,048 bits are read into 2,048 separate sense amplifiers during the row access phase. Row accesses might take 50

2583: 7367: 1795:

chip select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.

626: 5737: 4905: 7549: 6373: 2995:

operating at a clock frequency of 133 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC133 is available in 168-pin

6589: 6556: 6471: 4521: 4334: 4180: 1500: 6348: 1041: 6399: 6489: 3805: 3601: 2694: 6196: 1574:

fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.

7421: 3388:

There were a number of 8-bit control registers and 32-bit status registers to control various device timing parameters.

2555:, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings. 2503:

M9: Write burst mode. If 0, writes use the read burst length and mode. If 1, all writes are non-burst (single location).

6841: 6287: 1250: 202: 6658: 247: 6781: 5970: 5943: 5916: 2325:

commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or t

989: 932: 252: 7822: 6305: 6257: 3035:

for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.

2547:

If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again.

2409:.) The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, t 8329: 5102: 3704: 100: 7179: 1570:, allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an 1315: 975: 919: 6429: 2368:

done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line.

8010: 6244: 3414: 3136:

prefetch as DDR3. Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.

1001: 670: 482: 78: 6214: 2443:

If the read command includes auto-precharge, the precharge begins the same cycle as the interrupting command.

7791: 7313: 1865:, this selects one of eight commands. It generally distinguishes read-like commands from write-like commands. 1581:

fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.

1350: 6450: 8159: 8019: 7929: 6771: 5884: 3465: 2830:

48LC32M8A2 SDRAM chips. They run at 133 MHz (7.5 ns clock period) and have 8-bit wide data buses.

2782: 2766: 2736: 701: 596: 497: 7479:"Samsung Electronics Announces Industry's First 8Gb LPDDR5 DRAM for 5G and AI-powered Mobile Applications" 658: 7514: 7114: 2499:

The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle.

2265:

DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer

6959: 6269: 3373:

A notable omission from the specification was per-byte write enables; it was designed for systems with

2892:

form factors. The theoretical bandwidth is 533 MB/s. (1 MB/s = one million bytes per second)

2372:

the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, t

1617:

RAM and presented their results at the International Solid-State Circuits Convention in 1990. In 1998,

1493: 1290: 1189: 1061: 691: 680: 7881:"Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems" 7630:"Samsung Announces the World's First 222 MHz 32Mbit SGRAM for 3D Graphics and Networking Applications" 6921: 3087:

of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).

789: 7254:"Samsung Develops the Industry's Fastest DDR3 SRAM for High Performance EDP and Network Applications" 6983: 6141: 5866: 2535:= 64 ms is a common value). All banks must be idle (closed, precharged) when this command is issued. 2240:

The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)

2215:

Auto refresh: refresh one row of each bank, using an internal counter. All banks must be precharged.

552: 487: 382: 6622: 3625: 2513:

M3: Burst type. 0 - requests sequential burst ordering, while 1 requests interleaved burst ordering.

1644:) the same year and mass-produced in 1993. By 2000, SDRAM had replaced virtually all other types of 5883:

A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in

3534: 2602:, depending on the speed of the DRAM, whereas column accesses off an open row are less than 10 ns. 2275:

controls it, during which the other control lines are used as row address bits 16, 15 and 14. When

1362: 1345: 834: 120: 5908:

Microprocessor: Prolegomenes - Calculation and Storage Functions - Calculation Models and Computer

3076:

400–800 MHz clock), the internal RAM array has to perform 100–200 M fetches per second.

7544: 3410: 1357: 1174: 897: 302: 137: 115: 95: 48: 8288: 3178:

In addition to DDR, there were several other proposed memory technologies to succeed SDR SDRAM.

2246:

All SDRAM generations (SDR and DDRx) use essentially the same commands, with the changes being:

6892: 5871: 3609: 2858: 2471: 2460: 1230: 447: 317: 257: 7036: 6181: 2517:

continue until interrupted. Full-row bursts are only permitted with the sequential burst type.

579: 8111: 7854: 7727: 7634: 7452: 7447: 7395: 7390: 7332: 7258: 6928: 5671: 5075: 4550: 3783: 3597: 3592: 3496: 3491:μPD481850, introduced in December 1994. The earliest known commercial device to use SGRAM is 3472:, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the 3110: 3080: 1656: 1486: 733: 651: 437: 242: 222: 212: 68: 33: 7967: 1728: 8272: 7145: 6533: 5996: 3907: 2965: 2950: 2877: 1577: 1560: 1536:

where the operation of its external pin interface is coordinated by an externally supplied

1429: 1297: 1076: 1036: 959: 572: 477: 367: 262: 125: 105: 88: 83: 8303: 7359: 3633: 8: 7761: 7700: 7669: 7180:"EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP" 7150: 7082: 6812: 5251: 3895: 3855: 3741: 3605: 3580: 3208:, SLDRAM uses a double-pumped bus, giving it an effective speed of 400, 600, or 800 3005: 2969: 2862: 1701: 1637: 1594: 1335: 1026: 964: 949: 816: 768: 621: 432: 130: 6000: 3657:

Please help update this article to reflect recent events or newly available information.

8143: 8003: 7307: 3504: 3500: 2820: 1690: 1662:

Today, virtually all SDRAM is manufactured in compliance with standards established by

1571: 1544: 1435: 1400: 1046: 472: 457: 402: 397: 387: 362: 287: 7988: 2522:

extended mode register No. 1 (EMR1), and a 5-bit extended mode register No. 2 (EMR2).

7536: 7509: 6166: 6030: 5966: 5939: 5912: 5696: 3406: 3152: 2827: 1841:, column address strobe. This is also not a strobe, rather a command bit. Along with 1709: 1686: 1112: 1107: 1031: 996: 850: 828: 727: 686: 589: 427: 152: 6598: 6565: 6229: 3629: 6352: 6004: 3522: 3121:

or less, compared to the 1.5 V of DDR3 chips, and have in excess of 2 billion

3024: 2715: 2575:

DDR SDRAM employs prefetch architecture to allow quick and easy access to multiple

1713: 1622: 1614: 1447: 1441: 1367: 1330: 1320: 1285: 1097: 1051: 1019: 794: 777: 462: 422: 182: 167: 63: 53: 7078:"Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option" 3219:

The basic read/write command consisted of (beginning with CA9 of the first word):

8095: 7959:

Everything you always wanted to know about SDRAM (memory), but were afraid to ask

6845: 6403: 6025: 5960: 5933: 5906: 3473: 3357:

CMD4=1 to open (activate) the specified row; CMD4=0 to use the currently open row

2865:(FPM-RAM) which took typically two or three clocks to transfer one word of data. 1340: 1167: 1154: 845: 840: 696: 563: 542: 517: 377: 297: 227: 197: 172: 58: 29: 6509:"DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond" 8324: 7823:"Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand" 3449: 2920: 2311: 2262:

DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"

1667: 1652: 1459: 1377: 1220: 877: 739: 675: 547: 532: 512: 507: 452: 417: 372: 322: 312: 307: 292: 187: 177: 110: 7723:"Samsung Electronics Develops Industry's First Ultra-Fast GDDR4 Graphics DRAM" 2288: 8318: 8249: 8164: 7996: 6964: 6085: 5813: 5017: 4433: 4428: 4158: 3860: 3572:

GDDR was initially known as DDR SGRAM. It was commercially introduced as a 16

3469: 3200: 3122: 2916: 1465: 1092: 1087: 1056: 811: 721: 537: 527: 522: 502: 337: 327: 207: 192: 6838: 2268: 7849: 7665:"Samsung Electronics Announces JEDEC-Compliant 256Mb GDDR2 for 3D Graphics" 7290: 6649: 5573: 5547: 4861: 4807: 4779: 2912: 2904: 2475: 1694: 1537: 1412: 1406: 1372: 1240: 1195: 1179: 1071: 867: 862: 822: 784: 467: 442: 342: 277: 232: 217: 7228: 7011: 6867: 6451:"Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology" 8209: 8204: 8199: 8194: 8189: 8184: 3453: 3084: 2114:

Write with auto precharge: as above, and precharge (close row) when done

1776: 1756: 1566: 1533: 1471: 1423: 857: 392: 332: 237: 6743: 2238:

Load mode register: A0 through A9 are loaded to configure the DRAM chip.

2062:

Read with auto precharge: as above, and precharge (close row) when done

1806:

the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.

8179: 8082: 8077: 8072: 8067: 4264: 3526: 3516: 3457: 3378: 3164: 3106: 3100: 3070: 3048: 2932: 2843: 2823: 2815: 2792: 2774: 2747: 2652: 2646: 2640: 2634: 2599: 2564: 2544:

permissible to change the clock rate, or even stop the clock entirely.

2456: 1679: 1675: 1066: 892: 646: 412: 407: 282: 147: 73: 20: 7958: 2587:

the sense amplifiers also act as latches. For reference, a row of a 1

2401:

to return the chip to the idle state. (This time is usually equal to t

2259:

Additional extended mode registers (selected by the bank address bits)

1513: 8239: 8062: 7962: 7827: 7796: 5137: 5009: 4010: 3736: 3530: 3374: 3205: 3017: 2992: 2938: 2704: 2628: 2576: 2452: 2413:

before the row is fully open and can accept read and write commands.

1671: 1626: 1453: 1418: 1255: 1184: 1082: 953: 944: 641: 584: 352: 272: 7908:"Samsung fires up its foundries for mass production of GDDR6 memory" 6008: 3155:

technology and draws 40% less power than an equivalent DDR3 module.

8234: 8039: 8034: 7119: 5877: 5628: 3613: 3461: 1705: 1641: 1382: 1325: 1260: 1215: 1200: 970: 939: 912: 887: 745: 631: 357: 267: 162: 157: 5885:

High-Performance DRAM System Design Constraints and Considerations

3366:

CMD1=1 to close the row after this access; CMD1=0 to leave it open

8267: 8131: 7884: 7859: 7732: 7674: 7639: 7482: 7457: 7400: 7337: 7263: 7155: 7087: 6896: 6817: 6690: 6125:

Micron, General DDR SDRAM Functionality, Technical Note, TN-46-05

5143: 4197: 3731: 3576: 3484: 3144: 3140: 3000: 2962: 2889: 2655:'s prefetch buffer size is 8n; there is an additional mode of 16n 2649:'s prefetch buffer size is 8n (eight datawords per memory access) 2643:'s prefetch buffer size is 8n (eight datawords per memory access) 2588: 1633: 1618: 1280: 1270: 1265: 1225: 1127: 1122: 1102: 907: 882: 872: 663: 7930:"Samsung Begins Producing The Fastest GDDR6 Memory In The World" 2637:'s prefetch buffer size is 4n (four datawords per memory access) 1689:

varieties, for systems that require greater scalability such as

8221: 8106: 7792:"Micron Begins to Sample GDDR5X Memory, Unveils Specs of Chips" 7043: 5818: 5690: 5148: 5107: 5022: 4897: 4667: 4272: 4202: 3969: 3709: 3566: 3562: 3554: 3510: 3507:

model released in December 1995, using the NEC μPD481850 chip.

3148: 2900: 2631:'s prefetch buffer size is 2n (two datawords per memory access) 2624:

Each generation of SDRAM has a different prefetch buffer size:

2189:

Precharge all: deactivate (close) the current row of all banks

2163:

Precharge: deactivate (close) the current row of selected bank

1547:(ICs) produced from the early 1970s to the early 1990s used an 1275: 1235: 1117: 1006: 804: 347: 7294:. 4 November 2003. Archived from the original on July 10, 2019 6808:"Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs" 2010:

Burst terminate: stop a burst read or burst write in progress

1589: 8229: 8174: 8169: 8136: 8121: 8101: 8089: 7984:

PC SDRAM Serial Presence Detect (SPD) Specification, Rev 1.2B

6493: 6377: 5861: 5857: 5853: 5849: 5845: 5841: 5804: 5538: 5498: 5452: 5394: 5323: 5133: 4535: 4348: 4188: 3778: 3558: 3550: 3546: 3542: 3538: 3401: 3360:

CMD3=1 to transfer an 8-word burst; CMD3=0 for a 4-word burst

3186: 3132:

double the internal prefetch width again, but uses the same 8

2908: 2480: 1663: 1556: 1210: 1147: 1142: 1137: 799: 756: 750: 636: 616: 601: 6400:"Samsung hints to DDR4 with first validated 40 nm DRAM" 3655:. The reason given is: Advances in DDR5 need to be included. 19:"PC100" redirects here. For the Japanese home computer, see 8262: 8257: 8126: 8116: 7186: 7115:"Samsung Demonstrates World's First DDR 3 Memory Prototype" 5985: 5837: 5729: 5245: 5153: 4853: 4373: 4193: 3753: 3492: 3209: 3199:

name to Advanced Memory International, Inc.) SLDRAM was an

3118: 2996: 2958: 2885: 2839: 2618: 2591: 2314:

the dynamic (capacitive) memory storage cells of that row.

1645: 1598: 1205: 492: 142: 6374:"JEDEC Announces Key Attributes of Upcoming DDR4 Standard" 5931: 3079:

Again, with every doubling, the downside is the increased

2137:

Active (activate): open a row for read and write commands

1700:

Today, the world's largest manufacturers of SDRAM include

7580: 6777: 6721: 5179: 5090: 3816: 3692: 3488: 3397: 3396:

VCM was a proprietary type of SDRAM that was designed by

2595: 2088:

Write: write a burst of data to the currently active row

2036:

Read: read a burst of data from the currently active row

1648:

in modern computers, because of its greater performance.

1610: 1245: 1132: 902: 6472:"Samsung develops DDR4 memory, up to 40% more efficient" 6324:"Next-Generation DDR4 Memory to Reach 4.266GHz - Report" 2850:

never required for a read and a write at the same time.

1559:, the clock signal controls the stepping of an internal 8018: 6620: 6490:"JEDEC DDR5 & NVDIMM-P Standards Under Development" 6306:"heise online - IT-News, Nachrichten und Hintergründe" 2923:. It was superseded by the PC100 and PC133 standards. 2256:

Wider mode registers (DDR2 and up use 13 bits, A0–A12)

1825:

a strobe, but rather simply a command bit. Along with

7422:"Samsung 50nm 2GB DDR3 chips are industry's smallest" 7328:"Samsung Shows Industry's First 2-Gigabit DDR2 SDRAM" 5880:- Flash website built by Tel-Aviv University students 3391: 1779:, which are sampled on the rising edge of the clock: 1731: 611: 2972:

with PC66 and was superseded by the PC133 standard.

2510:

clock frequency to translate that limit into cycles.

6651:

128M-BIT VirtualChannel SDRAM preliminary datasheet

6554: 6020: 6018: 3443: 3381:, which always write in multiples of a cache line. 7140: 7138: 6288:"IDF: "DDR3 won't catch up with DDR2 during 2009"" 6245:"G.SKILL Announces DDR3 Memory Kit For Ivy Bridge" 6135: 6133: 6131: 5887:, a master thesis from the University of Maryland. 3369:CMD0 selects the DCLK pair to use (DCLK1 or DCLK0) 2570: 1744: 1666:, an electronics industry association that adopts 6197:"Pipe Dreams: Six P35-DDR3 Motherboards Compared" 6194: 3680:Synchronous dynamic random-access memory (SDRAM) 3193: 2506:M8, M7: Operating mode. Reserved, and must be 00. 2250:Additional address bits to support larger devices 8316: 7380:ATI engineers by way of Beyond 3D's Dave Baumann 6242: 6015: 3487:HM5283206, introduced in November 1994, and the 2579:located on a common physical row in the memory. 1821:, row address strobe. Despite the name, this is 7135: 6366: 6351:(in German). hardware-infos.com. Archived from 6326:. Xbitlabs.com. August 16, 2010. Archived from 6142:"The outlook for DRAMs in consumer electronics" 6128: 1891:The SDR SDRAM commands are defined as follows: 7979:133 MHz PC133 SDRAM SO-DIMM Specification 7659: 7657: 7604:"16M-BIT SYNCHRONOUS GRAPHICS RAM: μPD4811650" 6500: 3600:(HBM) is a high-performance RAM interface for 3586: 2949:is a standard for internal removable computer 2763:Internal operations are at 1/2 the clock rate. 2279:is high, other commands are the same as above. 8004: 7816: 7814: 7223: 7221: 7219: 7217: 7215: 7213: 7211: 6862: 6860: 6858: 6856: 6854: 6230:"Super Talent & TEAM: DDR3-1600 Is Here!" 5792: 5714: 5678: 5436: 5402: 5229: 5165: 5122: 4684: 3995: 3955: 3339:5 or 4 bits spare for row or column expansion 2987:is a computer memory standard defined by the 2317:Once the row has been activated or "opened", 2283: 1494: 7383: 7072: 7070: 7068: 6916: 6914: 6802: 6800: 6798: 6679: 6677: 6597:(data sheet), pp. 32–33, archived from 3511:Graphics double data rate SDRAM (GDDR SDRAM) 3223:SLDRAM Read, write or row op request packet 2419: 7654: 7320: 7174: 7172: 7006: 7004: 6587: 5958: 3319: 3299: 3291: 3288: 3282: 3268: 2804:point-to-point (single module per channel) 8011: 7997: 7811: 7505:"Samsung Unleashes a Roomy DDR4 256GB RAM" 7208: 6885: 6851: 6766: 6764: 6710: 6708: 6227: 6038:(15–21). Hayden Publishing Company. 1993. 5959:Jacob, B.; Ng, S. W.; Wang, D. T. (2008). 5874:- EEPROM with timing data on SDRAM modules 3533:designed to be used as the main memory of 3350:A read/write command had the msbit clear: 2903:-based PCs. It also features in the Beige 1501: 1487: 7065: 6911: 6795: 6674: 6624:HYB39V64x0yT 64MBit Virtual Channel SDRAM 6558:HYSL8M18D600A 600 Mb/s/pin 8M x 18 SLDRAM 6531: 5904: 5072:Synchronous graphics random-access memory 3212:. (1 MT/s = 1000^2 transfers per second) 2455:will generally access memory in units of 7899: 7601: 7169: 7001: 6591:SLD4M18DR400 400 Mb/s/pin 4M x 18 SLDRAM 6064: 6062: 6060: 6058: 6056: 6054: 6052: 6050: 6048: 3476:nature of other video RAM technologies. 2937: 2814: 2287: 1588: 1522:Synchronous dynamic random-access memory 1512: 7905: 7352: 7109: 7107: 7105: 6978: 6976: 6974: 6761: 6705: 6397: 6099:"Nanya 256 Mb DDR SDRAM Datasheet" 5932:B. Jacob; S. W. Ng; D. T. Wang (2008). 2842:that read or write 64 (non-ECC) or 72 ( 2391: 1869: 8317: 7820: 7789: 7391:"Our Proud Heritage from 2000 to 2009" 6988:STOL (Semiconductor Technology Online) 6426:"DDR3 Will be Cheaper, Faster in 2009" 6423: 6398:Gruener, Wolfgang (February 4, 2009). 6139: 3181: 2876:refers to internal removable computer 2819:The 64 MB of sound memory on the 2271:of the activate command. A new signal 1878: 7992: 7448:"Our Proud Heritage from 2010 to Now" 6506: 6045: 5111: 5101: 3713: 3703: 3479:The earliest known SGRAM memory are 8 3363:CMD2=1 for a write, CMD2=0 for a read 1849:, this selects one of eight commands. 1833:, this selects one of eight commands. 1042:Vision Electronic Recording Apparatus 7360:"ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資" 7102: 6971: 6349:"IDF: DDR4 memory targeted for 2012" 5989:IEEE Journal of Solid-State Circuits 5115: 3717: 3637: 3626:Random-access memory § Timeline 3483:Mbit chips dating back to 1994: the 3409:. In the late 1990s, a number of PC 3173: 2931:For the Japanese home computer, see 2440:time, three cycles may be required. 7608:NEC Device Technology International 7537:"Hitachi HM5283206FP10 8Mbit SGRAM" 6848:page 118 "High-Bandwidth DRAM" 6647: 13: 7513:. 6 September 2018. Archived from 6555:Hyundai Electronics (1997-12-20), 6243:Jennifer Johnson (24 April 2012). 6215:"AMD to Adopt DDR3 in Three Years" 6195:Thomas Soderstrom (June 5, 2007). 3392:Virtual channel memory (VCM) SDRAM 2538: 1810: 1770: 203:Data validation and reconciliation 14: 8341: 7952: 5962:Memory Systems: Cache, DRAM, Disk 5935:Memory Systems: Cache, DRAM, Disk 3316: 3313: 3310: 3302: 2446: 2211: 2208: 2205: 2185: 2179: 2159: 2006: 2003: 2000: 1980: 1977: 1974: 1954: 1951: 1948: 1945: 1942: 1939: 1613:invented DDR SDRAM, they built a 253:Distributed file system for cloud 7906:Killian, Zak (18 January 2018). 7790:Shilov, Anton (March 29, 2016). 7370:from the original on 2016-08-13. 5965:. Morgan Kaufmann. p. 333. 5938:. Morgan Kaufmann. p. 324. 5840:(graphics DDR) and its subtypes 5065: 3642: 3444:Synchronous Graphics RAM (SGRAM) 2915:. It is also used in many early 2490: 101:Areal density (computer storage) 7974:PC SDRAM Specification, Rev 1.7 7922: 7873: 7842: 7821:Shilov, Anton (July 19, 2017). 7783: 7771:from the original on 2022-01-24 7747: 7715: 7689: 7622: 7595: 7567: 7555:from the original on 2003-07-16 7529: 7497: 7471: 7440: 7414: 7374: 7286:"Elpida ships 2GB DDR2 modules" 7278: 7246: 7196:from the original on 2017-02-27 7053:from the original on 2019-06-21 7029: 6950: 6938:from the original on 2019-06-21 6832: 6773:NEC Application Specific Memory 6736: 6664:from the original on 2013-12-03 6641: 6637:from the original on 2018-11-12 6614: 6581: 6548: 6525: 6482: 6464: 6443: 6428:. dailytech.com. Archived from 6424:Jansen, Ng (January 20, 2009). 6417: 6391: 6341: 6316: 6298: 6280: 6262: 6251: 6236: 6221: 6207: 6188: 6174: 6159: 3285: 3274: 3271: 3265: 3117:The DDR4 chips run at 1.2 3105:DDR4 SDRAM is the successor to 2821:Sound Blaster X-Fi Fatality Pro 2571:DDR SDRAM prefetch architecture 2525: 2451:A modern microprocessor with a 2228: 2225: 2222: 2219: 2202: 2199: 2196: 2193: 2182: 2176: 2173: 2170: 2167: 2156: 2150: 2147: 2144: 2141: 2127: 2124: 2121: 2118: 2107: 2101: 2098: 2095: 2092: 2081: 2075: 2072: 2069: 2066: 2055: 2049: 2046: 2043: 2040: 2029: 2023: 2020: 2017: 2014: 1997: 1994: 1991: 1988: 1971: 1968: 1965: 1962: 1958:Command inhibit (no operation) 1936: 920:Programmable metallization cell 6270:"DDR4 not expected until 2015" 6119: 6091: 5979: 5952: 5925: 5898: 3634:Transistor count § Memory 3413:chipsets (such as the popular 3194:Synchronous-link DRAM (SLDRAM) 2942:DIMM: 168 pins and two notches 2659: 483:Persistence (computer science) 1: 8293: 6621:Siemens Semiconductor Group, 6402:. tgdaily.com. Archived from 5891: 3503:, starting with the Japanese 1351:Electronic quantum holography 8020:Dynamic random-access memory 7970:, May 2011, Hardware Secrets 6967:. February 1996. p. 40. 6564:(data sheet), archived from 6228:Wesly Fink (July 20, 2007). 6140:Graham, Allan (2007-01-12). 3630:Flash memory § Timeline 3460:. It adds functions such as 3417:) included VCSDRAM support. 3336:10 or 11 bits of row address 3031:DDR SDRAM (sometimes called 702:Video RAM (dual-ported DRAM) 498:Non-RAID drive architectures 7: 7755:"K4W1G1646G-BC08 Datasheet" 5831: 3619: 3587:High Bandwidth Memory (HBM) 3529:) is a type of specialized 2919:systems with a 66 MHz 2834:Originally simply known as 2292:SDRAM memory module, zoomed 2253:Additional bank select bits 1886: 1857:, write enable. Along with 1685:SDRAM is also available in 10: 8346: 6588:SLDRAM Inc. (1998-07-09), 6507:Smith, Ryan (2020-07-14). 3623: 3590: 3514: 3440:(256 bytes) in a segment. 3162: 3098: 3068: 3046: 3015: 2930: 2895:This standard was used by 2787:Much longer CAS latencies 2284:Construction and operation 2237: 2214: 2188: 2162: 2136: 2113: 2087: 2061: 2035: 2009: 1983: 1957: 1584: 1291:Holographic Versatile Disc 1190:Compact Disc Digital Audio 1062:Magnetic-tape data storage 681:Content-addressable memory 18: 8281: 8248: 8220: 8152: 8048: 8027: 7968:Understanding RAM Timings 7312:: CS1 maint: unfit URL ( 5867:List of device bandwidths 5649: 5642: 5639: 5632: 5627: 5519: 5512: 5509: 5388: 5381: 5378: 5371: 5368: 5362: 5355: 5352: 4998: 4995: 4816: 4813: 4793: 4786: 4783: 4758: 4755: 4717: 4645: 4638: 4635: 4517: 4400: 4397: 4362: 4330: 4219: 4216: 4111: 4108: 4041: 4038: 3768: 3651:This section needs to be 3535:graphics processing units 3109:. It was revealed at the 2791: 2773: 2754:"Burst terminate" removed 2746: 2703: 2677: 2672: 2669: 2483:for its microprocessors. 2420:Interrupting a read burst 2269:DDR4 changes the encoding 2234: 2133: 1719: 1636:) followed soon after by 488:Persistent data structure 383:Digital rights management 6893:"KM48SL2000-7 Datasheet" 6532:Dean Kent (1998-10-24), 6088:based on powers of 1024. 3674: 3342:7 bits of column address 2979: 2926: 2880:standard defined by the 2756:4 units used in parallel 2610:in multiple data words. 1363:DNA digital data storage 1346:Holographic data storage 835:Solid-state hybrid drive 121:Network-attached storage 8330:South Korean inventions 7545:Smithsonian Institution 6957:"Ultra 64 Tech Specs". 3158: 3094: 3064: 3042: 2868: 1801:data mask. (The letter 1526:synchronous dynamic RAM 1358:5D optical data storage 1175:3D optical data storage 898:Universal Flash Storage 303:Replication (computing) 248:Distributed file system 138:Single-instance storage 116:Direct-attached storage 96:Continuous availability 16:Type of computer memory 7697:"K4D553238F Datasheet" 7602:Takeuchi, Kei (1998). 7364:pc.watch.impress.co.jp 6922:"MSM5718C50/MD5764802" 5872:Serial presence detect 3333:3 bits of bank address 3011: 2943: 2859:extended data out DRAM 2831: 2810: 2293: 1746: 1745:{\displaystyle 10^{6}} 1602: 1518: 1231:Nintendo optical discs 448:Storage virtualization 318:Information repository 258:Distributed data store 7855:Samsung Semiconductor 7728:Samsung Semiconductor 7635:Samsung Semiconductor 7453:Samsung Semiconductor 7396:Samsung Semiconductor 7333:Samsung Semiconductor 7259:Samsung Semiconductor 6780:. Fall 1995. p. 6453:. Samsung. 2011-01-04 6182:"What is DDR memory?" 5083:Date of introduction 5076:High Bandwidth Memory 3685:Date of introduction 3598:High Bandwidth Memory 3593:High Bandwidth Memory 3111:Intel Developer Forum 3008:with PC100 and PC66. 2941: 2818: 2291: 1755:Another limit is the 1747: 1597:SDRAM ICs on a PC100 1592: 1516: 734:Mellon optical memory 722:Williams–Kilburn tube 438:Locality of reference 243:Clustered file system 69:Memory access pattern 7576:UPD4811650 Datasheet 6330:on December 19, 2010 6167:"SDRAM Part Catalog" 3151:at 1.2 V, uses 2951:random-access memory 2392:Command interactions 1870:Bank selection (BAn) 1729: 1561:finite-state machine 1430:Magnetic-core memory 1077:Digital Data Storage 1037:Quadruplex videotape 478:In-memory processing 368:Information transfer 263:Distributed database 126:Storage area network 106:Block (data storage) 7762:Samsung Electronics 7701:Samsung Electronics 7670:Samsung Electronics 7428:. 29 September 2008 7340:. 20 September 2004 7151:Samsung Electronics 7083:Samsung Electronics 6820:. 17 September 1998 6813:Samsung Electronics 6717:μPD481850 Datasheet 6686:HM5283206 Datasheet 6217:. 28 November 2005. 6026:"Electronic Design" 6001:1990IJSSC..25.1118K 5079: 3681: 3581:Samsung Electronics 3415:VIA KX133 and KT133 3327:9 bits of device ID 3224: 3182:Rambus DRAM (RDRAM) 3006:backward compatible 2970:backward compatible 2863:fast page mode DRAM 2666: 2470:For the sequential 1879:Addressing (A10/An) 1702:Samsung Electronics 1638:Hyundai Electronics 1545:integrated circuits 1517:SDRAM memory module 1027:Phonograph cylinder 965:Electrochemical RAM 817:Solid-state storage 433:Memory segmentation 131:Block-level storage 8144:Hybrid Memory Cube 7887:. January 18, 2018 7735:. October 26, 2005 7189:. April 21, 2003. 7123:. 17 February 2005 7090:. 10 February 1999 6844:2015-02-06 at the 6693:. 11 November 1994 5905:P. Darche (2020). 5070: 3679: 3501:video game console 3222: 3139:In February 2009, 2991:. PC133 refers to 2944: 2846:) bits at a time. 2832: 2826:is built from two 2779:Access is ≥8 words 2752:Access is ≥4 words 2712:Access is ≥2 words 2665:SDRAM feature map 2664: 2294: 1742: 1615:dual-edge clocking 1609:In the late 1980s 1603: 1519: 1436:Plated-wire memory 1401:Paper data storage 1047:Magnetic recording 473:In-memory database 458:Memory-mapped file 403:Volume boot record 398:Master boot record 388:Volume (computing) 363:Data communication 288:Data deduplication 8312: 8311: 7936:. 18 January 2018 7764:. November 2010. 7266:. 29 January 2003 7046:. 12 March 1998. 6931:. February 1999. 6929:Oki Semiconductor 6839:ISSCC 2014 Trends 6724:. 6 December 1994 6535:RAM Guide: SLDRAM 6492:(Press release). 6376:(Press release). 6276:. 16 August 2010. 6171:070928 micron.com 6148:. AspenCore Media 6031:Electronic Design 5829: 5828: 5063: 5062: 3672: 3671: 3407:memory controller 3330:6 bits of command 3324: 3323: 3174:Failed successors 3153:pseudo open drain 2953:, defined by the 2808: 2807: 2383:delay between an 2244: 2243: 1710:Micron Technology 1511: 1510: 1108:8 mm video format 1032:Phonograph record 851:Flash Core Module 829:Solid-state drive 728:Delay-line memory 687:Computational RAM 590:Scratchpad memory 428:Disk partitioning 153:Unstructured data 79:Secondary storage 8337: 8304:Transistor count 8013: 8006: 7999: 7990: 7989: 7946: 7945: 7943: 7941: 7926: 7920: 7919: 7917: 7915: 7903: 7897: 7896: 7894: 7892: 7877: 7871: 7870: 7868: 7866: 7846: 7840: 7839: 7837: 7835: 7818: 7809: 7808: 7806: 7804: 7787: 7781: 7780: 7778: 7776: 7770: 7759: 7751: 7745: 7744: 7742: 7740: 7719: 7713: 7712: 7710: 7708: 7693: 7687: 7686: 7684: 7682: 7677:. 28 August 2003 7661: 7652: 7651: 7649: 7647: 7626: 7620: 7619: 7617: 7615: 7599: 7593: 7592: 7590: 7588: 7571: 7565: 7564: 7562: 7560: 7554: 7541: 7533: 7527: 7526: 7524: 7522: 7517:on June 21, 2019 7501: 7495: 7494: 7492: 7490: 7475: 7469: 7468: 7466: 7464: 7444: 7438: 7437: 7435: 7433: 7418: 7412: 7411: 7409: 7407: 7387: 7381: 7378: 7372: 7371: 7356: 7350: 7349: 7347: 7345: 7324: 7318: 7317: 7311: 7303: 7301: 7299: 7282: 7276: 7275: 7273: 7271: 7250: 7244: 7243: 7241: 7239: 7229:"History: 2000s" 7225: 7206: 7205: 7203: 7201: 7195: 7184: 7176: 7167: 7166: 7164: 7162: 7142: 7133: 7132: 7130: 7128: 7111: 7100: 7099: 7097: 7095: 7074: 7063: 7062: 7060: 7058: 7052: 7041: 7033: 7027: 7026: 7024: 7022: 7012:"History: 1990s" 7008: 6999: 6998: 6996: 6994: 6980: 6969: 6968: 6954: 6948: 6947: 6945: 6943: 6937: 6926: 6918: 6909: 6908: 6906: 6904: 6889: 6883: 6882: 6880: 6878: 6868:"History: 2010s" 6864: 6849: 6836: 6830: 6829: 6827: 6825: 6804: 6793: 6792: 6790: 6788: 6768: 6759: 6758: 6756: 6754: 6740: 6734: 6733: 6731: 6729: 6712: 6703: 6702: 6700: 6698: 6681: 6672: 6671: 6670: 6669: 6663: 6656: 6645: 6639: 6638: 6636: 6629: 6618: 6612: 6611: 6610: 6609: 6603: 6596: 6585: 6579: 6578: 6577: 6576: 6570: 6563: 6552: 6546: 6545: 6544: 6543: 6538:, Tom's Hardware 6529: 6523: 6522: 6520: 6519: 6504: 6498: 6497: 6496:. 30 March 2017. 6486: 6480: 6479: 6468: 6462: 6461: 6459: 6458: 6447: 6441: 6440: 6438: 6437: 6432:on June 22, 2009 6421: 6415: 6414: 6412: 6411: 6395: 6389: 6388: 6386: 6385: 6370: 6364: 6363: 6361: 6360: 6345: 6339: 6338: 6336: 6335: 6320: 6314: 6313: 6302: 6296: 6295: 6284: 6278: 6277: 6274:semiaccurate.com 6266: 6260: 6258:DDR4 PDF page 23 6255: 6249: 6248: 6240: 6234: 6233: 6225: 6219: 6218: 6211: 6205: 6204: 6192: 6186: 6185: 6178: 6172: 6170: 6163: 6157: 6156: 6154: 6153: 6137: 6126: 6123: 6117: 6116: 6114: 6113: 6103: 6095: 6089: 6066: 6043: 6042: 6022: 6013: 6012: 5983: 5977: 5976: 5956: 5950: 5949: 5929: 5923: 5922: 5902: 5794: 5716: 5680: 5438: 5404: 5231: 5167: 5124: 5117: 5099:Manufacturer(s) 5080: 5069: 4686: 3997: 3957: 3719: 3701:Manufacturer(s) 3682: 3678: 3667: 3664: 3658: 3646: 3645: 3638: 3575: 3523:double data rate 3482: 3225: 3221: 3025:double data rate 2803: 2760: 2731: 2726: 2690: 2673:Feature changes 2667: 2663: 2594:device is 2,048 2496:register write. 2278: 2274: 1914: 1909: 1904: 1899: 1894: 1893: 1864: 1860: 1855: 1848: 1844: 1839: 1832: 1828: 1819: 1793: 1751: 1749: 1748: 1743: 1741: 1740: 1714:Nanya Technology 1632: 1625:SDRAM, known as 1623:double data rate 1503: 1496: 1489: 1448:Thin-film memory 1442:Core rope memory 1368:Universal memory 1331:Millipede memory 1321:Racetrack memory 1286:Ultra HD Blu-ray 1098:Linear Tape-Open 1052:Magnetic storage 1020:Analog recording 463:Software entropy 423:Disk aggregation 183:Data degradation 168:Data compression 64:Memory hierarchy 54:Memory coherence 26: 25: 8345: 8344: 8340: 8339: 8338: 8336: 8335: 8334: 8315: 8314: 8313: 8308: 8277: 8244: 8216: 8148: 8096:Fast Cycle DRAM 8044: 8023: 8017: 7961:, August 2010, 7955: 7950: 7949: 7939: 7937: 7928: 7927: 7923: 7913: 7911: 7904: 7900: 7890: 7888: 7879: 7878: 7874: 7864: 7862: 7848: 7847: 7843: 7833: 7831: 7819: 7812: 7802: 7800: 7788: 7784: 7774: 7772: 7768: 7757: 7753: 7752: 7748: 7738: 7736: 7721: 7720: 7716: 7706: 7704: 7695: 7694: 7690: 7680: 7678: 7663: 7662: 7655: 7645: 7643: 7628: 7627: 7623: 7613: 7611: 7600: 7596: 7586: 7584: 7583:. December 1997 7573: 7572: 7568: 7558: 7556: 7552: 7539: 7535: 7534: 7530: 7520: 7518: 7503: 7502: 7498: 7488: 7486: 7485:. July 17, 2018 7477: 7476: 7472: 7462: 7460: 7446: 7445: 7441: 7431: 7429: 7420: 7419: 7415: 7405: 7403: 7389: 7388: 7384: 7379: 7375: 7358: 7357: 7353: 7343: 7341: 7326: 7325: 7321: 7305: 7304: 7297: 7295: 7284: 7283: 7279: 7269: 7267: 7252: 7251: 7247: 7237: 7235: 7227: 7226: 7209: 7199: 7197: 7193: 7182: 7178: 7177: 7170: 7160: 7158: 7144: 7143: 7136: 7126: 7124: 7113: 7112: 7103: 7093: 7091: 7076: 7075: 7066: 7056: 7054: 7050: 7039: 7035: 7034: 7030: 7020: 7018: 7010: 7009: 7002: 6992: 6990: 6982: 6981: 6972: 6963:. No. 14. 6960:Next Generation 6956: 6955: 6951: 6941: 6939: 6935: 6924: 6920: 6919: 6912: 6902: 6900: 6891: 6890: 6886: 6876: 6874: 6866: 6865: 6852: 6846:Wayback Machine 6837: 6833: 6823: 6821: 6806: 6805: 6796: 6786: 6784: 6770: 6769: 6762: 6752: 6750: 6742: 6741: 6737: 6727: 6725: 6714: 6713: 6706: 6696: 6694: 6683: 6682: 6675: 6667: 6665: 6661: 6654: 6646: 6642: 6634: 6627: 6619: 6615: 6607: 6605: 6601: 6594: 6586: 6582: 6574: 6572: 6568: 6561: 6553: 6549: 6541: 6539: 6530: 6526: 6517: 6515: 6505: 6501: 6488: 6487: 6483: 6470: 6469: 6465: 6456: 6454: 6449: 6448: 6444: 6435: 6433: 6422: 6418: 6409: 6407: 6406:on May 24, 2009 6396: 6392: 6383: 6381: 6372: 6371: 6367: 6358: 6356: 6347: 6346: 6342: 6333: 6331: 6322: 6321: 6317: 6304: 6303: 6299: 6286: 6285: 6281: 6268: 6267: 6263: 6256: 6252: 6241: 6237: 6226: 6222: 6213: 6212: 6208: 6193: 6189: 6180: 6179: 6175: 6165: 6164: 6160: 6151: 6149: 6138: 6129: 6124: 6120: 6111: 6109: 6101: 6097: 6096: 6092: 6086:binary prefixes 6067: 6046: 6024: 6023: 6016: 6009:10.1109/4.62132 5984: 5980: 5973: 5957: 5953: 5946: 5930: 5926: 5919: 5903: 5899: 5894: 5834: 5068: 3677: 3668: 3662: 3659: 3656: 3647: 3643: 3636: 3622: 3595: 3589: 3579:memory chip by 3573: 3519: 3513: 3480: 3446: 3394: 3300:Row (continued) 3196: 3184: 3176: 3167: 3161: 3103: 3097: 3073: 3067: 3051: 3045: 3020: 3014: 2982: 2936: 2929: 2871: 2813: 2801: 2797: 2786: 2780: 2764: 2762: 2758: 2757: 2755: 2753: 2742: 2729: 2724: 2720: 2699: 2688: 2684: 2662: 2573: 2554: 2541: 2539:Low power modes 2534: 2528: 2493: 2449: 2422: 2412: 2408: 2404: 2400: 2394: 2382: 2375: 2333:command, and a 2328: 2286: 2276: 2272: 2239: 1912: 1907: 1902: 1897: 1889: 1881: 1872: 1862: 1858: 1853: 1846: 1842: 1837: 1830: 1826: 1817: 1813: 1811:Command signals 1791: 1773: 1771:Control signals 1736: 1732: 1730: 1727: 1726: 1722: 1630: 1587: 1507: 1478: 1477: 1396: 1388: 1387: 1341:Patterned media 1311: 1303: 1302: 1170: 1160: 1159: 1155:Hard disk drive 1022: 1012: 1011: 992: 981: 980: 935: 925: 924: 846:IBM FlashSystem 841:USB flash drive 780: 763: 762: 717: 709: 708: 697:Dual-ported RAM 575: 558: 557: 518:Cloud computing 378:Copy protection 298:Data redundancy 228:Shared resource 198:Data validation 173:Data corruption 148:Structured data 59:Cache coherence 44: 30:Computer memory 24: 17: 12: 11: 5: 8343: 8333: 8332: 8327: 8310: 8309: 8307: 8306: 8301: 8296: 8294:SDRAM timeline 8291: 8285: 8283: 8279: 8278: 8276: 8275: 8270: 8265: 8260: 8254: 8252: 8250:Memory modules 8246: 8245: 8243: 8242: 8237: 8232: 8226: 8224: 8218: 8217: 8215: 8214: 8213: 8212: 8207: 8202: 8197: 8192: 8187: 8182: 8172: 8167: 8162: 8156: 8154: 8150: 8149: 8147: 8146: 8141: 8140: 8139: 8134: 8129: 8124: 8119: 8109: 8104: 8099: 8093: 8087: 8086: 8085: 8080: 8075: 8070: 8060: 8054: 8052: 8046: 8045: 8043: 8042: 8037: 8031: 8029: 8025: 8024: 8016: 8015: 8008: 8001: 7993: 7987: 7986: 7981: 7976: 7971: 7965: 7954: 7953:External links 7951: 7948: 7947: 7921: 7898: 7872: 7841: 7810: 7782: 7746: 7714: 7688: 7653: 7642:. 12 July 1999 7621: 7594: 7566: 7528: 7510:Tom's Hardware 7496: 7470: 7439: 7413: 7382: 7373: 7351: 7319: 7277: 7245: 7207: 7168: 7134: 7101: 7064: 7037:"Direct RDRAM" 7028: 7000: 6970: 6949: 6910: 6884: 6850: 6831: 6794: 6760: 6735: 6704: 6673: 6640: 6613: 6580: 6547: 6524: 6499: 6481: 6463: 6442: 6416: 6390: 6365: 6340: 6315: 6297: 6279: 6261: 6250: 6235: 6220: 6206: 6201:Tom's Hardware 6187: 6173: 6158: 6127: 6118: 6090: 6044: 6014: 5978: 5971: 5951: 5944: 5924: 5917: 5911:. p. 59. 5896: 5895: 5893: 5890: 5889: 5888: 5881: 5878:SDRAM Tutorial 5875: 5869: 5864: 5833: 5830: 5827: 5826: 5824: 5821: 5816: 5811: 5808: 5801: 5798: 5795: 5789: 5788: 5786: 5779: 5776: 5773: 5770: 5767: 5764: 5757: 5753: 5752: 5750: 5743: 5740: 5735: 5732: 5727: 5724: 5717: 5711: 5710: 5708: 5705: 5702: 5699: 5694: 5687: 5684: 5683:MT58K256M32JA 5681: 5675: 5674: 5669: 5662: 5655: 5651: 5650: 5648: 5641: 5638: 5631: 5626: 5625:SGRAM (GDDR3) 5623: 5620: 5613: 5609: 5608: 5606: 5603: 5600: 5593: 5590: 5589:SGRAM (GDDR3) 5587: 5584: 5581: 5577: 5576: 5571: 5568: 5567:SGRAM (GDDR5) 5565: 5562: 5555: 5551: 5550: 5545: 5542: 5535: 5532: 5525: 5521: 5520: 5518: 5511: 5508: 5501: 5496: 5495:SGRAM (GDDR4) 5493: 5490: 5483: 5479: 5478: 5476: 5469: 5466: 5459: 5456: 5449: 5446: 5439: 5433: 5432: 5430: 5427: 5424: 5417: 5414: 5411: 5408: 5405: 5399: 5398: 5390: 5389: 5387: 5380: 5377: 5370: 5367: 5366:SGRAM (GDDR2) 5364: 5361: 5354: 5350: 5349: 5347: 5340: 5337: 5330: 5327: 5320: 5317: 5310: 5306: 5305: 5303: 5300: 5297: 5290: 5287: 5284: 5281: 5278: 5274: 5273: 5271: 5264: 5261: 5254: 5249: 5242: 5239: 5232: 5230:September 1998 5226: 5225: 5223: 5220: 5217: 5214: 5211: 5208: 5205: 5202: 5198: 5197: 5195: 5192: 5189: 5182: 5177: 5174: 5171: 5168: 5162: 5161: 5159: 5156: 5151: 5146: 5141: 5131: 5128: 5125: 5119: 5118: 5113: 5110: 5105: 5100: 5097: 5094: 5087: 5084: 5067: 5064: 5061: 5060: 5058: 5051: 5048: 5045: 5042: 5039: 5035: 5034: 5032: 5025: 5020: 5015: 5012: 5007: 5004: 4997: 4993: 4992: 4990: 4983: 4980: 4977: 4974: 4971: 4968: 4961: 4957: 4956: 4954: 4947: 4944: 4941: 4938: 4935: 4932: 4925: 4921: 4920: 4918: 4911: 4908: 4903: 4900: 4895: 4888: 4881: 4877: 4876: 4874: 4867: 4864: 4859: 4856: 4851: 4847: 4846: 4844: 4837: 4834: 4831: 4828: 4825: 4822: 4815: 4811: 4810: 4805: 4802: 4799: 4795: 4794: 4792: 4785: 4782: 4777: 4774: 4771: 4764: 4757: 4753: 4752: 4745: 4742: 4739: 4736: 4733: 4730: 4723: 4719: 4718: 4716: 4709: 4706: 4703: 4700: 4697: 4694: 4687: 4681: 4680: 4673: 4670: 4665: 4658: 4651: 4647: 4646: 4644: 4637: 4634: 4631: 4628: 4625: 4622: 4615: 4611: 4610: 4608: 4601: 4598: 4595: 4592: 4589: 4586: 4578: 4577: 4575: 4568: 4565: 4562: 4559: 4556: 4553: 4547: 4546: 4544: 4541: 4538: 4533: 4532:Sony, Toshiba 4530: 4527: 4524: 4519: 4515: 4514: 4512: 4505: 4502: 4499: 4496: 4493: 4490: 4483: 4479: 4478: 4476: 4469: 4466: 4459: 4456: 4453: 4449: 4448: 4446: 4439: 4436: 4431: 4425: 4424: 4422: 4415: 4412: 4405: 4402: 4399: 4395: 4394: 4392: 4385: 4382: 4379: 4376: 4371: 4368: 4360: 4359: 4357: 4354: 4351: 4346: 4345:Sony, Toshiba 4343: 4340: 4337: 4332: 4328: 4327: 4325: 4318: 4315: 4308: 4305: 4302: 4299: 4292: 4288: 4287: 4285: 4278: 4275: 4270: 4267: 4262: 4254: 4253: 4251: 4244: 4241: 4234: 4231: 4228: 4225: 4218: 4214: 4213: 4211: 4208: 4205: 4200: 4191: 4186: 4183: 4178: 4174: 4173: 4171: 4164: 4161: 4156: 4153: 4150: 4146: 4145: 4143: 4136: 4133: 4126: 4123: 4120: 4117: 4110: 4106: 4105: 4103: 4096: 4093: 4086: 4083: 4080: 4076: 4075: 4073: 4066: 4063: 4056: 4053: 4050: 4047: 4040: 4036: 4035: 4033: 4026: 4023: 4016: 4013: 4008: 4005: 3998: 3992: 3991: 3989: 3982: 3979: 3972: 3967: 3964: 3961: 3958: 3952: 3951: 3949: 3946: 3943: 3936: 3933: 3930: 3927: 3924: 3920: 3919: 3917: 3910: 3905: 3898: 3893: 3890: 3887: 3880: 3876: 3875: 3873: 3866: 3863: 3858: 3853: 3850: 3847: 3839: 3838: 3836: 3829: 3826: 3819: 3814: 3811: 3808: 3802: 3801: 3799: 3796: 3793: 3786: 3781: 3776: 3773: 3770: 3766: 3765: 3763: 3756: 3751: 3744: 3739: 3734: 3728: 3725: 3721: 3720: 3715: 3712: 3707: 3702: 3699: 3696: 3689: 3686: 3676: 3673: 3670: 3669: 3650: 3648: 3641: 3621: 3618: 3591:Main article: 3588: 3585: 3515:Main article: 3512: 3509: 3450:texture memory 3445: 3442: 3393: 3390: 3371: 3370: 3367: 3364: 3361: 3358: 3355: 3344: 3343: 3340: 3337: 3334: 3331: 3328: 3322: 3321: 3318: 3315: 3312: 3309: 3305: 3304: 3301: 3298: 3294: 3293: 3290: 3287: 3284: 3281: 3277: 3276: 3273: 3270: 3267: 3264: 3260: 3259: 3256: 3253: 3250: 3247: 3244: 3241: 3238: 3235: 3232: 3229: 3195: 3192: 3183: 3180: 3175: 3172: 3163:Main article: 3160: 3157: 3123:data transfers 3099:Main article: 3096: 3093: 3069:Main article: 3066: 3063: 3047:Main article: 3044: 3041: 3016:Main article: 3013: 3010: 2981: 2978: 2928: 2925: 2870: 2867: 2861:(EDO-RAM) and 2812: 2809: 2806: 2805: 2799: 2795: 2789: 2788: 2777: 2771: 2770: 2750: 2744: 2743: 2741: 2740: 2733: 2727: 2722: 2718: 2716:Double clocked 2713: 2709: 2707: 2701: 2700: 2698: 2697: 2691: 2686: 2681: 2679: 2675: 2674: 2671: 2661: 2658: 2657: 2656: 2650: 2644: 2638: 2632: 2572: 2569: 2552: 2540: 2537: 2532: 2527: 2524: 2519: 2518: 2514: 2511: 2507: 2504: 2492: 2489: 2448: 2447:Burst ordering 2445: 2421: 2418: 2410: 2406: 2402: 2398: 2393: 2390: 2380: 2373: 2326: 2285: 2282: 2281: 2280: 2266: 2263: 2260: 2257: 2254: 2251: 2242: 2241: 2236: 2233: 2230: 2227: 2224: 2221: 2217: 2216: 2213: 2210: 2207: 2204: 2201: 2198: 2195: 2191: 2190: 2187: 2184: 2181: 2178: 2175: 2172: 2169: 2165: 2164: 2161: 2158: 2155: 2152: 2149: 2146: 2143: 2139: 2138: 2135: 2132: 2129: 2126: 2123: 2120: 2116: 2115: 2112: 2109: 2106: 2103: 2100: 2097: 2094: 2090: 2089: 2086: 2083: 2080: 2077: 2074: 2071: 2068: 2064: 2063: 2060: 2057: 2054: 2051: 2048: 2045: 2042: 2038: 2037: 2034: 2031: 2028: 2025: 2022: 2019: 2016: 2012: 2011: 2008: 2005: 2002: 1999: 1996: 1993: 1990: 1986: 1985: 1982: 1979: 1976: 1973: 1970: 1967: 1964: 1960: 1959: 1956: 1953: 1950: 1947: 1944: 1941: 1938: 1934: 1933: 1930: 1924: 1921: 1915: 1910: 1905: 1900: 1888: 1885: 1880: 1877: 1871: 1868: 1867: 1866: 1850: 1834: 1812: 1809: 1808: 1807: 1796: 1788: 1772: 1769: 1739: 1735: 1721: 1718: 1668:open standards 1653:burst EDO DRAM 1586: 1583: 1509: 1508: 1506: 1505: 1498: 1491: 1483: 1480: 1479: 1476: 1475: 1469: 1463: 1460:Twistor memory 1457: 1451: 1445: 1439: 1433: 1427: 1421: 1416: 1410: 1404: 1397: 1394: 1393: 1390: 1389: 1386: 1385: 1380: 1378:Quantum memory 1375: 1370: 1365: 1360: 1355: 1354: 1353: 1343: 1338: 1333: 1328: 1323: 1318: 1312: 1310:In development 1309: 1308: 1305: 1304: 1301: 1300: 1295: 1294: 1293: 1288: 1283: 1278: 1273: 1268: 1263: 1258: 1253: 1248: 1243: 1238: 1233: 1228: 1223: 1221:Super Video CD 1218: 1213: 1208: 1203: 1198: 1193: 1187: 1182: 1171: 1166: 1165: 1162: 1161: 1158: 1157: 1152: 1151: 1150: 1145: 1140: 1135: 1130: 1125: 1120: 1115: 1110: 1105: 1100: 1095: 1090: 1085: 1080: 1074: 1069: 1064: 1059: 1054: 1044: 1039: 1034: 1029: 1023: 1018: 1017: 1014: 1013: 1010: 1009: 1004: 999: 993: 987: 986: 983: 982: 979: 978: 973: 968: 962: 957: 947: 942: 936: 931: 930: 927: 926: 923: 922: 917: 916: 915: 910: 905: 900: 895: 890: 885: 880: 878:MultiMediaCard 875: 870: 865: 855: 854: 853: 848: 843: 838: 832: 826: 814: 809: 808: 807: 802: 792: 787: 781: 776: 775: 772: 771: 765: 764: 761: 760: 754: 748: 743: 740:Selectron tube 737: 731: 725: 718: 715: 714: 711: 710: 707: 706: 705: 704: 694: 689: 684: 678: 673: 668: 667: 666: 656: 655: 654: 649: 644: 639: 634: 629: 624: 619: 614: 609: 604: 594: 593: 592: 587: 580:Hardware cache 576: 571: 570: 567: 566: 560: 559: 556: 555: 550: 545: 540: 535: 533:Edge computing 530: 525: 520: 515: 513:Grid computing 510: 508:Bank switching 505: 500: 495: 490: 485: 480: 475: 470: 465: 460: 455: 453:Virtual memory 450: 445: 440: 435: 430: 425: 420: 418:Disk mirroring 415: 410: 405: 400: 395: 390: 385: 380: 375: 373:Temporary file 370: 365: 360: 355: 350: 345: 340: 335: 330: 325: 323:Knowledge base 320: 315: 313:Storage record 310: 308:Memory refresh 305: 300: 295: 293:Data structure 290: 285: 280: 275: 270: 265: 260: 255: 250: 245: 240: 235: 230: 225: 220: 215: 210: 205: 200: 195: 190: 188:Data integrity 185: 180: 178:Data cleansing 175: 170: 165: 160: 155: 150: 145: 140: 135: 134: 133: 128: 118: 113: 111:Object storage 108: 103: 98: 93: 92: 91: 81: 76: 71: 66: 61: 56: 51: 45: 42: 41: 38: 37: 15: 9: 6: 4: 3: 2: 8342: 8331: 8328: 8326: 8323: 8322: 8320: 8305: 8302: 8300: 8297: 8295: 8292: 8290: 8289:DRAM timeline 8287: 8286: 8284: 8280: 8274: 8271: 8269: 8266: 8264: 8261: 8259: 8256: 8255: 8253: 8251: 8247: 8241: 8238: 8236: 8233: 8231: 8228: 8227: 8225: 8223: 8219: 8211: 8208: 8206: 8203: 8201: 8198: 8196: 8193: 8191: 8188: 8186: 8183: 8181: 8178: 8177: 8176: 8173: 8171: 8168: 8166: 8163: 8161: 8158: 8157: 8155: 8151: 8145: 8142: 8138: 8135: 8133: 8130: 8128: 8125: 8123: 8120: 8118: 8115: 8114: 8113: 8110: 8108: 8105: 8103: 8100: 8097: 8094: 8091: 8088: 8084: 8081: 8079: 8076: 8074: 8071: 8069: 8066: 8065: 8064: 8061: 8059: 8056: 8055: 8053: 8051: 8047: 8041: 8038: 8036: 8033: 8032: 8030: 8026: 8021: 8014: 8009: 8007: 8002: 8000: 7995: 7994: 7991: 7985: 7982: 7980: 7977: 7975: 7972: 7969: 7966: 7964: 7960: 7957: 7956: 7935: 7931: 7925: 7910:. Tech Report 7909: 7902: 7886: 7882: 7876: 7861: 7857: 7856: 7851: 7845: 7830: 7829: 7824: 7817: 7815: 7799: 7798: 7793: 7786: 7767: 7763: 7756: 7750: 7734: 7730: 7729: 7724: 7718: 7702: 7698: 7692: 7676: 7672: 7671: 7666: 7660: 7658: 7641: 7637: 7636: 7631: 7625: 7609: 7605: 7598: 7582: 7578: 7577: 7570: 7551: 7547: 7546: 7538: 7532: 7516: 7512: 7511: 7506: 7500: 7484: 7480: 7474: 7459: 7455: 7454: 7449: 7443: 7427: 7423: 7417: 7402: 7398: 7397: 7392: 7386: 7377: 7369: 7365: 7361: 7355: 7339: 7335: 7334: 7329: 7323: 7315: 7309: 7293: 7292: 7287: 7281: 7265: 7261: 7260: 7255: 7249: 7234: 7230: 7224: 7222: 7220: 7218: 7216: 7214: 7212: 7192: 7188: 7181: 7175: 7173: 7157: 7153: 7152: 7147: 7141: 7139: 7122: 7121: 7116: 7110: 7108: 7106: 7089: 7085: 7084: 7079: 7073: 7071: 7069: 7049: 7045: 7038: 7032: 7017: 7013: 7007: 7005: 6989: 6985: 6979: 6977: 6975: 6966: 6965:Imagine Media 6962: 6961: 6953: 6934: 6930: 6923: 6917: 6915: 6899:. August 1992 6898: 6894: 6888: 6873: 6869: 6863: 6861: 6859: 6857: 6855: 6847: 6843: 6840: 6835: 6819: 6815: 6814: 6809: 6803: 6801: 6799: 6783: 6779: 6775: 6774: 6767: 6765: 6749: 6745: 6739: 6723: 6719: 6718: 6711: 6709: 6692: 6688: 6687: 6680: 6678: 6660: 6653: 6652: 6644: 6633: 6626: 6625: 6617: 6604:on 2012-04-26 6600: 6593: 6592: 6584: 6571:on 2012-04-26 6567: 6560: 6559: 6551: 6537: 6536: 6528: 6514: 6510: 6503: 6495: 6491: 6485: 6477: 6473: 6467: 6452: 6446: 6431: 6427: 6420: 6405: 6401: 6394: 6379: 6375: 6369: 6355:on 2009-07-13 6354: 6350: 6344: 6329: 6325: 6319: 6311: 6307: 6301: 6293: 6289: 6283: 6275: 6271: 6265: 6259: 6254: 6246: 6239: 6231: 6224: 6216: 6210: 6202: 6198: 6191: 6183: 6177: 6168: 6162: 6147: 6143: 6136: 6134: 6132: 6122: 6107: 6100: 6094: 6087: 6084:refer to the 6083: 6079: 6075: 6071: 6065: 6063: 6061: 6059: 6057: 6055: 6053: 6051: 6049: 6041: 6037: 6033: 6032: 6027: 6021: 6019: 6010: 6006: 6002: 5998: 5994: 5990: 5982: 5974: 5972:9780080553849 5968: 5964: 5963: 5955: 5947: 5945:9780080553849 5941: 5937: 5936: 5928: 5920: 5918:9781786305633 5914: 5910: 5909: 5901: 5897: 5886: 5882: 5879: 5876: 5873: 5870: 5868: 5865: 5863: 5859: 5855: 5851: 5847: 5843: 5839: 5836: 5835: 5825: 5822: 5820: 5817: 5815: 5812: 5809: 5806: 5802: 5799: 5796: 5791: 5790: 5787: 5785: 5784: 5780: 5777: 5774: 5771: 5768: 5765: 5763: 5762: 5758: 5755: 5754: 5751: 5749: 5748: 5744: 5741: 5739: 5736: 5733: 5731: 5728: 5725: 5723: 5722: 5718: 5713: 5712: 5709: 5706: 5703: 5700: 5698: 5695: 5692: 5688: 5685: 5682: 5677: 5676: 5673: 5670: 5668: 5667: 5663: 5661: 5660: 5656: 5653: 5652: 5647: 5646: 5637: 5636: 5630: 5624: 5621: 5619: 5618: 5614: 5611: 5610: 5607: 5604: 5601: 5599: 5598: 5594: 5591: 5588: 5585: 5582: 5579: 5578: 5575: 5572: 5569: 5566: 5563: 5561: 5560: 5556: 5553: 5552: 5549: 5546: 5543: 5540: 5536: 5533: 5531: 5530: 5526: 5523: 5522: 5517: 5516: 5507: 5506: 5502: 5500: 5497: 5494: 5491: 5489: 5488: 5484: 5481: 5480: 5477: 5475: 5474: 5470: 5467: 5465: 5464: 5460: 5457: 5454: 5450: 5447: 5445: 5444: 5440: 5435: 5434: 5431: 5428: 5425: 5423: 5422: 5418: 5415: 5413:SGRAM (GDDR) 5412: 5409: 5406: 5401: 5400: 5396: 5392: 5391: 5386: 5385: 5376: 5375: 5365: 5360: 5359: 5351: 5348: 5346: 5345: 5341: 5338: 5336: 5335: 5331: 5328: 5325: 5321: 5318: 5316: 5315: 5311: 5308: 5307: 5304: 5301: 5298: 5296: 5295: 5291: 5288: 5285: 5282: 5279: 5276: 5275: 5272: 5270: 5269: 5265: 5262: 5260: 5259: 5255: 5253: 5250: 5247: 5243: 5240: 5238: 5237: 5233: 5228: 5227: 5224: 5221: 5218: 5215: 5212: 5209: 5206: 5203: 5200: 5199: 5196: 5193: 5190: 5188: 5187: 5183: 5181: 5178: 5175: 5172: 5169: 5166:December 1994 5164: 5163: 5160: 5157: 5155: 5152: 5150: 5147: 5145: 5142: 5139: 5135: 5132: 5129: 5126: 5123:November 1994 5121: 5120: 5114: 5109: 5106: 5104: 5098: 5095: 5092: 5088: 5085: 5082: 5081: 5077: 5073: 5066:SGRAM and HBM 5059: 5057: 5056: 5052: 5049: 5046: 5043: 5040: 5037: 5036: 5033: 5031: 5030: 5026: 5024: 5021: 5019: 5016: 5013: 5011: 5008: 5005: 5003: 5002: 4994: 4991: 4989: 4988: 4984: 4981: 4978: 4975: 4972: 4969: 4967: 4966: 4962: 4959: 4958: 4955: 4953: 4952: 4948: 4945: 4942: 4939: 4936: 4933: 4931: 4930: 4926: 4923: 4922: 4919: 4917: 4916: 4912: 4909: 4907: 4904: 4901: 4899: 4896: 4894: 4893: 4889: 4887: 4886: 4882: 4879: 4878: 4875: 4873: 4872: 4868: 4865: 4863: 4860: 4857: 4855: 4852: 4849: 4848: 4845: 4843: 4842: 4838: 4835: 4832: 4829: 4826: 4823: 4821: 4820: 4812: 4809: 4806: 4803: 4800: 4797: 4796: 4791: 4790: 4781: 4778: 4775: 4772: 4770: 4769: 4765: 4763: 4762: 4754: 4751: 4750: 4746: 4743: 4740: 4737: 4734: 4731: 4729: 4728: 4724: 4721: 4720: 4715: 4714: 4710: 4707: 4704: 4701: 4698: 4695: 4693: 4692: 4688: 4683: 4682: 4679: 4678: 4674: 4671: 4669: 4666: 4664: 4663: 4659: 4657: 4656: 4652: 4649: 4648: 4643: 4642: 4632: 4629: 4626: 4623: 4621: 4620: 4616: 4613: 4612: 4609: 4607: 4606: 4602: 4599: 4596: 4593: 4590: 4587: 4585: 4584: 4580: 4579: 4576: 4574: 4573: 4569: 4566: 4563: 4560: 4557: 4554: 4552: 4549: 4548: 4545: 4542: 4539: 4537: 4534: 4531: 4528: 4525: 4523: 4520: 4516: 4513: 4511: 4510: 4506: 4503: 4500: 4497: 4494: 4491: 4489: 4488: 4484: 4481: 4480: 4477: 4475: 4474: 4470: 4467: 4465: 4464: 4460: 4457: 4454: 4451: 4450: 4447: 4445: 4444: 4440: 4437: 4435: 4432: 4430: 4427: 4426: 4423: 4421: 4420: 4416: 4413: 4411: 4410: 4406: 4403: 4396: 4393: 4391: 4390: 4386: 4383: 4380: 4377: 4375: 4372: 4369: 4367: 4366: 4361: 4358: 4355: 4352: 4350: 4347: 4344: 4341: 4338: 4336: 4333: 4329: 4326: 4324: 4323: 4319: 4316: 4314: 4313: 4309: 4306: 4303: 4300: 4298: 4297: 4293: 4290: 4289: 4286: 4284: 4283: 4279: 4276: 4274: 4271: 4268: 4266: 4263: 4261: 4260: 4256: 4255: 4252: 4250: 4249: 4245: 4242: 4240: 4239: 4235: 4232: 4229: 4226: 4224: 4223: 4215: 4212: 4209: 4206: 4204: 4201: 4199: 4195: 4192: 4190: 4187: 4184: 4182: 4179: 4176: 4175: 4172: 4170: 4169: 4165: 4162: 4160: 4157: 4154: 4151: 4148: 4147: 4144: 4142: 4141: 4137: 4134: 4132: 4131: 4127: 4124: 4121: 4118: 4116: 4115: 4107: 4104: 4102: 4101: 4097: 4094: 4092: 4091: 4087: 4084: 4081: 4078: 4077: 4074: 4072: 4071: 4067: 4064: 4062: 4061: 4057: 4054: 4051: 4048: 4046: 4045: 4037: 4034: 4032: 4031: 4027: 4024: 4022: 4021: 4017: 4014: 4012: 4009: 4006: 4004: 4003: 3999: 3994: 3993: 3990: 3988: 3987: 3983: 3980: 3978: 3977: 3973: 3971: 3968: 3965: 3962: 3960:Direct RDRAM 3959: 3954: 3953: 3950: 3947: 3944: 3942: 3941: 3937: 3934: 3931: 3928: 3925: 3922: 3921: 3918: 3916: 3915: 3911: 3909: 3906: 3904: 3903: 3899: 3897: 3894: 3891: 3888: 3886: 3885: 3881: 3878: 3877: 3874: 3872: 3871: 3867: 3864: 3862: 3859: 3857: 3854: 3851: 3848: 3846: 3845: 3841: 3840: 3837: 3835: 3834: 3830: 3827: 3825: 3824: 3820: 3818: 3815: 3812: 3809: 3807: 3804: 3803: 3800: 3797: 3794: 3792: 3791: 3787: 3785: 3782: 3780: 3777: 3774: 3771: 3767: 3764: 3762: 3761: 3757: 3755: 3752: 3750: 3749: 3745: 3743: 3740: 3738: 3735: 3733: 3729: 3726: 3723: 3722: 3716: 3711: 3708: 3706: 3700: 3697: 3694: 3690: 3687: 3684: 3683: 3666: 3663:December 2023 3654: 3649: 3640: 3639: 3635: 3631: 3627: 3617: 3615: 3611: 3607: 3603: 3599: 3594: 3584: 3582: 3578: 3570: 3568: 3564: 3560: 3556: 3552: 3548: 3544: 3540: 3536: 3532: 3528: 3524: 3518: 3508: 3506: 3502: 3498: 3494: 3490: 3486: 3477: 3475: 3471: 3467: 3463: 3459: 3455: 3451: 3441: 3437: 3434: 3430: 3426: 3422: 3418: 3416: 3412: 3408: 3403: 3399: 3389: 3386: 3382: 3380: 3376: 3368: 3365: 3362: 3359: 3356: 3353: 3352: 3351: 3348: 3341: 3338: 3335: 3332: 3329: 3326: 3325: 3307: 3306: 3296: 3295: 3279: 3278: 3262: 3261: 3257: 3254: 3251: 3248: 3245: 3242: 3239: 3236: 3233: 3230: 3227: 3226: 3220: 3217: 3213: 3211: 3207: 3202: 3201:open standard 3191: 3188: 3179: 3171: 3166: 3156: 3154: 3150: 3146: 3142: 3137: 3135: 3131: 3126: 3124: 3120: 3115: 3112: 3108: 3102: 3092: 3088: 3086: 3082: 3077: 3072: 3062: 3059: 3055: 3050: 3040: 3036: 3034: 3029: 3026: 3019: 3009: 3007: 3002: 2998: 2994: 2990: 2986: 2977: 2973: 2971: 2967: 2964: 2960: 2956: 2952: 2948: 2940: 2934: 2924: 2922: 2918: 2917:Intel Celeron 2914: 2913:PowerBook G3s 2910: 2906: 2902: 2898: 2897:Intel Pentium 2893: 2891: 2887: 2883: 2879: 2875: 2866: 2864: 2860: 2855: 2851: 2847: 2845: 2841: 2837: 2829: 2825: 2822: 2817: 2796: 2794: 2790: 2784: 2778: 2776: 2772: 2768: 2751: 2749: 2745: 2738: 2734: 2728: 2719: 2717: 2714: 2711: 2710: 2708: 2706: 2702: 2696: 2692: 2683: 2682: 2680: 2676: 2668: 2654: 2651: 2648: 2645: 2642: 2639: 2636: 2633: 2630: 2627: 2626: 2625: 2622: 2620: 2615: 2611: 2607: 2603: 2601: 2597: 2593: 2590: 2585: 2580: 2578: 2568: 2566: 2560: 2556: 2548: 2545: 2536: 2523: 2515: 2512: 2508: 2505: 2502: 2501: 2500: 2497: 2491:Mode register 2488: 2484: 2482: 2477: 2473: 2468: 2464: 2462: 2458: 2454: 2444: 2441: 2437: 2433: 2429: 2426: 2417: 2414: 2389: 2386: 2377: 2369: 2366: 2361: 2358: 2353: 2351: 2347: 2342: 2340: 2336: 2332: 2324: 2320: 2315: 2313: 2308: 2303: 2300: 2290: 2270: 2267: 2264: 2261: 2258: 2255: 2252: 2249: 2248: 2247: 2231: 2218: 2192: 2166: 2153: 2140: 2130: 2117: 2110: 2104: 2091: 2084: 2078: 2065: 2058: 2052: 2039: 2032: 2026: 2013: 1987: 1984:No operation 1961: 1935: 1931: 1929: 1925: 1922: 1920: 1916: 1911: 1906: 1901: 1896: 1895: 1892: 1884: 1876: 1856: 1851: 1840: 1835: 1824: 1820: 1815: 1814: 1804: 1800: 1797: 1794: 1789: 1785: 1782: 1781: 1780: 1778: 1768: 1764: 1760: 1758: 1753: 1737: 1733: 1717: 1715: 1711: 1707: 1703: 1698: 1696: 1692: 1688: 1683: 1681: 1677: 1673: 1669: 1665: 1660: 1658: 1654: 1649: 1647: 1643: 1639: 1635: 1628: 1624: 1620: 1616: 1612: 1607: 1600: 1596: 1591: 1582: 1579: 1575: 1573: 1569: 1568: 1562: 1558: 1554: 1550: 1546: 1541: 1539: 1535: 1531: 1527: 1523: 1515: 1504: 1499: 1497: 1492: 1490: 1485: 1484: 1482: 1481: 1473: 1470: 1467: 1466:Bubble memory 1464: 1461: 1458: 1455: 1452: 1449: 1446: 1443: 1440: 1437: 1434: 1431: 1428: 1425: 1422: 1420: 1417: 1414: 1411: 1408: 1405: 1402: 1399: 1398: 1392: 1391: 1384: 1381: 1379: 1376: 1374: 1371: 1369: 1366: 1364: 1361: 1359: 1356: 1352: 1349: 1348: 1347: 1344: 1342: 1339: 1337: 1334: 1332: 1329: 1327: 1324: 1322: 1319: 1317: 1314: 1313: 1307: 1306: 1299: 1296: 1292: 1289: 1287: 1284: 1282: 1279: 1277: 1274: 1272: 1269: 1267: 1264: 1262: 1259: 1257: 1254: 1252: 1249: 1247: 1244: 1242: 1239: 1237: 1234: 1232: 1229: 1227: 1224: 1222: 1219: 1217: 1214: 1212: 1209: 1207: 1204: 1202: 1199: 1197: 1194: 1191: 1188: 1186: 1183: 1181: 1178: 1177: 1176: 1173: 1172: 1169: 1164: 1163: 1156: 1153: 1149: 1146: 1144: 1141: 1139: 1136: 1134: 1131: 1129: 1126: 1124: 1121: 1119: 1116: 1114: 1111: 1109: 1106: 1104: 1101: 1099: 1096: 1094: 1093:Cassette tape 1091: 1089: 1088:Videocassette 1086: 1084: 1081: 1078: 1075: 1073: 1070: 1068: 1065: 1063: 1060: 1058: 1057:Magnetic tape 1055: 1053: 1050: 1049: 1048: 1045: 1043: 1040: 1038: 1035: 1033: 1030: 1028: 1025: 1024: 1021: 1016: 1015: 1008: 1005: 1003: 1000: 998: 995: 994: 991: 985: 984: 977: 974: 972: 969: 966: 963: 961: 958: 955: 951: 948: 946: 943: 941: 938: 937: 934: 929: 928: 921: 918: 914: 911: 909: 906: 904: 901: 899: 896: 894: 891: 889: 886: 884: 881: 879: 876: 874: 871: 869: 866: 864: 861: 860: 859: 856: 852: 849: 847: 844: 842: 839: 836: 833: 830: 827: 824: 821: 820: 818: 815: 813: 812:ROM cartridge 810: 806: 803: 801: 798: 797: 796: 793: 791: 788: 786: 783: 782: 779: 774: 773: 770: 767: 766: 758: 755: 752: 749: 747: 744: 741: 738: 735: 732: 729: 726: 723: 720: 719: 713: 712: 703: 700: 699: 698: 695: 693: 690: 688: 685: 682: 679: 677: 674: 672: 669: 665: 662: 661: 660: 657: 653: 650: 648: 645: 643: 640: 638: 635: 633: 630: 628: 625: 623: 620: 618: 615: 613: 610: 608: 605: 603: 600: 599: 598: 595: 591: 588: 586: 583: 582: 581: 578: 577: 574: 569: 568: 565: 562: 561: 554: 551: 549: 546: 544: 541: 539: 538:Dew computing 536: 534: 531: 529: 528:Fog computing 526: 524: 523:Cloud storage 521: 519: 516: 514: 511: 509: 506: 504: 503:Memory paging 501: 499: 496: 494: 491: 489: 486: 484: 481: 479: 476: 474: 471: 469: 466: 464: 461: 459: 456: 454: 451: 449: 446: 444: 441: 439: 436: 434: 431: 429: 426: 424: 421: 419: 416: 414: 411: 409: 406: 404: 401: 399: 396: 394: 391: 389: 386: 384: 381: 379: 376: 374: 371: 369: 366: 364: 361: 359: 356: 354: 351: 349: 346: 344: 341: 339: 338:File deletion 336: 334: 331: 329: 328:Computer file 326: 324: 321: 319: 316: 314: 311: 309: 306: 304: 301: 299: 296: 294: 291: 289: 286: 284: 281: 279: 276: 274: 271: 269: 266: 264: 261: 259: 256: 254: 251: 249: 246: 244: 241: 239: 236: 234: 231: 229: 226: 224: 221: 219: 216: 214: 211: 209: 208:Data recovery 206: 204: 201: 199: 196: 194: 193:Data security 191: 189: 186: 184: 181: 179: 176: 174: 171: 169: 166: 164: 161: 159: 156: 154: 151: 149: 146: 144: 141: 139: 136: 132: 129: 127: 124: 123: 122: 119: 117: 114: 112: 109: 107: 104: 102: 99: 97: 94: 90: 89:floating-gate 87: 86: 85: 82: 80: 77: 75: 72: 70: 67: 65: 62: 60: 57: 55: 52: 50: 47: 46: 40: 39: 35: 31: 28: 27: 22: 8092:(Mobile DDR) 8057: 8049: 8028:Asynchronous 7938:. Retrieved 7933: 7924: 7912:. Retrieved 7901: 7889:. Retrieved 7875: 7863:. Retrieved 7853: 7844: 7832:. Retrieved 7826: 7801:. Retrieved 7795: 7785: 7773:. Retrieved 7749: 7737:. Retrieved 7726: 7717: 7705:. Retrieved 7703:. March 2005 7691: 7679:. Retrieved 7668: 7644:. Retrieved 7633: 7624: 7612:. Retrieved 7607: 7597: 7585:. Retrieved 7575: 7569: 7557:. Retrieved 7543: 7531: 7519:. Retrieved 7515:the original 7508: 7499: 7487:. Retrieved 7473: 7461:. Retrieved 7451: 7442: 7430:. Retrieved 7425: 7416: 7404:. Retrieved 7394: 7385: 7376: 7363: 7354: 7342:. Retrieved 7331: 7322: 7296:. Retrieved 7291:The Inquirer 7289: 7280: 7268:. Retrieved 7257: 7248: 7236:. Retrieved 7232: 7198:. Retrieved 7159:. Retrieved 7149: 7125:. Retrieved 7118: 7092:. Retrieved 7081: 7055:. Retrieved 7031: 7019:. Retrieved 7015: 6991:. Retrieved 6987: 6958: 6952: 6940:. Retrieved 6901:. Retrieved 6887: 6875:. Retrieved 6871: 6834: 6822:. Retrieved 6811: 6785:. Retrieved 6772: 6751:. Retrieved 6747: 6738: 6726:. Retrieved 6716: 6695:. Retrieved 6685: 6666:, retrieved 6650: 6648:NEC (1999), 6643: 6623: 6616: 6606:, retrieved 6599:the original 6590: 6583: 6573:, retrieved 6566:the original 6557: 6550: 6540:, retrieved 6534: 6527: 6516:. Retrieved 6512: 6502: 6484: 6475: 6466: 6455:. Retrieved 6445: 6434:. Retrieved 6430:the original 6419: 6408:. Retrieved 6404:the original 6393: 6382:. Retrieved 6380:. 2011-08-22 6368: 6357:. Retrieved 6353:the original 6343: 6332:. Retrieved 6328:the original 6318: 6310:heise online 6309: 6300: 6291: 6282: 6273: 6264: 6253: 6238: 6232:. Anandtech. 6223: 6209: 6200: 6190: 6176: 6161: 6150:. Retrieved 6145: 6121: 6110:. Retrieved 6108:. April 2003 6105: 6093: 6081: 6077: 6073: 6069: 6039: 6035: 6029: 5992: 5988: 5981: 5961: 5954: 5934: 5927: 5907: 5900: 5823:225 mm 5793:January 2018 5782: 5781: 5760: 5759: 5746: 5745: 5720: 5719: 5707:140 mm 5665: 5664: 5658: 5657: 5644: 5643: 5634: 5633: 5616: 5615: 5605:100 mm 5596: 5595: 5558: 5557: 5528: 5527: 5514: 5513: 5504: 5503: 5486: 5485: 5472: 5471: 5462: 5461: 5442: 5441: 5437:October 2005 5420: 5419: 5383: 5382: 5373: 5372: 5357: 5356: 5343: 5342: 5333: 5332: 5313: 5312: 5302:280 mm 5293: 5292: 5286:SGRAM (SDR) 5267: 5266: 5257: 5256: 5235: 5234: 5222:280 mm 5216:350 nm 5210:SGRAM (SDR) 5194:280 mm 5185: 5184: 5176:SGRAM (SDR) 5074:(SGRAM) and 5054: 5053: 5028: 5027: 5000: 4999: 4986: 4985: 4964: 4963: 4950: 4949: 4928: 4927: 4914: 4913: 4891: 4890: 4884: 4883: 4870: 4869: 4840: 4839: 4818: 4817: 4788: 4787: 4767: 4766: 4760: 4759: 4748: 4747: 4726: 4725: 4712: 4711: 4690: 4689: 4676: 4675: 4661: 4660: 4654: 4653: 4640: 4639: 4618: 4617: 4604: 4603: 4582: 4581: 4571: 4570: 4508: 4507: 4486: 4485: 4472: 4471: 4462: 4461: 4442: 4441: 4418: 4417: 4408: 4407: 4388: 4387: 4364: 4363: 4321: 4320: 4311: 4310: 4295: 4294: 4281: 4280: 4258: 4257: 4247: 4246: 4237: 4236: 4221: 4220: 4210:279 mm 4167: 4166: 4139: 4138: 4129: 4128: 4113: 4112: 4099: 4098: 4089: 4088: 4069: 4068: 4059: 4058: 4043: 4042: 4029: 4028: 4019: 4018: 4001: 4000: 3985: 3984: 3975: 3974: 3948:325 mm 3939: 3938: 3913: 3912: 3901: 3900: 3883: 3882: 3869: 3868: 3843: 3842: 3832: 3831: 3822: 3821: 3798:325 mm 3789: 3788: 3759: 3758: 3747: 3746: 3660: 3652: 3596: 3571: 3520: 3478: 3454:framebuffers 3447: 3438: 3435: 3431: 3427: 3423: 3419: 3395: 3387: 3383: 3372: 3349: 3345: 3283:Command code 3218: 3214: 3197: 3185: 3177: 3168: 3138: 3133: 3129: 3127: 3116: 3104: 3089: 3078: 3074: 3060: 3056: 3052: 3037: 3032: 3030: 3021: 2999:and 144-pin 2984: 2983: 2974: 2966:form factors 2961:and 144-pin 2946: 2945: 2905:Power Mac G3 2894: 2888:and 144-pin 2873: 2872: 2856: 2852: 2848: 2835: 2833: 2730:2.5 - 7.5 ns 2623: 2616: 2612: 2608: 2604: 2581: 2574: 2561: 2557: 2549: 2546: 2542: 2529: 2526:Auto refresh 2520: 2498: 2494: 2485: 2476:exclusive or 2469: 2465: 2450: 2442: 2438: 2434: 2430: 2427: 2423: 2415: 2395: 2384: 2378: 2370: 2364: 2362: 2356: 2354: 2349: 2345: 2343: 2338: 2334: 2330: 2322: 2318: 2316: 2306: 2304: 2298: 2295: 2245: 1927: 1918: 1890: 1882: 1873: 1852: 1836: 1822: 1816: 1802: 1798: 1790: 1783: 1774: 1765: 1761: 1754: 1723: 1699: 1695:workstations 1684: 1661: 1650: 1608: 1604: 1576: 1565: 1552: 1549:asynchronous 1548: 1542: 1538:clock signal 1529: 1525: 1521: 1520: 1413:Punched tape 1407:Punched card 1373:Time crystal 1241:Hyper CD-ROM 1180:Optical disc 1072:Tape library 1007:FeFET memory 988:Early-stage 868:CompactFlash 863:Memory Stick 823:Flash memory 785:Diode matrix 769:Non-volatile 606: 553:Kryder's law 543:Amdahl's law 468:Software rot 443:Logical disk 343:File copying 278:Data storage 233:File sharing 218:Data cluster 34:data storage 8050:Synchronous 5995:(5): 1118. 5797:K4ZAF325BM 5775:20 nm 5701:20 nm 5583:K4W1G1646G 5429:77 mm 5407:K4D553238F 5280:KM4132G112 5204:μPD4811650 5158:58 mm 5096:SDRAM type 5047:10 nm 4979:20 nm 4943:20 nm 4833:40 nm 4824:16384 Mbit 4741:50 nm 4732:16384 Mbit 4705:50 nm 4633:60 nm 4597:80 nm 4564:90 nm 4551:Xenos eDRAM 4543:86 mm 4522:EE+GS eDRAM 4501:80 nm 4381:90 nm 4356:86 mm 4335:EE+GS eDRAM 3861:150 nm 3772:MSM5718C50 3727:KM48SL2000 3698:SDRAM type 3604:SDRAM from 3497:PlayStation 3462:bit masking 3458:video cards 3456:, found on 3411:northbridge 3085:CAS latency 2968:. PC100 is 2759:1.25 - 5 ns 2660:Generations 2457:cache lines 1757:CAS latency 1621:released a 1572:interleaved 1553:synchronous 1472:Floppy disk 1424:Drum memory 858:Memory card 825:is used in: 759:(2002–2010) 724:(1946–1947) 548:Moore's law 393:Boot sector 333:Object file 238:File system 49:Memory cell 8319:Categories 7914:18 January 6668:2012-07-17 6608:2011-12-27 6575:2011-12-27 6542:2011-01-01 6518:2020-07-15 6457:2011-03-13 6436:2009-06-17 6410:2009-06-16 6384:2011-01-06 6359:2009-06-16 6334:2011-01-03 6152:2021-04-13 6112:2015-08-02 5892:References 5738:20 nm 5679:March 2016 5622:4096 Mbit 5586:1024 Mbit 5574:40 nm 5564:2048 Mbit 5548:60 nm 5534:1024 Mbit 5403:March 2005 5170:μPD481850 5127:HM5283206 5089:Capacity ( 5086:Chip name 5006:8192 Mbit 4934:8192 Mbit 4862:30 nm 4850:2048 Mbit 4798:2048 Mbit 4696:8192 Mbit 4685:April 2008 4624:1024 Mbit 4492:2048 Mbit 4452:1024 Mbit 4149:1024 Mbit 3956:March 1998 3926:MD5764802 3889:1024 Mbit 3856:Mitsubishi 3849:1024 Mbit 3691:Capacity ( 3688:Chip name 3624:See also: 3602:3D-stacked 3527:GDDR SDRAM 3517:GDDR SDRAM 3379:ECC memory 3165:DDR5 SDRAM 3107:DDR3 SDRAM 3101:DDR4 SDRAM 3071:DDR3 SDRAM 3049:DDR2 SDRAM 2933:NEC PC-100 2824:sound card 2653:DDR5 SDRAM 2647:DDR4 SDRAM 2641:DDR3 SDRAM 2635:DDR2 SDRAM 2577:data words 2565:Mobile DDR 2472:burst mode 2312:refreshing 1777:active low 1687:registered 1680:DDR3 SDRAM 1629:, chip (64 1578:Pipelining 1395:Historical 1067:Tape drive 893:SmartMedia 716:Historical 413:Disk image 408:Disk array 283:Data store 84:MOS memory 74:Memory map 21:NEC PC-100 8299:Bandwidth 8240:XDR2 DRAM 8063:DDR SDRAM 7963:AnandTech 7828:AnandTech 7797:AnandTech 7426:SlashGear 7308:cite news 7146:"History" 6513:AnandTech 6106:intel.com 5715:June 2016 5492:512 Mbit 5448:256 Mbit 5410:256 Mbit 5363:256 Mbit 5319:128 Mbit 5038:128 Gbit 4588:512 Mbit 4398:512 Mbit 4301:256 Mbit 4227:288 Mbit 4119:128 Mbit 4079:128 Mbit 3996:June 1998 3806:N64 RDRAM 3583:in 1998. 3531:DDR SDRAM 3521:Graphics 3505:SCPH-5000 3474:dual-port 3269:Device ID 3206:DDR SDRAM 3128:DDR4 did 3018:DDR SDRAM 2993:SDR SDRAM 2761:per cycle 2732:per cycle 2629:DDR SDRAM 1657:bandwidth 1627:DDR SDRAM 1532:) is any 1454:Disk pack 1419:Plugboard 1256:DVD-Video 1185:LaserDisc 1083:Videotape 954:3D XPoint 945:Memristor 585:CPU cache 353:Core dump 273:Data bank 223:Directory 8235:XDR DRAM 8153:Graphics 8040:EDO DRAM 8035:FPM DRAM 7934:Wccftech 7766:Archived 7550:Archived 7368:Archived 7191:Archived 7120:Phys.org 7048:Archived 6984:"Memory" 6933:Archived 6842:Archived 6659:archived 6632:archived 6476:TechSpot 5832:See also 5810:Samsung 5800:16 Gbit 5772:Samsung 5766:64 Gbit 5734:Samsung 5726:32 Gbit 5629:SK Hynix 5592:Samsung 5458:Samsung 5416:Samsung 5369:Samsung 5329:Samsung 5289:Samsung 5283:32 Mbit 5241:16 Mbit 5207:16 Mbit 5044:Samsung 5014:Samsung 4976:Samsung 4970:12 Gbit 4940:Samsung 4902:Samsung 4738:Samsung 4702:Samsung 4594:Samsung 4555:80 Mbit 4526:32 Mbit 4498:Samsung 4378:Samsung 4370:72 Mbit 4339:32 Mbit 4269:Samsung 4185:32 Mbit 4181:GS eDRAM 4155:Samsung 4125:Samsung 4085:Samsung 4055:Hyundai 4049:64 Mbit 4015:Samsung 4007:64 Mbit 3963:72 Mbit 3929:64 Mbit 3810:36 Mbit 3775:18 Mbit 3620:Timeline 3614:SK Hynix 2907:, early 2781:Signal: 2765:Signal: 2735:Signal: 2693:Signal: 1932:Command 1887:Commands 1706:SK Hynix 1642:SK Hynix 1383:UltraRAM 1261:DVD card 1216:Video CD 1201:CD Video 971:Nano-RAM 940:Memistor 913:XQD card 888:SIM card 746:Dekatron 632:XDR DRAM 627:EDO DRAM 564:Volatile 358:Hex dump 268:Database 163:Metadata 158:Big data 8268:UniDIMM 8132:HBM-PIM 8098:(FCRAM) 7940:16 July 7891:15 July 7885:Samsung 7865:16 July 7860:Samsung 7834:29 June 7803:16 July 7775:10 July 7733:Samsung 7707:10 July 7681:26 June 7675:Samsung 7646:10 July 7640:Samsung 7614:10 July 7587:10 July 7559:10 July 7521:4 April 7483:Samsung 7463:25 June 7458:Samsung 7432:25 June 7406:25 June 7401:Samsung 7344:25 June 7338:Samsung 7298:25 June 7270:25 June 7264:Samsung 7238:4 April 7233:az5miao 7200:26 June 7161:19 June 7156:Samsung 7127:23 June 7094:23 June 7088:Samsung 7057:21 June 7021:4 April 7016:az5miao 6993:25 June 6942:21 June 6903:19 June 6897:Samsung 6877:4 April 6872:az5miao 6824:23 June 6818:Samsung 6787:21 June 6753:10 July 6744:"PU-18" 6728:10 July 6697:10 July 6691:Hitachi 5997:Bibcode 5803:SGRAM ( 5689:SGRAM ( 5686:8 Gbit 5537:SGRAM ( 5451:SGRAM ( 5393:SGRAM ( 5322:SGRAM ( 5252:Samsung 5244:SGRAM ( 5173:8 Mbit 5144:Hitachi 5130:8 Mbit 5103:Process 5050:FinFET 4973:LPDDR4 4937:LPDDR4 4198:Toshiba 3896:Hyundai 3742:Samsung 3705:Process 3653:updated 3606:Samsung 3525:SDRAM ( 3485:Hitachi 3320:Column 3145:Samsung 3141:Samsung 3081:latency 3001:SO-DIMM 2963:SO-DIMM 2890:SO-DIMM 2802:≤ 1.2 V 2783:SSTL_15 2769:(1.8V) 2767:SSTL_18 2725:= 2.5 V 2689:= 3.3 V 2584:bitline 2355:When a 1691:servers 1619:Samsung 1601:package 1595:Hyundai 1585:History 1468:(~1970) 1462:(~1968) 1444:(1960s) 1281:Blu-ray 1271:MiniDVD 1266:DVD-RAM 1226:Mini CD 1168:Optical 1128:U-matic 1123:MicroMV 1103:Betamax 967:(ECRAM) 908:MicroP2 883:SD card 873:PC Card 664:1T-SRAM 622:QDRSRAM 213:Storage 43:General 8222:Rambus 8107:RLDRAM 8022:(DRAM) 7739:8 July 7489:8 July 7044:Rambus 6748:PSXDEV 6068:Here, 5969: 5942: 5915: 5819:FinFET 5697:Micron 5691:GDDR5X 5570:Hynix 5544:Hynix 5149:350 nm 5108:MOSFET 5078:(HBM) 5023:FinFET 5010:LPDDR5 4898:LPDDR4 4858:Hynix 4830:Hynix 4804:Hynix 4776:Hynix 4672:Hynix 4668:LPDDR2 4630:Hynix 4558:eDRAM 4529:eDRAM 4458:Hynix 4434:110 nm 4429:Elpida 4404:Hynix 4342:eDRAM 4307:Hynix 4273:100 nm 4233:Hynix 4230:RDRAM 4203:180 nm 4159:140 nm 3970:Rambus 3966:RDRAM 3932:RDRAM 3813:RDRAM 3710:MOSFET 3632:, and 3574: 3567:GDDR6W 3563:GDDR6X 3555:GDDR5X 3481: 3375:caches 3354:CMD5=0 3149:Gbit/s 2909:iBooks 2901:AMD K6 2878:memory 2828:Micron 2785:(1.5V) 2739:(2.5V) 2737:SSTL_2 2678:SDRAM 2461:bursts 2385:active 2331:active 2307:active 2111:column 2085:column 2059:column 2033:column 1720:Timing 1712:, and 1631: 1593:Eight 1474:(1971) 1456:(1962) 1450:(1962) 1438:(1957) 1432:(1949) 1426:(1932) 1415:(1725) 1409:(1725) 1403:(1725) 1276:HD DVD 1236:CD-ROM 1192:(CDDA) 1118:MiniDV 837:(SSHD) 819:(SSS) 805:EEPROM 753:(2009) 742:(1952) 736:(1951) 730:(1947) 348:Backup 8325:SDRAM 8282:Lists 8230:RDRAM 8210:GDDR7 8205:GDDR6 8200:GDDR5 8195:GDDR4 8190:GDDR3 8185:GDDR2 8175:SGRAM 8170:MDRAM 8137:HBM3E 8122:HBM2E 8102:eDRAM 8090:LPDDR 8058:SDRAM 7850:"HBM" 7769:(PDF) 7758:(PDF) 7553:(PDF) 7540:(PDF) 7194:(PDF) 7183:(PDF) 7051:(PDF) 7040:(PDF) 6936:(PDF) 6925:(PDF) 6662:(PDF) 6655:(PDF) 6635:(PDF) 6628:(PDF) 6602:(PDF) 6595:(PDF) 6569:(PDF) 6562:(PDF) 6494:JEDEC 6378:JEDEC 6292:Alphr 6102:(PDF) 6080:, or 5862:GDDR7 5858:GDDR6 5854:GDDR5 5850:GDDR4 5846:GDDR3 5842:GDDR2 5814:10 nm 5805:GDDR6 5778:CMOS 5769:HBM2 5756:2017 5742:CMOS 5704:CMOS 5654:2013 5640:CMOS 5612:2012 5602:CMOS 5580:2010 5554:2009 5539:GDDR5 5524:2007 5510:CMOS 5499:Hynix 5482:2005 5468:CMOS 5453:GDDR4 5426:CMOS 5395:GDDR3 5379:CMOS 5353:2003 5339:CMOS 5324:GDDR2 5309:2002 5299:CMOS 5277:1999 5263:CMOS 5219:CMOS 5201:1997 5191:CMOS 5134:SGRAM 5112:Area 5041:DDR4 5018:10 nm 4996:2018 4982:CMOS 4960:2015 4946:CMOS 4924:2014 4910:CMOS 4906:20 nm 4880:2013 4866:CMOS 4836:CMOS 4827:DDR3 4814:2011 4808:40 nm 4801:DDR3 4784:CMOS 4780:44 nm 4773:DDR3 4756:2009 4744:CMOS 4735:DDR3 4722:2008 4708:CMOS 4699:DDR3 4650:2008 4636:CMOS 4627:DDR2 4614:2006 4600:CMOS 4591:DDR3 4567:CMOS 4540:CMOS 4536:65 nm 4518:2005 4504:CMOS 4495:DDR2 4482:2004 4468:CMOS 4455:DDR2 4438:CMOS 4414:CMOS 4401:DDR2 4384:CMOS 4353:CMOS 4349:90 nm 4331:2003 4317:CMOS 4291:2002 4277:CMOS 4243:CMOS 4217:2001 4207:CMOS 4189:eDRAM 4177:2000 4163:CMOS 4135:CMOS 4109:1999 4095:CMOS 4065:CMOS 4039:1998 4025:CMOS 3981:CMOS 3945:CMOS 3923:1998 3879:1997 3865:CMOS 3828:CMOS 3795:CMOS 3779:RDRAM 3769:1996 3724:1992 3714:Area 3675:SDRAM 3559:GDDR6 3551:GDDR5 3547:GDDR4 3543:GDDR3 3539:GDDR2 3499:(PS) 3402:RDRAM 3275:CMD5 3187:RDRAM 2989:JEDEC 2985:PC133 2980:PC133 2955:JEDEC 2947:PC100 2927:PC100 2882:JEDEC 2840:DIMMs 2836:SDRAM 2695:LVTTL 2670:Type 2481:Intel 2453:cache 2365:write 2350:write 2344:Both 2339:write 2323:write 1664:JEDEC 1640:(now 1567:banks 1557:JEDEC 1543:DRAM 1530:SDRAM 1336:ECRAM 1316:CBRAM 1251:DVD+R 1211:CD-RW 1148:D-VHS 1143:VHS-C 1138:S-VHS 1079:(DDS) 1002:ReRAM 997:FeRAM 990:NVRAM 976:CBRAM 933:NVRAM 831:(SSD) 800:EPROM 757:Z-RAM 751:T-RAM 683:(CAM) 671:ReRAM 637:RDRAM 617:LPDDR 612:SGRAM 607:SDRAM 602:eDRAM 36:types 8273:CAMM 8263:DIMM 8258:SIMM 8180:GDDR 8165:WRAM 8160:VRAM 8127:HBM3 8117:HBM2 8083:DDR5 8078:DDR4 8073:DDR3 8068:DDR2 7942:2019 7916:2018 7893:2019 7867:2019 7836:2019 7805:2019 7777:2019 7741:2019 7709:2019 7683:2019 7648:2019 7616:2019 7610:(48) 7589:2019 7561:2019 7523:2022 7491:2019 7465:2019 7434:2019 7408:2019 7346:2019 7314:link 7300:2019 7272:2019 7240:2022 7202:2019 7187:Sony 7163:2019 7129:2019 7096:2019 7059:2019 7023:2022 6995:2019 6944:2019 6905:2019 6879:2022 6826:2019 6789:2019 6755:2019 6730:2019 6699:2019 5967:ISBN 5940:ISBN 5913:ISBN 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