3216:
a rectangle, a cylinder, or some other more complex shape. There are two basic variations of the stacked capacitor, based on its location relative to the bitline—capacitor-over-bitline (COB) and capacitor-under-bitline (CUB). In a former variation, the capacitor is underneath the bitline, which is usually made of metal, and the bitline has a polysilicon contact that extends downwards to connect it to the access transistor's source terminal. In the latter variation, the capacitor is constructed above the bitline, which is almost always made of polysilicon, but is otherwise identical to the COB variation. The advantage the COB variant possesses is the ease of fabricating the contact between the bitline and the access transistor's source as it is physically close to the substrate surface. However, this requires the active area to be laid out at a 45-degree angle when viewed from above, which makes it difficult to ensure that the capacitor contact does not touch the bitline. CUB cells avoid this, but suffer from difficulties in inserting contacts in between bitlines, since the size of features this close to the surface are at or near the minimum feature size of the process technology (Kenner, pp. 33â42).
3475:, roughly one bit error, per hour, per gigabyte of memory to one bit error, per century, per gigabyte of memory. The Schroeder et al. 2009 study reported a 32% chance that a given computer in their study would suffer from at least one correctable error per year, and provided evidence that most such errors are intermittent hard rather than soft errors and that trace amounts of radioactive material that had gotten into the chip packaging were emitting alpha particles and corrupting the data. A 2010 study at the University of Rochester also gave evidence that a substantial fraction of memory errors are intermittent hard errors. Large scale studies on non-ECC main memory in PCs and laptops suggest that undetected memory errors account for a substantial number of system failures: the 2011 study reported a 1-in-1700 chance per 1.5% of memory tested (extrapolating to an approximately 26% chance for total memory) that a computer would have a memory error every eight months.
3240:, used a three-transistor, one-capacitor (3T1C) DRAM cell. By the second-generation, the requirement to reduce cost by fitting the same amount of bits in a smaller area led to the almost universal adoption of the 1T1C DRAM cell, although a couple of devices with 4 and 16 Kbit capacities continued to use the 3T1C cell for performance reasons (Kenner, p. 6). These performance advantages included, most significantly, the ability to read the state stored by the capacitor without discharging it, avoiding the need to write back what was read out (non-destructive read). A second performance advantage relates to the 3T1C cell has separate transistors for reading and writing; the memory controller can exploit this feature to perform atomic read-modify-writes, where a value is read, modified, and then written back as a single, indivisible operation (Jacob, p. 459).
4590:
4375:
3602:(DIP), soldered directly to the main board or mounted in sockets. As memory density skyrocketed, the DIP package was no longer practical. For convenience in handling, several dynamic RAM integrated circuits may be mounted on a single memory module, allowing installation of 16-bit, 32-bit or 64-bit wide memory in a single unit, without the requirement for the installer to insert multiple individual integrated circuits. Memory modules may include additional devices for parity checking or error correction. Over the evolution of desktop computers, several standardized types of memory module have been developed. Laptop computers, game consoles, and specialized devices may have their own formats of memory modules not interchangeable with standard desktop parts for packaging or proprietary reasons.
3339:
is minute. Sense amplifiers are required to resolve the voltage differential into the levels specified by the logic signaling system. Modern DRAMs use differential sense amplifiers, and are accompanied by requirements as to how the DRAM arrays are constructed. Differential sense amplifiers work by driving their outputs to opposing extremes based on the relative voltages on pairs of bitlines. The sense amplifiers function effectively and efficient only if the capacitance and voltages of these bitline pairs are closely matched. Besides ensuring that the lengths of the bitlines and the number of attached DRAM cells attached to them are equal, two basic architectures to array design have emerged to provide for the requirements of the sense amplifiers: open and folded bitline arrays.
3224:
capacitance (Jacob, pp. 356â357). Alternatively, the capacitance can be increased by etching a deeper hole without any increase to surface area (Kenner, pg. 44). Another advantage of the trench capacitor is that its structure is under the layers of metal interconnect, allowing them to be more easily made planar, which enables it to be integrated in a logic-optimized process technology, which have many levels of interconnect above the substrate. The fact that the capacitor is under the logic means that it is constructed before the transistors are. This allows high-temperature processes to fabricate the capacitors, which would otherwise be degrading the logic transistors and their performance. This makes trench capacitors suitable for constructing
2437:
propagate the amplified data back to recharge the cells. The time to read additional bits from an open page is much less, defined by the /CAS to /CAS cycle time. The quoted number is the clearest way to compare between the performance of different DRAM memories, as it sets the slower limit regardless of the row length or page size. Bigger arrays forcibly result in larger bit line capacitance and longer propagation delays, which cause this time to increase as the sense amplifier settling time is dependent on both the capacitance as well as the propagation latency. This is countered in modern DRAM chips by instead integrating many more complete DRAM arrays within a single chip, to accommodate more capacity without becoming too slow.
4578:
4645:
1988:
advance, effectively halving the number of address lines required, which enabled it to fit into packages with fewer pins, a cost advantage that grew with every jump in memory size. The MK4096 proved to be a very robust design for customer applications. At the 16 Kbit density, the cost advantage increased; the 16 Kbit Mostek MK4116 DRAM, introduced in 1976, achieved greater than 75% worldwide DRAM market share. However, as density increased to 64 Kbit in the early 1980s, Mostek and other US manufacturers were overtaken by
Japanese DRAM manufacturers, which dominated the US and worldwide markets during the 1980s and 1990s.
4050:, saving an additional three clocks over optimally designed EDO memory. It was done by adding an address counter on the chip to keep track of the next address. BEDO also added a pipeline stage allowing page-access cycle to be divided into two parts. During a memory-read operation, the first part accessed the data from the memory array to the output stage (second latch). The second part drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, quicker access time is achieved (up to 50% for large blocks of data) than with traditional EDO.
3298:
2171:
2053:
2081:
1853:
3984:
1637:
3327:. The bitline length is limited by its capacitance (which increases with length), which must be kept within a range for proper sensing (as DRAMs operate by sensing the charge of the capacitor released onto the bitline). Bitline length is also limited by the amount of operating current the DRAM can draw and by how power can be dissipated, since these two characteristics are largely determined by the charging and discharging of the bitline.
3009:. They are the fundamental building block in DRAM arrays. Multiple DRAM memory cell variants exist, but the most commonly used variant in modern DRAMs is the one-transistor, one-capacitor (1T1C) cell. The transistor is used to admit current into the capacitor during writes, and to discharge the capacitor during reads. The access transistor is designed to maximize drive strength and minimize transistor-transistor leakage (Kenner, pg. 34).
4708:
1579:
4509:
39:
3381:
problem worsens, since coupling between adjacent metal wires is inversely proportional to their pitch. The array folding and bitline twisting schemes that are used must increase in complexity in order to maintain sufficient noise reduction. Schemes that have desirable noise immunity characteristics for a minimal impact in area is the topic of current research (Kenner, p. 37).
4035:
immense performance loss associated with a lack of L2 cache in low-cost, commodity PCs. This was also good for notebooks due to difficulties with their limited form factor, and battery life limitations. Additionally, for systems with an L2 cache, the availability of EDO memory improved the average memory latency seen by applications over earlier FPM implementations.
4322:. This is the number of clock cycles allowed for internal operations between a read command and the first data word appearing on the data bus. The "Load mode register" command is used to transfer this value to the SDRAM chip. Other configurable parameters include the length of read and write bursts, i.e. the number of words transferred per read or write command.
2179:
hold a bit-line at stable voltage even after the forcing voltage is removed. During a write to a particular cell, all the columns in a row are sensed simultaneously just as during reading, so although only a single column's storage-cell capacitor charge is changed, the entire row is refreshed (written back in), as illustrated in the figure to the right.
4608:(GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2020, there are seven, successive generations of GDDR:
2224:
refresh requirements of the DRAM. When the row address is supplied by a counter within the DRAM, the system relinquishes control over which row is refreshed and only provides the refresh command. Some modern DRAMs are capable of self-refresh; no external logic is required to instruct the DRAM to refresh or to provide a row address.
2157:
charged to begin with, or by keeping it discharged if it was empty. Note that due to the length of the bit-lines there is a fairly long propagation delay for the charge to be transferred back to the cell's capacitor. This takes significant time past the end of sense amplification, and thus overlaps with one or more column reads.
3220:
by depositing doped polysilicon, which forms the top plate of the capacitor. The top of the capacitor is connected to the access transistor's drain terminal via a polysilicon strap (Kenner, pp. 42â44). A trench capacitor's depth-to-width ratio in DRAMs of the mid-2000s can exceed 50:1 (Jacob, p. 357).
1693:(MOS) technology. While most DRAM memory cell designs use a capacitor and transistor, some only use two transistors. In the designs where a capacitor is used, the capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The
3351:
The DRAM cells that are on the edges of the array do not have adjacent segments. Since the differential sense amplifiers require identical capacitance and bitline lengths from both segments, dummy bitline segments are provided. The advantage of the open bitline array is a smaller array area, although
3186:
capacitors. The drive to increase both density and, to a lesser extent, performance, required denser designs. This was strongly motivated by economics, a major consideration for DRAM devices, especially commodity DRAMs. The minimization of DRAM cell area can produce a denser device and lower the cost
2140:
from the storage cell to the connected bit-line (if the stored value is 1) or from the connected bit-line to the storage cell (if the stored value is 0). Since the capacitance of the bit-line is typically much higher than the capacitance of the storage cell, the voltage on the bit-line increases very
1938:
of data. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his
4663:
Some DRAM components have a "self-refresh mode". While this involves much of the same logic that is needed for pseudo-static operation, this mode is often equivalent to a standby mode. It is provided primarily to allow a system to suspend operation of its DRAM controller to save power without losing
4034:
Single-cycle EDO has the ability to carry out a complete memory transaction in one clock cycle. Otherwise, each sequential RAM access within the same page takes two clock cycles instead of three, once the page has been selected. EDO's performance and capabilities created an opportunity to reduce the
3219:
The trench capacitor is constructed by etching a deep hole into the silicon substrate. The substrate volume surrounding the hole is then heavily doped to produce a buried n plate and to reduce resistance. A layer of oxide-nitride-oxide dielectric is grown or deposited, and finally the hole is filled
3215:
The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate. The capacitor is constructed from an oxide-nitride-oxide (ONO) dielectric sandwiched in between two layers of polysilicon plates (the top plate is shared by all DRAM cells in an IC), and its shape can be
2440:
When such a RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle. For example, when accessed by a 100 MHz state machine (i.e. a 10 ns clock), the 50 ns DRAM can perform the first read in five clock cycles, and additional reads within the same
1987:
MK4096 4 Kbit DRAM designed by Robert
Proebsting and introduced in 1973. This addressing scheme uses the same address pins to receive the low half and the high half of the address of the memory cell being referenced, switching between the two halves on alternating bus cycles. This was a radical
3402:
did not have any redundancy. An integrated circuit with a defective DRAM cell would be discarded. Beginning with the 64 Kbit generation, DRAM arrays have included spare rows and columns to improve yields. Spare rows and columns provide tolerance of minor fabrication defects which have caused a
3389:
Advances in process technology could result in open bitline array architectures being favored if it is able to offer better long-term area efficiencies; since folded array architectures require increasingly complex folding schemes to match any advance in process technology. The relationship between
3338:
are required to read the state contained in the DRAM cells. When the access transistor is activated, the electrical charge in the capacitor is shared with the bitline. The bitline's capacitance is much greater than that of the capacitor (approximately ten times). Thus, the change in bitline voltage
3322:
The horizontal wire, the wordline, is connected to the gate terminal of every access transistor in its row. The vertical bitline is connected to the source terminal of the transistors in its column. The lengths of the wordlines and bitlines are limited. The wordline length is limited by the desired
3223:
Trench capacitors have numerous advantages. Since the capacitor is buried in the bulk of the substrate instead of lying on its surface, the area it occupies can be minimized to what is required to connect it to the access transistor's drain terminal without decreasing the capacitor's size, and thus
2436:
Thus, the generally quoted number is the minimum /RAS low time. This is the time to open a row, allowing the sense amplifiers to settle. Note that the data access for a bit in the row is shorter, since that happens as soon as the sense amplifier has settled, but the DRAM requires additional time to
2178:
To store data, a row is opened and a given column's sense amplifier is temporarily forced to the desired high or low voltage state, thus causing the bit-line to charge or discharge the cell storage capacitor to the desired value. Due to the sense amplifier's positive feedback configuration, it will
4659:
Pseudostatic RAM (PSRAM or PSDRAM) is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM (SRAM). It combines the high density of DRAM with the ease of use of true SRAM. PSRAM is used in the Apple iPhone and other embedded systems such as XFlar
4398:
interface to transfer one half on each clock edge. DDR2 and DDR3 increased this factor to 4Ã and 8Ã, respectively, delivering 4-word and 8-word bursts over 2 and 4 clock cycles, respectively. The internal access rate is mostly unchanged (200 million per second for DDR-400, DDR2-800 and DDR3-1600
3380:
The location where the bitline twists occupies additional area. To minimize area overhead, engineers select the simplest and most area-minimal twisting scheme that is able to reduce noise under the specified limit. As process technology improves to reduce minimum feature sizes, the signal to noise
2092:
The long horizontal lines connecting each row are known as word-lines. Each column of cells is composed of two bit-lines, each connected to every other storage cell in the column (the illustration to the right does not include this important detail). They are generally known as the "+" and "â" bit
1967:
to make a DRAM using a three-transistor cell that they had developed. This became the Intel 1102 in early 1970. However, the 1102 had many problems, prompting Intel to begin work on their own improved design, in secrecy to avoid conflict with
Honeywell. This became the first commercially available
4003:
enabled DRAM, is similar to fast page mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved performance. It is up to 30%
3510:
This property can be used to circumvent security and recover data stored in the main memory that is assumed to be destroyed at power-down. The computer could be quickly rebooted, and the contents of the main memory read out; or by removing a computer's memory modules, cooling them to prolong data
3376:
because it takes its basis from the open array architecture from the perspective of the circuit schematic. The folded array architecture appears to remove DRAM cells in alternate pairs (because two DRAM cells share a single bitline contact) from a column, then move the DRAM cells from an adjacent
3318:
is the smallest feature size of a given process technology. This scheme permits comparison of DRAM size over different process technology generations, as DRAM cell area scales at linear or near-linear rates with respect to feature size. The typical area for modern DRAM cells varies between 6â8 F.
3305:
DRAM cells are laid out in a regular rectangular, grid-like pattern to facilitate their control and access via wordlines and bitlines. The physical layout of the DRAM cells in an array is typically designed so that two adjacent DRAM cells in a column share a single bitline contact to reduce their
3347:
The first generation (1 Kbit) DRAM ICs, up until the 64 Kbit generation (and some 256 Kbit generation devices) had open bitline array architectures. In these architectures, the bitlines are divided into multiple segments, and the differential sense amplifiers are placed in between
2144:
The sense amplifiers are now connected to the bit-lines pairs. Positive feedback then occurs from the cross-connected inverters, thereby amplifying the small voltage difference between the odd and even row bit-lines of a particular column until one bit line is fully at the lowest voltage and the
1880:
incorporated a hard-wired dynamic memory. Paper tape was read and the characters on it "were remembered in a dynamic store. The store used a large bank of capacitors, which were either charged or not, a charged capacitor representing cross (1) and an uncharged capacitor dot (0). Since the charge
2156:
While reading of columns in an open row is occurring, current is flowing back up the bit-lines from the output of the sense amplifiers and recharging the storage cells. This reinforces (i.e. "refreshes") the charge in the storage cell by increasing the voltage in the storage capacitor if it was
2223:
within the DRAM. A system that provides the row address (and the refresh command) does so to have greater control over when to refresh and which row to refresh. This is done to minimize conflicts with memory accesses, since such a system has both knowledge of the memory access patterns and the
4563:(writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike VRAM and WRAM, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other video RAM technologies.
2004:
for the purpose of driving makers in the United States out of the commodity memory chip business. Prices for the 64K product plummeted to as low as 35 cents apiece from $ 3.50 within 18 months, with disastrous financial consequences for some U.S. firms. On 4 December 1985 the US Commerce
3897:
is a minor modification to the first-generation DRAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column. In page mode DRAM, after a row was opened by holding
3256:
In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor. 1T DRAM is a "capacitorless" bit cell design that stores data using the parasitic body capacitance that is inherent to
1774:
The need to refresh DRAM demands more complicated circuitry and timing than SRAM. This is offset by the structural simplicity of DRAM memory cells: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high
4325:
The most significant change, and the primary reason that SDRAM has supplanted asynchronous RAM, is the support for multiple internal banks inside the DRAM chip. Using a few bits of "bank address" which accompany each command, a second bank can be activated and begin reading data
2088:
DRAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit. The figure to the right shows a simple example with a four-by-four cell matrix. Some DRAM matrices are many thousands of cells in height and width.
2121:
The bit-lines are precharged to exactly equal voltages that are in between high and low logic levels (e.g., 0.5 V if the two levels are 0 and 1 V). The bit-lines are physically symmetrical to keep the capacitance equal, and therefore at this time their voltages are
4053:
Although BEDO DRAM showed additional optimization over EDO, by the time it was available the market had made a significant investment towards synchronous DRAM, or SDRAM. Even though BEDO RAM was superior to SDRAM in some ways, the latter technology quickly displaced BEDO.
3368:
noise rejection characteristics over open bitline arrays. The folded bitline array architecture began appearing in DRAM ICs during the mid-1980s, beginning with the 256 Kbit generation. This architecture is favored in modern DRAM ICs for its superior noise immunity.
2141:
slightly if the storage cell's capacitor is discharged and decreases very slightly if the storage cell is charged (e.g., 0.54 and 0.45 V in the two cases). As the other bit-line holds 0.50 V there is a small voltage difference between the two twisted bit-lines.
1782:
DRAM had a 47% increase in the price-per-bit in 2017, the largest jump in 30 years since the 45% jump in 1988, while in recent years the price has been going down. In 2018, a "key characteristic of the DRAM market is that there are currently only three major suppliers â
3252:
is a different way of constructing the basic DRAM memory cell, distinct from the classic one-transistor/one-capacitor (1T/1C) DRAM cell, which is also sometimes referred to as "1T DRAM", particularly in comparison to the 3T and 4T DRAM which it replaced in the 1970s.
3199:
capacitors. In the 2000s, manufacturers were sharply divided by the type of capacitor used in their DRAMs and the relative cost and long-term scalability of both designs have been the subject of extensive debate. The majority of DRAMs, from major manufactures such as
3548:
Dynamic memory, by definition, requires periodic refresh. Furthermore, reading dynamic memory is a destructive operation, requiring a recharge of the storage cells in the row that has been read. If these processes are imperfect, a read operation can cause
1943:
in 1968. MOS memory offered higher performance, was cheaper, and consumed less power, than magnetic-core memory. The patent describes the invention: "Each cell is formed, in one embodiment, using a single field-efiiect transistor and a single capacitor."
2206:
Some systems refresh every row in a burst of activity involving all rows every 64 ms. Other systems refresh one row at a time staggered throughout the 64 ms interval. For example, a system with 2 = 8,192 rows would require a staggered
2148:
All storage cells in the open row are sensed simultaneously, and the sense amplifier outputs latched. A column address then selects which latch bit to connect to the external data bus. Reads of different columns in the same row can be performed without a
4317:
Many timing parameters remain under the control of the DRAM controller. For example, a minimum time must elapse between a row being activated and a read or write command. One important parameter must be programmed into the SDRAM chip itself, namely the
1995:
decided to withdraw Intel from producing DRAM. By 1986, many, but not all, United States chip makers had stopped making DRAMs. Micron
Technology and Texas Instruments continued to produce them commercially, and IBM produced them for internal use.
2160:
When done with reading all the columns in the current open row, the word-line is switched off to disconnect the storage cell capacitors (the row is "closed") from the bit-lines. The sense amplifier is switched off, and the bit-lines are precharged
3228:(eDRAM) (Jacob, p. 357). Disadvantages of trench capacitors are difficulties in reliably constructing the capacitor's structures within deep holes and in connecting the capacitor to the access transistor's drain terminal (Kenner, pg. 44).
1999:
In 1985, when 64K DRAM memory chips were the most common memory chips used in computers, and when more than 60 percent of those chips were produced by
Japanese companies, semiconductor makers in the United States accused Japanese companies of
3348:
bitline segments. Because the sense amplifiers are placed between bitline segments, to route their outputs outside the array, an additional layer of interconnect placed above those used to construct the wordlines and bitlines is required.
2211:
of one row every 7.8 Ξs which is 64 ms divided by 8,192 rows. A few real-time systems refresh a portion of memory at a time determined by an external timer function that governs the operation of the rest of a system, such as the
3004:
Each bit of data in a DRAM is stored as a positive or negative electrical charge in a capacitive structure. The structure providing the capacitance, as well as the transistors that control access to it, is collectively referred to as a
3636:
without preventing the fabrication of fast-switching transistors used in high-performance logic, and modification of the basic logic-optimized process technology to accommodate the process steps required to build DRAM cell structures.
5101:
3166:). The time required to discharge a capacitor thus depends on what logic value is stored in the capacitor. A capacitor containing logic one begins to discharge when the voltage at the access transistor's gate terminal is above V
3356:, which affects the effectiveness of the differential sense amplifiers. Since each bitline segment does not have any spatial relationship to the other, it is likely that noise would affect only one of the two bitline segments.
4539:. MDRAM also allows operations to two banks in a single clock cycle, permitting multiple concurrent accesses to occur if the accesses were independent. MDRAM was primarily used in graphic cards, such as those featuring the
4313:
line's function is extended to a per-byte "DQM" signal, which controls data input (writes) in addition to data output (reads). This allows DRAM chips to be wider than 8 bits while still supporting byte-granularity writes.
3826:, R, and including internal timers that would periodically poll the row at R and then increment the value in the register. Refreshes were interleaved with common instructions like memory reads. In other systems, especially
3265:
can be used for data storage. This gives 1T DRAM cells the greatest density as well as allowing easier integration with high-performance logic circuits since they are constructed with the same SOI process technologies.
1976:. The 1103 was designed by Joel Karp and laid out by Pat Earhart. The masks were cut by Barbara Maness and Judy Garcia. MOS memory overtook magnetic-core memory as the dominant memory technology in the early 1970s.
3187:
per bit of storage. Starting in the mid-1980s, the capacitor was moved above or below the silicon substrate in order to meet these objectives. DRAM cells featuring capacitors above the substrate are referred to as
2104:
between the bit-lines. The first inverter is connected with input from the + bit-line and output to the â bit-line. The second inverter's input is from the â bit-line with output to the + bit-line. This results in
3913:), valid data would appear on the data out pins, which were held at high-Z before the appearance of valid data. For writes, the write enable signal and write data would be presented along with the column address.
5142:
3506:
often retain their values for significantly longer time, particularly at low temperatures. Under some conditions most of the data in DRAM can be recovered even if it has not been refreshed for several minutes.
3645:
Since the fundamental DRAM cell and array has maintained the same basic structure for many years, the types of DRAM are mainly distinguished by the many different interfaces for communicating with DRAM chips.
1895:. In 1966, Tomohisa Yoshimaru and Hiroshi Komikawa from Toshiba applied for a Japanese patent of a memory circuit composed of several transistors and a capacitor, in 1967 they applied for a patent in the US.
3456:; sometimes, the required logic is transparently implemented within DRAM chips or modules, enabling the ECC memory functionality for otherwise ECC-incapable systems. The extra memory bits are used to record
1703:
circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to
4500:. WRAM was designed to perform better and cost less than VRAM. WRAM offered up to 25% greater bandwidth than VRAM and accelerated commonly used graphical operations such as text drawing and block fills.
4068:
Synchronous dynamic RAM (SDRAM) significantly revises the asynchronous memory interface, adding a clock (and a clock enable) line. All other signals are received on the rising edge of the clock.
4442:
Reduced
Latency DRAM (RLDRAM) is a high performance double data rate (DDR) SDRAM that combines fast, random access with high bandwidth, mainly intended for networking and caching applications.
5334:
The first commercial synchronous DRAM, the
Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.
3273:
of the transistor. Performance-wise, access times are significantly better than capacitor-based DRAMs, but slightly worse than SRAM. There are several types of 1T DRAMs: the commercialized
4924:
3781:
The refresh cycles are distributed across the entire refresh interval in such a way that all rows are refreshed within the required interval. To refresh one row of the memory array using
5828:
Borucki, "Comparison of
Accelerated DRAM Soft Error Rates Measured at Component and System Level", 46th Annual International Reliability Physics Symposium, Phoenix, 2008, pp. 482â487
3182:
Up until the mid-1980s, the capacitors in DRAM cells were co-planar with the access transistor (they were constructed on the surface of the substrate), thus they were referred to as
3141:
5946:"Cycles, cells and platters: an empirical analysis of hardware failures on a million consumer PCs. Proceedings of the sixth conference on Computer systems (EuroSys '11). pp 343-356"
3075:
2241:
Many parameters are required to fully describe the timing of DRAM operation. Here are some examples for two timing grades of asynchronous DRAM, from a data sheet published in 1998:
1906:, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory. Capacitors had also been used for earlier memory schemes, such as the drum of the
4038:
Single-cycle EDO DRAM became very popular on video cards towards the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more costly VRAM.
4962:
6485:
5899:
5372:
3770:
Although the DRAM is asynchronous, the signals are typically generated by a clocked memory controller, which limits their timing to multiples of the controller's clock cycle.
3352:
this advantage is slightly diminished by the dummy bitline segments. The disadvantage that caused the near disappearance of this architecture is the inherent vulnerability to
6141:
2812:
to 10 ns. However, the DDR3 memory does achieve 32 times higher bandwidth; due to internal pipelining and wide data paths, it can output two words every 1.25 ns
3674:
An asynchronous DRAM chip has power connections, some number of address inputs (typically 12), and a few (typically one or four) bidirectional data lines. There are four
6076:
5149:
4819:
2074:
3511:
remanence, then transferring them to a different computer to be read out. Such an attack was demonstrated to circumvent popular disk encryption systems, such as the
1623:
676:
5546:
6517:
3902:
low, the row could be kept open, and multiple reads or writes could be performed to any of the columns in the row. Each column access was initiated by asserting
4386:
Double data rate SDRAM (DDR SDRAM or DDR) was a later development of SDRAM, used in PC memory beginning in 2000. Subsequent versions are numbered sequentially (
1779:
with a simultaneous reduction in cost per bit. Refreshing the data consumes power and a variety of techniques are used to manage the overall power consumption.
1763:
consoles. In contrast, SRAM, which is faster and more expensive than DRAM, is typically used where speed is of greater concern than cost and size, such as the
6157:
5480:
3662:" was the first type of DRAM in use. From its origins in the late 1960s, it was commonplace in computing up until around 1997, when it was mostly replaced by
6380:
3452:
memory bits and additional circuitry that use these bits to detect and correct soft errors. In most cases, the detection and correction are performed by the
3407:
or by cutting the wire by a laser. The spare rows or columns are substituted in by remapping logic in the row and column decoders (Jacob, pp. 358â361).
3830:, refresh was often handled by the video circuitry as it often had to read from large areas of memory, and performed refreshes as part of these operations.
3269:
Refreshing of cells remains necessary, but unlike with 1T1C DRAM, reads in 1T DRAM are non-destructive; the stored charge causes a detectable shift in the
2136:
The desired row's word-line is then driven high to connect a cell's storage capacitor to its bit-line. This causes the transistor to conduct, transferring
3565:
DRAM chips manufactured in 2012 and 2013 are susceptible to disturbance errors. The associated side effect that led to observed bit flips has been dubbed
3403:
small number of rows or columns to be inoperable. The defective rows and columns are physically disconnected from the rest of the array by a triggering a
1824:
3882:
is then asserted again, this performs a CBR refresh cycle while the DRAM outputs remain valid. Because data output is not interrupted, this is known as
3212:
use the stacked capacitor structure, whereas smaller manufacturers such Nanya
Technology use the trench capacitor structure (Jacob, pp. 355â357).
1697:
on the capacitors gradually leaks away; without intervention the data on the capacitor would soon be lost. To prevent this, DRAM requires an external
6046:
5623:
3846:(normally an illegal operation), then the DRAM ignores the address inputs and uses an internal counter to select the row to open. This is known as
3557:
in an adjacent or even nearby row. The awareness of disturbance errors dates back to the first commercially available DRAM in the early 1970s (the
5952:
4764:
3364:
The folded bitline array architecture routes bitlines in pairs throughout the array. The close proximity of the paired bitlines provide superior
4921:
4012:
with EDO DRAM support. Irrespective of the performance gains, FPM and EDO SIMMs can be used interchangeably in many (but not all) applications.
3818:
cycles. An external counter is needed to iterate over the row addresses in turn. In some designs, the CPU handled RAM refresh, among these the
3464:(ECC). Parity allows the detection of all single-bit errors (actually, any odd number of wrong bits). The most common error-correcting code, a
6314:
3953:
is a variant of fast page mode in which the column address does not need to be stored in, but rather, the address inputs may be changed with
3561:). Despite the mitigation techniques employed by manufacturers, commercial researchers proved in a 2014 analysis that commercially available
1940:
6923:
5928:
3916:
Page mode DRAM was in turn later improved with a small modification which further reduced latency. DRAMs with this improvement were called
3932:
was still deasserted. The column address propagated through the column address data path, but did not output data on the data pins until
3468:, allows a single-bit error to be corrected and, in the usual configuration, with an extra parity bit, double-bit errors to be detected.
6239:
5222:
6540:
5844:
5599:
5173:
6928:
6266:
3723:, Output Enable. This is an additional signal that controls output to the data I/O pins. The data pins are driven by the DRAM chip if
6034:
Yoongu Kim; Ross Daly; Jeremie Kim; Chris Fallin; Ji Hye Lee; Donghyuk Lee; Chris
Wilkerson; Konrad Lai; Onur Mutlu (June 24, 2014).
5703:
5563:
4589:
5412:
6687:
6679:
4989:
4601:
4339:
4063:
3553:. In particular, there is a risk that some charge can leak between nearby cells, causing the refresh or read of one row to cause a
2008:
671:
4900:
4344:
Single data rate SDRAM (SDR SDRAM or SDR) is the original generation of SDRAM; it made a single transfer of data per clock cycle.
5455:
3617:
1934:, while he was working on MOS memory and was trying to create an alternative to SRAM which required six MOS transistors for each
6098:
5991:
Scheick, Leif Z.; Guertin, Steven M.; Swift, Gary M. (December 2000). "Analysis of radiation effects on individual DRAM cells".
4946:
3445:
secondaries, which may change the contents of one or more memory cells or interfere with the circuitry used to read/write them.
4776:
Micron MT4C1024 â 1 mebibit (220 bit) dynamic ram. Widely used in 286 and 386-era computers, early 90s. Die size - 8662x3969Ξm.
3854:(CBR) refresh. This became the standard form of refresh for asynchronous DRAM, and is the only form generally used with SDRAM.
1565:
6072:
5116:
4811:
4664:
data stored in DRAM, rather than to allow operation without a separate DRAM controller as is in the case of mentioned PSRAMs.
2227:
Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes.
2109:
which stabilizes after one bit-line is fully at its highest voltage and the other bit-line is at the lowest possible voltage.
6467:
5744:
5249:
4876:
4374:
1106:
5301:
5076:
2448:
When describing synchronous memory, timing is described by clock cycle counts separated by hyphens. These numbers represent
5922:""A Realistic Evaluation of Memory Hardware Errors and Software System Susceptibility". Usenix Annual Tech Conference 2010"
5865:
5203:
4788:
1931:
6361:
4330:. By alternating banks, an SDRAM device can keep the data bus continuously busy, in a way that asynchronous DRAM cannot.
4551:
of MDRAM had enough memory to provide 24-bit color at a resolution of 1024Ã768—a very popular setting at the time.
4046:
An evolution of EDO DRAM, burst EDO DRAM (BEDO DRAM), could process four memory addresses in one burst, for a maximum of
3465:
1939:
development of the single-transistor MOS DRAM memory cell. He filed a patent in 1967, and was granted U.S. patent number
6388:
5777:
3024:/2 across the capacitor is required to store a logic zero. The electrical charge stored in the capacitor is measured in
3012:
The capacitor has two terminals, one of which is connected to its access transistor, and the other to either ground or V
6439:
5543:
3016:/2. In modern DRAMs, the latter case is more common, since it allows faster operation. In modern DRAMs, a voltage of +V
1315:
267:
6528:
5807:
5727:
F. Morishita; et al. (21 September 2005). "A capacitorless twin-transistor random access memory (TTRAM) on SOI".
3323:
performance of the array, since propagation time of the signal that must transverse the wordline is determined by the
2798:, and even the premium 20 ns variety is only 2.5 times better compared to the typical case (~2.22 times better).
312:
6214:
5423:
4675:. It is a set of small DRAM banks with an SRAM cache in front to make it behave much like a true SRAM. It is used in
3963:
is another variant in which four sequential locations within the row can be accessed with four consecutive pulses of
2145:
other is at the maximum high voltage. Once this has happened, the row is "open" (the desired cell data is available).
1690:
1054:
997:
317:
78:
6576:
Modern DRAM Memory Systems: Performance Analysis and a High Performance, Power-Constrained DRAM-Scheduling Algorithm
6154:
5491:
4577:
3590:
Dynamic RAM ICs can be packaged in molded epoxy cases, with an internal lead frame for interconnections between the
6969:
3633:
165:
49:
6539:
Mandelman, J. A.; Dennard, R. H.; Bronner, G. B.; Debrosse, J. K.; Divakaruni, R.; Li, Y.; Radens, C. J. (2002).
5895:
4559:
Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It adds functions such as
1380:
1040:
984:
6640:
5972:
5266:
1881:
gradually leaked away, a periodic pulse was applied to top up those still charged (hence the term 'dynamic')".
1066:
735:
547:
143:
3248:
The one-transistor, zero-capacitor (1T, or 1T0C) DRAM cell has been a topic of research since the late-1990s.
4644:
3967:. The difference from normal page mode is that the address inputs are not used for the second through fourth
3928:
was asserted before the column address was supplied. In FPM DRAM, the column address could be supplied while
2199:
Typically, manufacturers specify that each row must be refreshed every 64 ms or less, as defined by the
2130:
1415:
3471:
Recent studies give widely varying error rates with over seven orders of magnitude difference, ranging from
3092:
6964:
6789:
6035:
5630:
5188:
3031:
2486:
with a 200 MHz clock, while premium-priced high performance PC3200 DDR DRAM DIMM might be operated at
1907:
1648:
766:
562:
5853:
Proceedings of the Eleventh International Joint Conference on Measurement and Modeling of Computer Systems
3170:. If the capacitor contains a logic zero, it begins to discharge when the gate terminal voltage is above V
1803:
Memory Corporation after 2017 spin-off) which doesn't manufacture DRAM. Other manufacturers make and sell
5289:
4731:
4536:
1705:
723:
26:
Transistorized memory, such as RAM, ROM, flash and cache sizes as well as file sizes are specified using
5973:"Center for Information Technology Policy Âŧ Lest We Remember: Cold Boot Attacks on Encryption Keys"
3713:
is a read (if high) or write (if low). If low, the data inputs are also captured on the falling edge of
5606:
5278:
3519:
2213:
1755:
1558:
1355:
1254:
1126:
756:
745:
6495:
5945:
4760:
854:
4721:
3616:
DRAM that is integrated into an integrated circuit designed in a logic-optimized process (such as an
3146:
Reading or writing a logic one requires the wordline is driven to a voltage greater than the sum of V
617:
552:
447:
6567:
5405:
4547:
because of MDRAM's ability to be implemented more easily with such capacities. A graphics card with
6954:
6281:
4841:
4605:
4379:
3999:
who then licensed technology to many other memory manufacturers. EDO RAM, sometimes referred to as
3591:
3449:
2125:
The precharge circuit is switched off. Because the bit-lines are relatively long, they have enough
1776:
1583:
1427:
1410:
899:
185:
56:
6509:
6402:
1731:
chip, which can consist of dozens to billions of DRAM memory cells. DRAM chips are widely used in
5081:
4450:
Graphics RAMs are asynchronous and synchronous DRAMs designed for graphics-related tasks such as
2999:
2478:
in multiples of the DRAM clock cycle time. Note that this is half of the data transfer rate when
1930:
invented modern DRAM architecture in which there's a single MOS transistor per capacitor, at the
1768:
1678:
1422:
1239:
962:
367:
202:
180:
160:
113:
6918:
3498:
to retain its contents when supplied with power and refreshed every short period of time (often
6574:
5346:
4932:
4693:
3425:
Electrical or magnetic interference inside a computer system can cause a single bit of DRAM to
1295:
512:
382:
322:
6490:. Electrical Engineering and Computer Sciences,University of California, Berkeley. p. 15.
5921:
4866:
4535:
fashion, providing bandwidths suitable for graphics cards at a lower cost to memories such as
4497:
1856:
A schematic drawing depicting the cross-section of the original one-transistor, one-capacitor
644:
6959:
6741:
6503:
6231:
5219:
4689:
3838:
For convenience, the counter was quickly incorporated into the DRAM chips themselves. If the
3461:
3282:
3236:
First-generation DRAM ICs (those with capacities of 1 Kbit), of which the first was the
2101:
2059:
1948:
1889:
1720:), since it loses its data quickly when power is removed. However, DRAM does exhibit limited
1551:
798:
716:
502:
307:
287:
277:
133:
98:
20:
6560:
6498:â A 1997 discussion of SDRAM reliabilityâsome interesting information on "soft errors" from
5841:
4492:
Window DRAM (WRAM) is a variant of VRAM that was once used in graphics adaptors such as the
4394:, etc.). DDR SDRAM internally performs double-width accesses at the clock rate, and uses a
2219:
The row address of the row that will be refreshed next is maintained by external logic or a
1601:
6902:
6340:
6262:
6000:
5037:
5007:
3599:
3512:
3434:
3390:
process technology, array architecture, and area efficiency is an active area of research.
3297:
3262:
3258:
1972:, in October 1970, despite initial problems with low yield until the fifth revision of the
1903:
1670:
1667:
1494:
1362:
1141:
1101:
1024:
637:
542:
432:
327:
190:
170:
153:
148:
6933:
5692:
5574:
4023:
rises again. It holds the output valid (thus extending the data output time) until either
3195:
capacitors. Those with capacitors buried beneath the substrate surface are referred to as
8:
6541:"Challenges and future directions for the scaling of dynamic random-access memory (DRAM)"
5377:
5120:
3759:
cycle must not be attempted until the sense amplifiers have sensed the memory state, and
3353:
3209:
1899:
1808:
1792:
1732:
1717:
1400:
1091:
1029:
1014:
881:
833:
686:
497:
195:
6142:"What is DRAM refresh and why is the weird Apple II video memory layout affected by it?"
6004:
2015:. The first commercial SDRAM chip was the Samsung KM48SL2000, which had a capacity of 16
6773:
6633:
5750:
5430:
4892:
4713:
4532:
3823:
3399:
3365:
1820:
1728:
1591:
1500:
1465:
1111:
537:
522:
467:
462:
452:
427:
352:
6618:
5444:
5055:
3971:
edges; they are generated internally starting with the address supplied for the first
6463:
6435:
6210:
6105:
6016:
5740:
5324:
5245:
5167:
5099:, Dennard, Robert H., "Field-effect transistor memory", issued 1968-06-04
4943:
4872:
3996:
3789:
The row address of the row to be refreshed must be applied at the address input pins.
3453:
3270:
3205:
2220:
2170:
2106:
2041:
1960:
1784:
1587:
1177:
1172:
1096:
1061:
915:
893:
792:
751:
654:
492:
217:
5754:
3699:, the Column Address Strobe. The address inputs are captured on the falling edge of
3301:
Self-aligned storage node locations simplify the fabrication process in modern DRAM.
2052:
6583:
6552:
6416:
6365:
6304:
6296:
6008:
5837:
5732:
4598:
4395:
3957:
held low, and the data output will be updated accordingly a few nanoseconds later.
3947:
latency. Fast page mode DRAM was introduced in 1986 and was used with Intel 80486.
3625:
3531:
3324:
2479:
2037:
Later, in 2001, Japanese DRAM makers accused Korean DRAM manufacturers of dumping.
2027:
1512:
1506:
1432:
1395:
1385:
1350:
1162:
1116:
1084:
859:
842:
527:
487:
247:
232:
128:
118:
6279:
5373:"Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option"
4543:
ET6x00 chipsets. Boards based upon this chipset often had the unusual capacity of
6725:
6457:
6429:
6204:
6161:
5848:
5550:
5319:
5239:
5226:
4950:
4928:
4741:
4477:
4009:
3685:, the Row Address Strobe. The address inputs are captured on the falling edge of
3404:
3335:
2137:
2097:
2005:
Department's International Trade Administration ruled in favor of the complaint.
1736:
1713:
1694:
1405:
1232:
1219:
910:
905:
761:
628:
607:
582:
442:
362:
292:
262:
237:
123:
94:
5873:
4424:
in 1999, it was intended to become an industry standard, but was outcompeted by
55:
The references used may be made clearer with a different or consistent style of
5096:
4967:
4451:
3621:
3489:
2236:
2188:
2150:
2001:
1927:
1915:
1873:
1721:
1699:
1524:
1442:
1285:
942:
804:
740:
612:
597:
577:
572:
517:
482:
437:
387:
377:
372:
357:
252:
242:
175:
60:
5736:
4480:
variant of DRAM that was once commonly used to store the frame-buffer in some
3767:
is driven high, it must be held high long enough for precharging to complete.
1947:
MOS DRAM chips were commercialized in 1969 by Advanced Memory Systems, Inc of
6948:
6879:
6794:
6626:
6020:
5785:
4481:
3827:
3585:
3225:
3020:/2 across the capacitor is required to store a logic one; and a voltage of -V
1911:
1865:
1816:
1750:
1530:
1157:
1152:
1121:
876:
786:
602:
592:
587:
567:
402:
392:
272:
257:
27:
3995:
Extended data out DRAM (EDO DRAM) was invented and patented in the 1990s by
3763:
must not be returned high until the storage cells have been refreshed. When
2080:
1852:
6122:
5815:
4726:
3543:
2208:
2129:
to maintain the precharged voltage for a brief time. This is an example of
1992:
1877:
1812:
1709:
1477:
1471:
1437:
1305:
1260:
1244:
1136:
932:
927:
887:
849:
532:
507:
407:
342:
297:
282:
6601:
6280:
Cuppu, Vinodh; Jacob, Bruce; Davis, Brian; Mudge, Trevor (November 2001).
6033:
5731:. Vol. Custom Integrated Circuits Conference 2005. pp. 428â431.
3666:. In the present day, manufacture of asynchronous RAM is relatively rare.
1795:" that are "keeping a pretty tight rein on their capacity". There is also
6839:
6834:
6829:
6824:
6819:
6814:
6036:"Flipping Bits in Memory Without Accessing Them: DRAM Disturbance Errors"
5671:
5600:"Corsair CMX1024-3200 (1 GByte, two bank unbuffered DDR SDRAM DIMM)"
4736:
4524:
4455:
4421:
4319:
2799:
2126:
2112:
1980:
1741:
1640:
1536:
1488:
922:
457:
397:
302:
6556:
5729:
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
3983:
3940:
being asserted, the data out pins were held at high-Z. FPM DRAM reduced
3743:
can be permanently connected low (output always enabled), but switching
2153:
because, for the open row, all data has already been sensed and latched.
6809:
6712:
6707:
6702:
6697:
6499:
5896:"DRAM's Damning Defectsâand How They Cripple Computers - IEEE Spectrum"
5209:. Interviewed by Hendrie, Gardner. Computer History Museum. X3274.2006.
4540:
4459:
4369:
4365:
4361:
4357:
4283:
Auto refresh: refresh one row of each bank, using an internal counter.
3709:, Write Enable. This signal determines whether a given falling edge of
3675:
3567:
3558:
3550:
3523:
3457:
3442:
3430:
3426:
3420:
3416:
3237:
2389:
1969:
1857:
1760:
1686:
1647:
computer, 1990, with 64 MiB main memory DRAM (top left) and 256 KiB of
1636:
1131:
957:
711:
477:
472:
347:
212:
138:
6300:
6012:
2388:
Access time: Column address valid to valid data out (includes address
2274:
Random read or write cycle time (from one full /RAS cycle to another)
6869:
6692:
6587:
6309:
4425:
4353:
3819:
3527:
3515:
3503:
2023:
1973:
1952:
1764:
1682:
1518:
1483:
1320:
1249:
1147:
1018:
1009:
706:
649:
417:
337:
5976:
3778:
Classic asynchronous DRAM is refreshed by opening each row in turn.
6864:
6669:
6664:
6611:
4707:
4679:
4676:
4560:
3988:
3703:, and select a column from the currently open row to read or write.
3655:
1956:
1788:
1746:
1644:
1447:
1390:
1325:
1280:
1265:
1035:
1004:
977:
952:
810:
696:
422:
332:
227:
222:
5290:"More Japan Firms Accused: U.S. Contends 5 Companies Dumped Chips"
4519:
Multibank DRAM (MDRAM) is a type of specialized DRAM developed by
4015:
To be precise, EDO DRAM begins data output on the falling edge of
6897:
6761:
6525:
4th Annual Research Conference on Reliability Stanford University
6428:
Keeth, Brent; Baker, R. Jacob; Johnson, Brian; Lin, Feng (2007).
5382:
5350:
4868:
Colossus: The secrets of Bletchley Park's code-breaking computers
4672:
4653:
4582:
4083:, part of a 3-bit command controlled by a new active-low strobe,
3438:
3025:
2019:
2012:
1885:
1828:
1800:
1595:
1345:
1335:
1330:
1290:
1192:
1187:
1167:
972:
947:
937:
728:
3751:
This interface provides direct control of internal timing. When
3747:
can be useful when connecting multiple memory chips in parallel.
6851:
6736:
6538:
5406:"Japanese chip makers say they suspect dumping by Korean firms"
4633:
4625:
4493:
4437:
4303:
Load mode register: address bus specifies DRAM operation mode.
3595:
1984:
1832:
1796:
1340:
1300:
1182:
1071:
869:
412:
5805:
4508:
3822:
is perhaps the best known example, hosting a row counter in a
3632:(eDRAM). Embedded DRAM requires DRAM cell designs that can be
1578:
6859:
6804:
6799:
6766:
6751:
6731:
6719:
5189:"Reverse-engineering the classic MK4116 16-kilobit DRAM chip"
4761:"How to "open" microchip and what's inside? : ZeptoBars"
4668:
4629:
4621:
4617:
4613:
4609:
4520:
4512:
4408:
4079:
inputs no longer act as strobes, but are instead, along with
4005:
4004:
faster than FPM DRAM, which it began to replace in 1995 when
3611:
3544:§ Operations to read a data bit from a DRAM storage cell
3278:
3274:
3201:
3086:
2441:
page every two clock cycles. This was generally described as
2200:
1964:
1739:
is required. One of the largest applications for DRAM is the
1275:
1212:
1207:
1202:
864:
821:
815:
701:
681:
666:
6484:
Culler, David (2005). "Memory Capacity (Single Chip DRAM)".
5424:"DRAM pricing investigation in Japan targets Hynix, Samsung"
3689:, and select a row to open. The row is held open as long as
6892:
6887:
6756:
6746:
5693:"Principles of the 1T Dynamic Access Memory Concept on SOI"
4649:
4572:
4471:
3906:
and presenting a column address. For reads, after a delay (
3562:
3530:. This type of attack against a computer is often called a
3286:
2445:
timing, as bursts of four reads within a page were common.
1836:
1827:. Others sell such integrated into other products, such as
1804:
1708:(SRAM) which does not require data to be refreshed. Unlike
1270:
557:
207:
6496:
Benefits of Chipkill-Correct ECC for PC Server Main Memory
6512:
1994 literature review of memory error rate measurements.
5015:
4990:"1966: Semiconductor RAMs Serve High-speed Storage Needs"
4683:
4597:
Graphics double data rate SDRAM is a type of specialized
4183:
Burst Terminate: stop a read or write burst in progress.
3261:
transistors. Considered a nuisance in logic design, this
1935:
1674:
1628:
1310:
1197:
967:
6492:
Logarithmic graph 1980â2003 showing size and cycle time.
3810:
This can be done by supplying a row address and pulsing
3277:
from Innovative Silicon, the TTRAM from Renesas and the
6648:
5866:"A Memory Soft Error Measurement on Production Systems"
3598:
design used ICs, including those for DRAM, packaged in
2719:/RAS precharge time (minimum precharge to active time)
6431:
DRAM Circuit Design: Fundamental and High-Speed Topics
5806:
Mastipuram, Ritesh; Wee, Edwin C (30 September 2004).
5544:
Lest We Remember: Cold Boot Attacks on Encryption Keys
5413:"Japanese chip makers suspect dumping by Korean firms"
5071:
5069:
3095:
3034:
2113:
Operations to read a data bit from a DRAM storage cell
2062:
1604:
6518:"Scaling and Technology Issues for Soft Error Rates"
6427:
6341:"Burst EDO (BEDO) - Ram Guide | Tom's Hardware"
6282:"High-Performance DRAMs in Workstation Environments"
6190:
6173:
5842:"DRAM errors in the wild: a large-scale field study"
5658:
5646:
5531:
5241:
American Industrial Policy: Free or Managed Markets?
4812:"Are the Major DRAM Suppliers Stunting DRAM Demand?"
4703:
4347:
4333:
3785:
only refresh (ROR), the following steps must occur:
2216:
that occurs every 10â20 ms in video equipment.
5990:
5700:
MOS Modeling and Parameter Extraction Group Meeting
5066:
4696:-compliant 8-pin HyperBus or Octal xSPI interface.
3314:is a number derived from the DRAM cell design, and
2768:Row active time (minimum active to precharge time)
2482:signaling is used. JEDEC standard PC3200 timing is
2056:The principles of operation for reading a simple 4
2022:, and was introduced in 1992. The first commercial
6598:A detailed description of current DRAM technology.
6487:EECS 252 Graduate Computer Architecture: Lecture 1
6381:"Under the Hood â Update: Apple iPhone 3G exposed"
5919:
5624:"Corsair TWINX1024-3200XL dual-channel memory kit"
5077:"1970: Semiconductors compete with magnetic cores"
4671:variant of PSRAM was sold by MoSys under the name
4566:
3460:and to enable missing data to be reconstructed by
3135:
3069:
2369:Page-mode read or write cycle time (/CAS to /CAS)
2068:
1617:
6099:"Understanding DRAM Operation (Application Note)"
5312:
4031:falling edge selects a different column address.
3429:to the opposite state. The majority of one-off ("
3410:
1759:). It is also used in many portable devices and
6946:
6612:"What every programmer should know about memory"
6456:Jacob, Bruce; Wang, David; Ng, Spencer (2010) .
3150:and the access transistor's threshold voltage (V
1898:The earliest forms of DRAM mentioned above used
5527:
5525:
5523:
5521:
5519:
5517:
5515:
5513:
5511:
4328:while a read from the first bank is in progress
1979:The first DRAM with multiplexed row and column
4420:) was developed by Rambus. First supported on
4399:memory), but each access transfers more data.
3494:Although dynamic memory is only specified and
6634:
6582:(PhD). University of Maryland, College Park.
6510:Tezzaron Semiconductor Soft Error White Paper
5403:
5302:"Japanese Chip Dumping Has Ended, U.S. Finds"
4839:
3433:") errors in DRAM chips occur as a result of
3384:
2820:, while the EDO DRAM can output one word per
2774:Minimum random access time has improved from
2350:/RAS precharge time (minimum /RAS high time)
1963:, and others. The same year, Honeywell asked
1902:. While it offered improved performance over
1559:
6186:
6184:
6182:
5726:
5508:
5478:
5431:"Korean DRAM finds itself shut out of Japan"
4692:'s HyperRAM is a type of PSRAM supporting a
3669:
3393:
6455:
6232:"Memory Grades, the Most Confusing Subject"
5808:"Soft errors' impact on system reliability"
5114:
4944:Toshiba "Toscal" BC-1411 Desktop Calculator
4554:
3802:At the end of the required amount of time,
2827: = 20 ns (50 Mword/s).
2040:In 2002, US computer makers made claims of
691:
19:"DRAM" redirects here. For other uses, see
6641:
6627:
6202:
5831:
5332:(15â21). Hayden Publishing Company. 1993.
5201:
4604:designed to be used as the main memory of
4428:, making it technically obsolete by 2003.
4057:
3231:
2614:/CAS low to valid data out (equivalent to
2047:
1807:(but not the DRAM chips in them), such as
1745:(colloquially called the "RAM") in modern
1566:
1552:
6308:
6179:
6167:
5652:
5640:
4893:"Spec Sheet for Toshiba "TOSCAL" BC-1411"
4842:"DRAM Boom and Bust is Business as Usual"
3978:
3833:
2331:/RAS pulse width (minimum /RAS low time)
2100:is essentially a pair of cross-connected
1888:introduced a bipolar dynamic RAM for its
79:Learn how and when to remove this message
6515:
5984:
5822:
5553:, Halderman et al, USENIX Security 2008.
5220:"Outbreak of Japan-US Semiconductor War"
5202:Proebsting, Robert (14 September 2005).
5186:
5117:"Who Invented the Intel 1103 DRAM Chip?"
4871:. Oxford University Press. p. 301.
4864:
4643:
4588:
4576:
4507:
4373:
4263:Precharge (deactivate) the current row.
4064:Synchronous dynamic random-access memory
3982:
3814:low; it is not necessary to perform any
3359:
3296:
3243:
2411:Access time: /CAS low to valid data out
2293:Access time: /RAS low to valid data out
2169:
2079:
2051:
2009:Synchronous dynamic random-access memory
1851:
1635:
1577:
6609:
6545:IBM Journal of Research and Development
6378:
6354:
5967:
5965:
5814:. Cypress Semiconductor. Archived from
5690:
5556:
5279:"6 Japan Chip Makers Cited for Dumping"
5276:
5095:
4593:Inside a Samsung GDDR3 256-MBit package
4431:
3618:application-specific integrated circuit
3330:
3136:{\textstyle Q={-V_{CC} \over 2}\cdot C}
2830:
1753:(where the "main memory" is called the
6947:
6483:
5564:"Micron 4 Meg x 4 EDO DRAM data sheet"
5299:
5264:
5237:
5172:: CS1 maint: archived copy as title (
5000:
4753:
4382:of a Samsung DDR-SDRAM 64-MBit package
3448:The problem can be mitigated by using
3342:
3070:{\textstyle Q={V_{CC} \over 2}\cdot C}
2118:The sense amplifiers are disconnected.
30:for K (1024), M (1024), G (1024), etc.
6622:
6260:
6209:. Que; Har/Cdr Edition. p. 221.
6070:
4885:
4402:
3594:and the package leads. The original
2993:
2165:
2034:Mb DDR SDRAM chip, released in 1998.
1107:Vision Electronic Recording Apparatus
6572:
6338:
6242:from the original on 7 November 2017
6104:. IBM. December 1996. Archived from
6073:"SDRAM Memory Basics & Tutorial"
5993:IEEE Transactions on Nuclear Science
5962:
5858:
5300:Sanger, David E. (3 November 1987).
4840:EETimes; Hilson, Gary (2018-09-20).
3870:refresh, it is possible to deassert
3654:The original DRAM, now known by the
3649:
3537:
3372:This architecture is referred to as
2084:Basic structure of a DRAM cell array
1932:IBM Thomas J. Watson Research Center
1727:DRAM typically takes the form of an
1594:(1994). It has a capacity of 1
32:
6261:Huang, Andrew (14 September 1996).
6229:
5691:Sallese, Jean-Michel (2002-06-20).
5277:Woutat., Donald (4 November 1985).
5204:"Oral History of Robert Proebsting"
4639:
4243:Activate a row for read and write.
3773:
3292:
3177:
2030:SDRAM) memory chip was Samsung's 64
1860:DRAM cell. It was patented in 1968.
1811:, and some manufacturers that sell
13:
6449:
6320:from the original on 8 August 2017
6269:from the original on 12 June 2017.
5265:Sanger, David E. (3 August 1985).
4019:but does not stop the output when
3028:. For a logic one, the charge is:
1921:
268:Data validation and reconciliation
14:
6981:
6477:
6459:Memory Systems: Cache, DRAM, Disk
4503:
4348:Double data rate synchronous DRAM
4334:Single data rate synchronous DRAM
4041:
3889:
3857:
3483:
3306:area. DRAM cell area is given as
1951:. This 1024 bit chip was sold to
1735:where low-cost and high-capacity
318:Distributed file system for cloud
6230:Lin, Albert (20 December 1999).
5958:from the original on 2012-11-14.
5934:from the original on 2015-05-15.
4903:from the original on 3 July 2017
4706:
4279:
4259:
4203:Read from currently active row.
4179:
4159:
4139:
4136:
4133:
4130:
3878:low to maintain data output. If
3579:
3089:. A logic zero has a charge of:
2230:
1831:into its CPUs, AMD in GPUs, and
166:Areal density (computer storage)
37:
6409:
6395:
6379:Mannion, Patrick (2008-07-12).
6372:
6332:
6273:
6254:
6223:
6206:Upgrading and Repairing Laptops
6196:
6155:Various Methods of DRAM Refresh
6148:
6134:
6115:
6091:
6079:from the original on 2018-02-27
6064:
6052:from the original on 2015-03-26
6027:
5938:
5913:
5902:from the original on 2015-11-24
5888:
5799:
5778:"ECC DRAM â Intelligent Memory"
5770:
5761:
5720:
5709:from the original on 2007-11-29
5684:
5664:
5616:
5605:. December 2003. Archived from
5592:
5537:
5481:"Lecture 20: Memory Technology"
5472:
5461:from the original on 2015-06-16
5437:
5397:
5365:
5339:
5267:"Japan chip 'dumping' is found"
5258:
5231:
5213:
5195:
5187:Shirriff, Ken (November 2020).
5180:
5135:
5108:
5089:
5048:
5030:
4982:
4822:from the original on 2018-04-16
4767:from the original on 2016-03-14
4567:Graphics double data rate SDRAM
4523:. It is constructed from small
4445:
4223:Write to currently active row.
4143:Command inhibit (no operation)
2182:
1681:, usually consisting of a tiny
985:Programmable metallization cell
6339:Kent, Dean (24 October 1998).
6289:IEEE Transactions on Computers
6164:Micron Technical Note TN-04-30
5490:. pp. 3â5. Archived from
4955:
4937:
4915:
4858:
4833:
4804:
4781:
4487:
3795:must switch from high to low.
3739:is low. In many applications,
3411:Error detection and correction
3081:is the charge in coulombs and
2864:â precharge to precharge delay
548:Persistence (computer science)
1:
6516:Johnston, A. (October 2000).
6502:, especially with respect to
5920:Li, Huang; Shen, Chu (2010).
4789:"NeXTServiceManualPages1-160"
4747:
4465:
2802:has improved even less, from
2430:/CAS low pulse width minimum
2194:
1847:
1651:(lower edge, right of middle)
1416:Electronic quantum holography
6650:Dynamic random-access memory
3574:
1839:in some of their GPU chips.
1656:Dynamic random-access memory
767:Video RAM (dual-ported DRAM)
563:Non-RAID drive architectures
7:
5479:David August (2004-11-23).
5238:Nester, William R. (2016).
5119:. ThoughtCo. Archived from
5115:Mary Bellis (23 Feb 2018).
4897:www.oldcalculatormuseum.com
4732:List of interface bit rates
4699:
4531:, which are operated in an
3640:
3605:
3478:
2781: = 50 ns to
1706:static random-access memory
10:
6986:
6573:Wang, David Tawei (2005).
5767:J. Park et al., IEDM 2015.
5629:. May 2004. Archived from
4865:Copeland, B. Jack (2010).
4652:pseudostatic RAM, made by
4570:
4469:
4435:
4406:
4351:
4337:
4061:
3842:line is driven low before
3609:
3583:
3541:
3520:BitLocker Drive Encryption
3487:
3414:
3385:Future array architectures
3259:silicon on insulator (SOI)
3154:). This voltage is called
2997:
2967:â Write to precharge delay
2767:
2718:
2670:/RAS low to /CAS low time
2669:
2613:
2429:
2410:
2387:
2368:
2349:
2330:
2312:/RAS low to /CAS low time
2311:
2292:
2273:
2234:
2214:vertical blanking interval
2192:
2186:
1842:
1815:(used e.g. in the fastest
1689:, both typically based on
1356:Holographic Versatile Disc
1255:Compact Disc Digital Audio
1127:Magnetic-tape data storage
746:Content-addressable memory
25:
18:
6911:
6878:
6850:
6782:
6678:
6657:
5981:080222 citp.princeton.edu
5737:10.1109/CICC.2005.1568699
5445:"Lecture 12: DRAM Basics"
5244:. Springer. p. 115.
4922:Toscal BC-1411 calculator
4722:DRAM price fixing scandal
4606:graphics processing units
3394:Row and column redundancy
2931:â Read to precharge delay
2526:
2523:
2520:
2517:
2514:
2511:
2506:
2503:
2500:
2497:
2495:
2011:(SDRAM) was developed by
1691:metalâoxideâsemiconductor
553:Persistent data structure
448:Digital rights management
6610:Drepper, Ulrich (2007).
6602:Multi-port Cache DRAM â
6419:. Cypress semiconductor.
6405:. Cypress semiconductor.
5347:"KM48SL2000-7 Datasheet"
4555:Synchronous graphics RAM
4027:is deasserted, or a new
2900:â Row refresh cycle time
1908:AtanasoffâBerry Computer
1428:DNA digital data storage
1411:Holographic data storage
900:Solid-state hybrid drive
186:Network-attached storage
6970:20th-century inventions
6568:Ars Technica: RAM Guide
5082:Computer History Museum
5060:Encyclopedia Britannica
4994:Computer History Museum
4476:Video DRAM (VRAM) is a
4058:Synchronous dynamic RAM
3936:was asserted. Prior to
3670:Principles of operation
3377:column into the voids.
3232:Historical cell designs
3000:Memory cell (computing)
2069:{\displaystyle \times }
2048:Principles of operation
1423:5D optical data storage
1240:3D optical data storage
963:Universal Flash Storage
368:Replication (computing)
313:Distributed file system
203:Single-instance storage
181:Direct-attached storage
161:Continuous availability
16:Type of computer memory
5404:Kuriko Miyake (2001).
4933:Science Museum, London
4656:
4594:
4586:
4516:
4383:
4095:SDRAM Command summary
3992:
3979:Extended data out DRAM
3924:). In page mode DRAM,
3834:CAS before RAS refresh
3302:
3137:
3085:is the capacitance in
3071:
2985:â Write to write delay
2175:
2174:Writing to a DRAM cell
2085:
2077:
2070:
1861:
1823:), separately such as
1652:
1633:
1619:
1618:{\displaystyle 2^{20}}
1296:Nintendo optical discs
513:Storage virtualization
383:Information repository
323:Distributed data store
6504:error-correcting code
5870:www.ece.rochester.edu
5782:intelligentmemory.com
5672:"Pro Audio Reference"
5612:on 11 September 2008.
4690:Cypress Semiconductor
4686:video game consoles.
4647:
4592:
4580:
4511:
4377:
3986:
3600:dual in-line packages
3462:error-correcting code
3360:Folded bitline arrays
3300:
3244:Proposed cell designs
3138:
3072:
2976:â Write to read delay
2958:â Write recovery time
2949:â Read to write delay
2504:PC3-12800 (DDR3-1600)
2173:
2083:
2071:
2055:
1890:electronic calculator
1855:
1639:
1620:
1581:
799:Mellon optical memory
787:WilliamsâKilburn tube
503:Locality of reference
308:Clustered file system
134:Memory access pattern
5580:on 27 September 2007
4432:Reduced Latency DRAM
3918:fast page mode DRAMs
3435:background radiation
3331:Bitline architecture
3263:floating body effect
3093:
3032:
2940:â Read to read delay
2831:Timing abbreviations
2060:
1904:magnetic-core memory
1671:semiconductor memory
1602:
1495:Magnetic-core memory
1142:Digital Data Storage
1102:Quadruplex videotape
543:In-memory processing
433:Information transfer
328:Distributed database
191:Storage area network
171:Block (data storage)
6965:American inventions
6557:10.1147/rd.462.0187
6462:. Morgan Kaufmann.
6362:"Window RAM (WRAM)"
6203:S. Mueller (2004).
6124:Z80 CPU User Manual
6005:2000ITNS...47.2534S
5876:on 14 February 2017
5855:, pp. 193â204.
5702:. Wroclaw, Poland.
5636:on 7 December 2006.
5378:Samsung Electronics
5320:"Electronic Design"
4585:GDDR3 SDRAM package
4096:
3502:), the memory cell
3466:SECDED Hamming code
3400:integrated circuits
3343:Open bitline arrays
3210:Samsung Electronics
2501:PC2-6400 (DDR2-800)
1900:bipolar transistors
1868:machine code-named
1809:Kingston Technology
1793:Samsung Electronics
1733:digital electronics
1718:non-volatile memory
1092:Phonograph cylinder
1030:Electrochemical RAM
882:Solid-state storage
498:Memory segmentation
196:Block-level storage
6774:Hybrid Memory Cube
6343:. Tomshardware.com
6263:"Bunnie's RAM FAQ"
6160:2011-10-03 at the
6111:on 29 August 2017.
5847:2015-03-10 at the
5549:2015-01-05 at the
5385:. 10 February 1999
5225:2020-02-29 at the
4949:2007-05-20 at the
4927:2017-07-29 at the
4816:www.icinsights.com
4714:Electronics portal
4657:
4648:1 Mbit high speed
4595:
4587:
4517:
4414:Direct RAMBUS DRAM
4403:Direct Rambus DRAM
4384:
4094:
3993:
3987:A pair of 32
3824:processor register
3427:spontaneously flip
3303:
3133:
3067:
2994:Memory cell design
2922:â RAS to RAS delay
2882:â RAS to CAS delay
2176:
2166:To write to memory
2086:
2078:
2066:
1884:In November 1965,
1862:
1729:integrated circuit
1653:
1634:
1615:
1592:integrated circuit
1586:photograph of the
1501:Plated-wire memory
1466:Paper data storage
1112:Magnetic recording
538:In-memory database
523:Memory-mapped file
468:Volume boot record
463:Master boot record
453:Volume (computing)
428:Data communication
353:Data deduplication
6942:
6941:
6469:978-0-08-055384-9
6403:"psRAM(HyperRAM)"
6301:10.1109/12.966491
6295:(11): 1133â1153.
6191:Keeth et al. 2007
6174:Keeth et al. 2007
6013:10.1109/23.903804
5979:on July 22, 2011.
5838:Schroeder, Bianca
5818:on 16 April 2007.
5746:978-0-7803-9023-2
5659:Keeth et al. 2007
5647:Keeth et al. 2007
5532:Keeth et al. 2007
5433:. Phys.org. 2006.
5325:Electronic Design
5294:Los Angeles Times
5283:Los Angeles Times
5251:978-1-349-25568-9
5062:. September 2023.
4878:978-0-19-157366-8
4482:graphics adaptors
4307:
4306:
3997:Micron Technology
3862:Given support of
3806:must return high.
3799:must remain high.
3755:is driven low, a
3678:control signals:
3660:asynchronous DRAM
3650:Asynchronous DRAM
3555:disturbance error
3538:Memory corruption
3473:10â10 error/bit·h
3454:memory controller
3405:programmable fuse
3271:threshold voltage
3206:Micron Technology
3125:
3059:
2991:
2990:
2873:â RAS active time
2772:
2771:
2498:PC-3200 (DDR-400)
2434:
2433:
2392:before /CAS low)
2151:row opening delay
2107:positive feedback
2042:DRAM price fixing
1961:Wang Laboratories
1825:Viking Technology
1785:Micron Technology
1673:that stores each
1588:Micron Technology
1576:
1575:
1173:8 mm video format
1097:Phonograph record
916:Flash Core Module
894:Solid-state drive
793:Delay-line memory
752:Computational RAM
655:Scratchpad memory
493:Disk partitioning
218:Unstructured data
144:Secondary storage
89:
88:
81:
6977:
6934:Transistor count
6643:
6636:
6629:
6620:
6619:
6615:
6597:
6595:
6594:
6581:
6564:
6559:. Archived from
6551:(2.3): 187â212.
6535:
6533:
6527:. Archived from
6522:
6491:
6473:
6445:
6421:
6420:
6413:
6407:
6406:
6399:
6393:
6392:
6387:. Archived from
6376:
6370:
6369:
6364:. Archived from
6358:
6352:
6351:
6349:
6348:
6336:
6330:
6329:
6327:
6325:
6319:
6312:
6286:
6277:
6271:
6270:
6258:
6252:
6251:
6249:
6247:
6227:
6221:
6220:
6200:
6194:
6188:
6177:
6171:
6165:
6152:
6146:
6145:
6138:
6132:
6131:
6129:
6119:
6113:
6112:
6110:
6103:
6095:
6089:
6088:
6086:
6084:
6068:
6062:
6061:
6059:
6057:
6051:
6040:
6031:
6025:
6024:
5999:(6): 2534â2538.
5988:
5982:
5980:
5975:. Archived from
5969:
5960:
5959:
5957:
5950:
5942:
5936:
5935:
5933:
5926:
5917:
5911:
5910:
5908:
5907:
5892:
5886:
5885:
5883:
5881:
5872:. Archived from
5862:
5856:
5835:
5829:
5826:
5820:
5819:
5803:
5797:
5796:
5794:
5793:
5784:. Archived from
5774:
5768:
5765:
5759:
5758:
5724:
5718:
5717:
5715:
5714:
5708:
5697:
5688:
5682:
5681:
5679:
5678:
5668:
5662:
5656:
5650:
5644:
5638:
5637:
5635:
5628:
5620:
5614:
5613:
5611:
5604:
5596:
5590:
5589:
5587:
5585:
5579:
5573:. Archived from
5568:
5560:
5554:
5541:
5535:
5534:, pp. 24â30
5529:
5506:
5505:
5503:
5502:
5496:
5488:cs.princeton.edu
5485:
5476:
5470:
5469:
5467:
5466:
5460:
5449:
5441:
5435:
5434:
5427:
5426:. EETimes. 2001.
5420:
5409:
5401:
5395:
5394:
5392:
5390:
5369:
5363:
5362:
5360:
5358:
5343:
5337:
5336:
5316:
5310:
5309:
5297:
5286:
5274:
5262:
5256:
5255:
5235:
5229:
5217:
5211:
5210:
5208:
5199:
5193:
5192:
5184:
5178:
5177:
5171:
5163:
5161:
5160:
5154:
5148:. Archived from
5147:
5139:
5133:
5132:
5130:
5128:
5123:on March 6, 2013
5112:
5106:
5105:
5104:
5100:
5093:
5087:
5086:
5073:
5064:
5063:
5056:"Robert Dennard"
5052:
5046:
5045:
5044:. 9 August 2017.
5034:
5028:
5027:
5025:
5023:
5004:
4998:
4997:
4986:
4980:
4979:
4977:
4975:
4963:"Memory Circuit"
4959:
4953:
4941:
4935:
4919:
4913:
4912:
4910:
4908:
4889:
4883:
4882:
4862:
4856:
4855:
4853:
4852:
4837:
4831:
4830:
4828:
4827:
4808:
4802:
4801:
4799:
4798:
4793:
4785:
4779:
4778:
4773:
4772:
4757:
4716:
4711:
4710:
4640:Pseudostatic RAM
4550:
4546:
4530:
4396:double data rate
4312:
4117:
4112:
4107:
4102:
4097:
4093:
4090:
4082:
4078:
4074:
4049:
4030:
4026:
4022:
4018:
3991:EDO DRAM modules
3974:
3970:
3966:
3956:
3939:
3935:
3931:
3927:
3905:
3901:
3881:
3877:
3873:
3869:
3865:
3853:
3849:
3845:
3841:
3817:
3813:
3805:
3798:
3794:
3784:
3774:RAS Only Refresh
3766:
3762:
3758:
3754:
3746:
3742:
3738:
3734:
3730:
3726:
3722:
3716:
3712:
3708:
3702:
3698:
3692:
3688:
3684:
3664:Synchronous DRAM
3626:system on a chip
3532:cold boot attack
3501:
3474:
3336:Sense amplifiers
3325:RC time constant
3293:Array structures
3178:Capacitor design
3142:
3140:
3139:
3134:
3126:
3121:
3120:
3119:
3103:
3076:
3074:
3073:
3068:
3060:
3055:
3054:
3042:
2891:â Refresh period
2835:
2834:
2819:
2817:
2811:
2797:
2493:
2492:
2489:
2485:
2480:double data rate
2477:
2444:
2244:
2243:
2075:
2073:
2072:
2067:
2033:
2028:double data rate
2018:
1893:"Toscal" BC-1411
1666:) is a type of
1632:
1624:
1622:
1621:
1616:
1614:
1613:
1568:
1561:
1554:
1513:Thin-film memory
1507:Core rope memory
1433:Universal memory
1396:Millipede memory
1386:Racetrack memory
1351:Ultra HD Blu-ray
1163:Linear Tape-Open
1117:Magnetic storage
1085:Analog recording
528:Software entropy
488:Disk aggregation
248:Data degradation
233:Data compression
129:Memory hierarchy
119:Memory coherence
91:
90:
84:
77:
73:
70:
64:
41:
40:
33:
6985:
6984:
6980:
6979:
6978:
6976:
6975:
6974:
6955:Computer memory
6945:
6944:
6943:
6938:
6907:
6874:
6846:
6778:
6726:Fast Cycle DRAM
6674:
6653:
6647:
6592:
6590:
6579:
6531:
6520:
6480:
6470:
6452:
6450:Further reading
6442:
6424:
6415:
6414:
6410:
6401:
6400:
6396:
6377:
6373:
6360:
6359:
6355:
6346:
6344:
6337:
6333:
6323:
6321:
6317:
6284:
6278:
6274:
6259:
6255:
6245:
6243:
6228:
6224:
6217:
6201:
6197:
6189:
6180:
6172:
6168:
6162:Wayback Machine
6153:
6149:
6140:
6139:
6135:
6127:
6121:
6120:
6116:
6108:
6101:
6097:
6096:
6092:
6082:
6080:
6069:
6065:
6055:
6053:
6049:
6038:
6032:
6028:
5989:
5985:
5971:
5970:
5963:
5955:
5948:
5944:
5943:
5939:
5931:
5924:
5918:
5914:
5905:
5903:
5894:
5893:
5889:
5879:
5877:
5864:
5863:
5859:
5849:Wayback Machine
5840:et al. (2009).
5836:
5832:
5827:
5823:
5804:
5800:
5791:
5789:
5776:
5775:
5771:
5766:
5762:
5747:
5725:
5721:
5712:
5710:
5706:
5695:
5689:
5685:
5676:
5674:
5670:
5669:
5665:
5657:
5653:
5645:
5641:
5633:
5626:
5622:
5621:
5617:
5609:
5602:
5598:
5597:
5593:
5583:
5581:
5577:
5566:
5562:
5561:
5557:
5551:Wayback Machine
5542:
5538:
5530:
5509:
5500:
5498:
5494:
5483:
5477:
5473:
5464:
5462:
5458:
5447:
5443:
5442:
5438:
5429:
5428:
5422:
5421:
5411:
5410:
5402:
5398:
5388:
5386:
5371:
5370:
5366:
5356:
5354:
5345:
5344:
5340:
5318:
5317:
5313:
5298:
5288:
5287:
5275:
5263:
5259:
5252:
5236:
5232:
5227:Wayback Machine
5218:
5214:
5206:
5200:
5196:
5185:
5181:
5165:
5164:
5158:
5156:
5152:
5145:
5143:"Archived copy"
5141:
5140:
5136:
5126:
5124:
5113:
5109:
5102:
5094:
5090:
5075:
5074:
5067:
5054:
5053:
5049:
5038:"IBM100 â DRAM"
5036:
5035:
5031:
5021:
5019:
5018:. 9 August 2017
5006:
5005:
5001:
4988:
4987:
4983:
4973:
4971:
4961:
4960:
4956:
4951:Wayback Machine
4942:
4938:
4929:Wayback Machine
4920:
4916:
4906:
4904:
4891:
4890:
4886:
4879:
4863:
4859:
4850:
4848:
4838:
4834:
4825:
4823:
4810:
4809:
4805:
4796:
4794:
4791:
4787:
4786:
4782:
4770:
4768:
4759:
4758:
4754:
4750:
4742:Memory geometry
4712:
4705:
4702:
4642:
4575:
4569:
4557:
4548:
4544:
4528:
4506:
4498:ATI 3D Rage Pro
4496:Millennium and
4490:
4474:
4468:
4448:
4440:
4434:
4411:
4405:
4372:
4352:Main articles:
4350:
4342:
4336:
4310:
4115:
4110:
4105:
4100:
4088:
4080:
4076:
4072:
4066:
4060:
4047:
4044:
4028:
4024:
4020:
4016:
4008:introduced the
4001:hyper page mode
3981:
3972:
3968:
3964:
3954:
3946:
3937:
3933:
3929:
3925:
3912:
3903:
3899:
3892:
3879:
3875:
3871:
3867:
3863:
3860:
3851:
3847:
3843:
3839:
3836:
3815:
3811:
3803:
3796:
3792:
3782:
3776:
3764:
3760:
3756:
3752:
3744:
3740:
3736:
3732:
3728:
3724:
3720:
3714:
3710:
3706:
3700:
3696:
3690:
3686:
3682:
3672:
3652:
3643:
3624:, or an entire
3614:
3608:
3588:
3582:
3577:
3546:
3540:
3499:
3492:
3486:
3481:
3472:
3423:
3415:Main articles:
3413:
3398:The first DRAM
3396:
3387:
3362:
3345:
3333:
3295:
3246:
3234:
3180:
3173:
3169:
3165:
3159:
3153:
3149:
3112:
3108:
3104:
3102:
3094:
3091:
3090:
3047:
3043:
3041:
3033:
3030:
3029:
3023:
3019:
3015:
3002:
2996:
2984:
2975:
2966:
2957:
2948:
2939:
2930:
2921:
2909:â RAS precharge
2908:
2899:
2890:
2881:
2872:
2863:
2854:
2845:
2833:
2826:
2815:
2813:
2809:
2803:
2795:
2788:
2782:
2780:
2729:
2680:
2631:
2620:
2575:
2487:
2483:
2476:
2469:
2462:
2455:
2449:
2442:
2421:
2402:
2379:
2360:
2341:
2322:
2303:
2284:
2265:
2239:
2233:
2197:
2195:§ Security
2191:
2185:
2168:
2115:
2098:sense amplifier
2061:
2058:
2057:
2050:
2031:
2016:
1991:Early in 1985,
1924:
1922:Single MOS DRAM
1850:
1845:
1756:graphics memory
1737:computer memory
1714:volatile memory
1695:electric charge
1626:
1609:
1605:
1603:
1600:
1599:
1572:
1543:
1542:
1461:
1453:
1452:
1406:Patterned media
1376:
1368:
1367:
1235:
1225:
1224:
1220:Hard disk drive
1087:
1077:
1076:
1057:
1046:
1045:
1000:
990:
989:
911:IBM FlashSystem
906:USB flash drive
845:
828:
827:
782:
774:
773:
762:Dual-ported RAM
640:
623:
622:
583:Cloud computing
443:Copy protection
363:Data redundancy
293:Shared resource
263:Data validation
238:Data corruption
213:Structured data
124:Cache coherence
109:
95:Computer memory
85:
74:
68:
65:
54:
48:has an unclear
42:
38:
31:
28:binary meanings
24:
17:
12:
11:
5:
6983:
6973:
6972:
6967:
6962:
6957:
6940:
6939:
6937:
6936:
6931:
6926:
6924:SDRAM timeline
6921:
6915:
6913:
6909:
6908:
6906:
6905:
6900:
6895:
6890:
6884:
6882:
6880:Memory modules
6876:
6875:
6873:
6872:
6867:
6862:
6856:
6854:
6848:
6847:
6845:
6844:
6843:
6842:
6837:
6832:
6827:
6822:
6817:
6812:
6802:
6797:
6792:
6786:
6784:
6780:
6779:
6777:
6776:
6771:
6770:
6769:
6764:
6759:
6754:
6749:
6739:
6734:
6729:
6723:
6717:
6716:
6715:
6710:
6705:
6700:
6690:
6684:
6682:
6676:
6675:
6673:
6672:
6667:
6661:
6659:
6655:
6654:
6646:
6645:
6638:
6631:
6623:
6617:
6616:
6607:
6599:
6570:
6565:
6563:on 2005-03-22.
6536:
6534:on 2004-11-03.
6513:
6507:
6493:
6479:
6478:External links
6476:
6475:
6474:
6468:
6451:
6448:
6447:
6446:
6441:978-0470184752
6440:
6423:
6422:
6408:
6394:
6391:on 2013-01-22.
6371:
6368:on 2010-01-02.
6353:
6331:
6272:
6253:
6236:Simmtester.com
6222:
6215:
6195:
6178:
6166:
6147:
6133:
6114:
6090:
6063:
6026:
5983:
5961:
5937:
5912:
5887:
5857:
5830:
5821:
5798:
5769:
5760:
5745:
5719:
5683:
5663:
5651:
5639:
5615:
5591:
5555:
5536:
5507:
5471:
5454:. 2011-02-17.
5436:
5396:
5364:
5338:
5311:
5306:New York Times
5271:New York Times
5257:
5250:
5230:
5212:
5194:
5179:
5134:
5107:
5088:
5065:
5047:
5029:
4999:
4981:
4968:Google Patents
4954:
4936:
4914:
4884:
4877:
4857:
4832:
4803:
4780:
4763:. 2012-11-15.
4751:
4749:
4746:
4745:
4744:
4739:
4734:
4729:
4724:
4718:
4717:
4701:
4698:
4641:
4638:
4571:Main article:
4568:
4565:
4556:
4553:
4505:
4504:Multibank DRAM
4502:
4489:
4486:
4470:Main article:
4467:
4464:
4452:texture memory
4447:
4444:
4436:Main article:
4433:
4430:
4407:Main article:
4404:
4401:
4349:
4346:
4335:
4332:
4305:
4304:
4301:
4298:
4295:
4292:
4289:
4285:
4284:
4281:
4278:
4275:
4272:
4269:
4265:
4264:
4261:
4258:
4255:
4252:
4249:
4245:
4244:
4241:
4238:
4235:
4232:
4229:
4225:
4224:
4221:
4218:
4215:
4212:
4209:
4205:
4204:
4201:
4198:
4195:
4192:
4189:
4185:
4184:
4181:
4178:
4175:
4172:
4169:
4165:
4164:
4161:
4158:
4155:
4152:
4149:
4145:
4144:
4141:
4138:
4135:
4132:
4129:
4125:
4124:
4121:
4118:
4113:
4108:
4103:
4062:Main article:
4059:
4056:
4043:
4042:Burst EDO DRAM
4040:
3980:
3977:
3944:
3910:
3895:Page mode DRAM
3891:
3890:Page mode DRAM
3888:
3884:hidden refresh
3874:while holding
3859:
3858:Hidden refresh
3856:
3835:
3832:
3828:home computers
3808:
3807:
3800:
3790:
3775:
3772:
3749:
3748:
3718:
3704:
3694:
3671:
3668:
3651:
3648:
3642:
3639:
3622:microprocessor
3610:Main article:
3607:
3604:
3584:Main article:
3581:
3578:
3576:
3573:
3539:
3536:
3518:, Microsoft's
3490:Data remanence
3488:Main article:
3485:
3484:Data remanence
3482:
3480:
3477:
3412:
3409:
3395:
3392:
3386:
3383:
3361:
3358:
3344:
3341:
3332:
3329:
3294:
3291:
3245:
3242:
3233:
3230:
3179:
3176:
3171:
3167:
3163:
3157:
3151:
3147:
3132:
3129:
3124:
3118:
3115:
3111:
3107:
3101:
3098:
3066:
3063:
3058:
3053:
3050:
3046:
3040:
3037:
3021:
3017:
3013:
2995:
2992:
2989:
2988:
2987:
2986:
2982:
2977:
2973:
2968:
2964:
2959:
2955:
2950:
2946:
2941:
2937:
2932:
2928:
2923:
2919:
2912:
2911:
2910:
2906:
2901:
2897:
2892:
2888:
2883:
2879:
2874:
2870:
2865:
2861:
2856:
2855:â Command rate
2852:
2847:
2843:
2832:
2829:
2824:
2818: Mword/s)
2807:
2796:= 22.5 ns
2793:
2786:
2778:
2770:
2769:
2766:
2763:
2760:
2757:
2754:
2751:
2748:
2745:
2742:
2739:
2736:
2733:
2730:
2727:
2721:
2720:
2717:
2714:
2711:
2708:
2705:
2702:
2699:
2696:
2693:
2690:
2687:
2684:
2681:
2678:
2672:
2671:
2668:
2665:
2662:
2659:
2656:
2653:
2650:
2647:
2644:
2641:
2638:
2635:
2632:
2629:
2623:
2622:
2618:
2612:
2609:
2606:
2603:
2600:
2597:
2594:
2591:
2588:
2585:
2582:
2579:
2576:
2573:
2567:
2566:
2563:
2560:
2557:
2554:
2551:
2548:
2545:
2542:
2539:
2536:
2533:
2529:
2528:
2525:
2522:
2519:
2516:
2513:
2509:
2508:
2505:
2502:
2499:
2496:
2474:
2467:
2460:
2453:
2432:
2431:
2428:
2425:
2422:
2419:
2413:
2412:
2409:
2406:
2403:
2400:
2394:
2393:
2386:
2383:
2380:
2377:
2371:
2370:
2367:
2364:
2361:
2358:
2352:
2351:
2348:
2345:
2342:
2339:
2333:
2332:
2329:
2326:
2323:
2320:
2314:
2313:
2310:
2307:
2304:
2301:
2295:
2294:
2291:
2288:
2285:
2282:
2276:
2275:
2272:
2269:
2266:
2263:
2257:
2256:
2253:
2250:
2247:
2237:Memory timings
2235:Main article:
2232:
2229:
2189:Memory refresh
2187:Main article:
2184:
2181:
2167:
2164:
2163:
2162:
2158:
2154:
2146:
2142:
2134:
2123:
2119:
2114:
2111:
2065:
2049:
2046:
2002:export dumping
1928:Robert Dennard
1923:
1920:
1916:Selectron tube
1874:Bletchley Park
1849:
1846:
1844:
1841:
1817:supercomputers
1765:cache memories
1751:graphics cards
1722:data remanence
1700:memory refresh
1612:
1608:
1598:equivalent to
1590:MT4C1024 DRAM
1574:
1573:
1571:
1570:
1563:
1556:
1548:
1545:
1544:
1541:
1540:
1534:
1528:
1525:Twistor memory
1522:
1516:
1510:
1504:
1498:
1492:
1486:
1481:
1475:
1469:
1462:
1459:
1458:
1455:
1454:
1451:
1450:
1445:
1443:Quantum memory
1440:
1435:
1430:
1425:
1420:
1419:
1418:
1408:
1403:
1398:
1393:
1388:
1383:
1377:
1375:In development
1374:
1373:
1370:
1369:
1366:
1365:
1360:
1359:
1358:
1353:
1348:
1343:
1338:
1333:
1328:
1323:
1318:
1313:
1308:
1303:
1298:
1293:
1288:
1286:Super Video CD
1283:
1278:
1273:
1268:
1263:
1258:
1252:
1247:
1236:
1231:
1230:
1227:
1226:
1223:
1222:
1217:
1216:
1215:
1210:
1205:
1200:
1195:
1190:
1185:
1180:
1175:
1170:
1165:
1160:
1155:
1150:
1145:
1139:
1134:
1129:
1124:
1119:
1109:
1104:
1099:
1094:
1088:
1083:
1082:
1079:
1078:
1075:
1074:
1069:
1064:
1058:
1052:
1051:
1048:
1047:
1044:
1043:
1038:
1033:
1027:
1022:
1012:
1007:
1001:
996:
995:
992:
991:
988:
987:
982:
981:
980:
975:
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965:
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945:
943:MultiMediaCard
940:
935:
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920:
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913:
908:
903:
897:
891:
879:
874:
873:
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867:
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852:
846:
841:
840:
837:
836:
830:
829:
826:
825:
819:
813:
808:
805:Selectron tube
802:
796:
790:
783:
780:
779:
776:
775:
772:
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749:
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689:
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674:
669:
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658:
657:
652:
645:Hardware cache
641:
636:
635:
632:
631:
625:
624:
621:
620:
615:
610:
605:
600:
598:Edge computing
595:
590:
585:
580:
578:Grid computing
575:
573:Bank switching
570:
565:
560:
555:
550:
545:
540:
535:
530:
525:
520:
518:Virtual memory
515:
510:
505:
500:
495:
490:
485:
483:Disk mirroring
480:
475:
470:
465:
460:
455:
450:
445:
440:
438:Temporary file
435:
430:
425:
420:
415:
410:
405:
400:
395:
390:
388:Knowledge base
385:
380:
378:Storage record
375:
373:Memory refresh
370:
365:
360:
358:Data structure
355:
350:
345:
340:
335:
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325:
320:
315:
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305:
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253:Data integrity
250:
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243:Data cleansing
240:
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215:
210:
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200:
199:
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176:Object storage
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136:
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110:
107:
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87:
86:
50:citation style
45:
43:
36:
15:
9:
6:
4:
3:
2:
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6956:
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6950:
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6927:
6925:
6922:
6920:
6919:DRAM timeline
6917:
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5839:
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5825:
5817:
5813:
5809:
5802:
5788:on 2014-12-23
5787:
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5779:
5773:
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5752:
5748:
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5526:
5524:
5522:
5520:
5518:
5516:
5514:
5512:
5497:on 2005-05-19
5493:
5489:
5482:
5475:
5457:
5453:
5446:
5440:
5432:
5425:
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5414:
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5384:
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5368:
5353:. August 1992
5352:
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5234:
5228:
5224:
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5216:
5205:
5198:
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5183:
5175:
5169:
5155:on 2014-01-16
5151:
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5098:
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4315:
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4230:
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4199:
4196:
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4190:
4187:
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4182:
4176:
4173:
4170:
4167:
4166:
4163:No operation
4162:
4156:
4153:
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4147:
4146:
4142:
4127:
4126:
4122:
4119:
4114:
4109:
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4092:
4086:
4069:
4065:
4055:
4051:
4039:
4036:
4032:
4013:
4011:
4010:430FX chipset
4007:
4002:
3998:
3990:
3985:
3976:
3962:
3958:
3952:
3951:Static column
3948:
3943:
3923:
3919:
3914:
3909:
3896:
3887:
3885:
3855:
3831:
3829:
3825:
3821:
3801:
3791:
3788:
3787:
3786:
3779:
3771:
3768:
3735:is high, and
3719:
3705:
3695:
3681:
3680:
3679:
3677:
3667:
3665:
3661:
3657:
3647:
3638:
3635:
3631:
3630:embedded DRAM
3627:
3623:
3619:
3613:
3603:
3601:
3597:
3593:
3587:
3586:Memory module
3580:Memory module
3572:
3570:
3569:
3564:
3560:
3556:
3552:
3545:
3535:
3533:
3529:
3525:
3521:
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3508:
3505:
3497:
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3463:
3459:
3455:
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3428:
3422:
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3408:
3406:
3401:
3391:
3382:
3378:
3375:
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3357:
3355:
3349:
3340:
3337:
3328:
3326:
3320:
3317:
3313:
3309:
3299:
3290:
3288:
3284:
3280:
3276:
3272:
3267:
3264:
3260:
3254:
3251:
3241:
3239:
3229:
3227:
3226:embedded DRAM
3221:
3217:
3213:
3211:
3207:
3203:
3198:
3194:
3190:
3185:
3175:
3161:
3144:
3130:
3127:
3122:
3116:
3113:
3109:
3105:
3099:
3096:
3088:
3084:
3080:
3064:
3061:
3056:
3051:
3048:
3044:
3038:
3035:
3027:
3010:
3008:
3001:
2981:
2978:
2972:
2969:
2963:
2960:
2954:
2951:
2945:
2942:
2936:
2933:
2927:
2924:
2918:
2915:
2914:
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2905:
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2896:
2893:
2887:
2884:
2878:
2875:
2869:
2866:
2860:
2857:
2851:
2848:
2846:â CAS latency
2842:
2839:
2838:
2837:
2836:
2828:
2823:
2806:
2801:
2792:
2785:
2777:
2764:
2761:
2759:33.75 ns
2758:
2755:
2752:
2749:
2746:
2743:
2740:
2737:
2734:
2731:
2726:
2723:
2722:
2715:
2712:
2710:11.25 ns
2709:
2706:
2703:
2700:
2697:
2694:
2691:
2688:
2685:
2682:
2677:
2674:
2673:
2666:
2663:
2661:11.25 ns
2660:
2657:
2654:
2651:
2648:
2645:
2642:
2639:
2636:
2633:
2628:
2625:
2624:
2617:
2610:
2607:
2605:11.25 ns
2604:
2601:
2598:
2595:
2592:
2589:
2586:
2583:
2580:
2577:
2572:
2569:
2568:
2564:
2561:
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2543:
2540:
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2510:
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2270:
2267:
2262:
2259:
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2245:
2242:
2238:
2231:Memory timing
2228:
2225:
2222:
2217:
2215:
2210:
2204:
2202:
2196:
2190:
2180:
2172:
2159:
2155:
2152:
2147:
2143:
2139:
2135:
2132:
2131:dynamic logic
2128:
2124:
2120:
2117:
2116:
2110:
2108:
2103:
2099:
2094:
2090:
2082:
2063:
2054:
2045:
2043:
2038:
2035:
2029:
2025:
2021:
2014:
2010:
2006:
2003:
1997:
1994:
1989:
1986:
1982:
1981:address lines
1977:
1975:
1971:
1966:
1962:
1958:
1954:
1950:
1949:Sunnyvale, CA
1945:
1942:
1937:
1933:
1929:
1926:In 1966, Dr.
1919:
1917:
1913:
1912:Williams tube
1909:
1905:
1901:
1896:
1894:
1891:
1887:
1882:
1879:
1875:
1871:
1867:
1866:cryptanalytic
1859:
1854:
1840:
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1806:
1802:
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1723:
1719:
1715:
1711:
1707:
1702:
1701:
1696:
1692:
1688:
1684:
1680:
1677:of data in a
1676:
1672:
1669:
1668:random-access
1665:
1661:
1657:
1650:
1646:
1642:
1638:
1630:
1610:
1606:
1597:
1593:
1589:
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1569:
1564:
1562:
1557:
1555:
1550:
1549:
1547:
1546:
1538:
1535:
1532:
1531:Bubble memory
1529:
1526:
1523:
1520:
1517:
1514:
1511:
1508:
1505:
1502:
1499:
1496:
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1234:
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1199:
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1158:Cassette tape
1156:
1154:
1153:Videocassette
1151:
1149:
1146:
1143:
1140:
1138:
1135:
1133:
1130:
1128:
1125:
1123:
1122:Magnetic tape
1120:
1118:
1115:
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1110:
1108:
1105:
1103:
1100:
1098:
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904:
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877:ROM cartridge
875:
871:
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848:
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639:
634:
633:
630:
627:
626:
619:
616:
614:
611:
609:
606:
604:
603:Dew computing
601:
599:
596:
594:
593:Fog computing
591:
589:
588:Cloud storage
586:
584:
581:
579:
576:
574:
571:
569:
568:Memory paging
566:
564:
561:
559:
556:
554:
551:
549:
546:
544:
541:
539:
536:
534:
531:
529:
526:
524:
521:
519:
516:
514:
511:
509:
506:
504:
501:
499:
496:
494:
491:
489:
486:
484:
481:
479:
476:
474:
471:
469:
466:
464:
461:
459:
456:
454:
451:
449:
446:
444:
441:
439:
436:
434:
431:
429:
426:
424:
421:
419:
416:
414:
411:
409:
406:
404:
403:File deletion
401:
399:
396:
394:
393:Computer file
391:
389:
386:
384:
381:
379:
376:
374:
371:
369:
366:
364:
361:
359:
356:
354:
351:
349:
346:
344:
341:
339:
336:
334:
331:
329:
326:
324:
321:
319:
316:
314:
311:
309:
306:
304:
301:
299:
296:
294:
291:
289:
286:
284:
281:
279:
276:
274:
273:Data recovery
271:
269:
266:
264:
261:
259:
258:Data security
256:
254:
251:
249:
246:
244:
241:
239:
236:
234:
231:
229:
226:
224:
221:
219:
216:
214:
211:
209:
206:
204:
201:
197:
194:
192:
189:
188:
187:
184:
182:
179:
177:
174:
172:
169:
167:
164:
162:
159:
155:
154:floating-gate
152:
151:
150:
147:
145:
142:
140:
137:
135:
132:
130:
127:
125:
122:
120:
117:
115:
112:
111:
105:
104:
100:
96:
93:
92:
83:
80:
72:
62:
58:
52:
51:
46:This article
44:
35:
34:
29:
22:
6960:Types of RAM
6722:(Mobile DDR)
6658:Asynchronous
6649:
6603:
6591:. Retrieved
6575:
6561:the original
6548:
6544:
6529:the original
6524:
6486:
6458:
6430:
6411:
6397:
6389:the original
6384:
6374:
6366:the original
6356:
6345:. Retrieved
6334:
6322:. Retrieved
6292:
6288:
6275:
6256:
6244:. Retrieved
6238:. CST, Inc.
6235:
6225:
6205:
6198:
6193:, p. 14
6176:, p. 13
6169:
6150:
6136:
6130:. p. 3.
6123:
6117:
6106:the original
6093:
6081:. Retrieved
6066:
6054:. Retrieved
6042:
6029:
5996:
5992:
5986:
5977:the original
5940:
5915:
5904:. Retrieved
5890:
5878:. Retrieved
5874:the original
5869:
5860:
5852:
5833:
5824:
5816:the original
5811:
5801:
5790:. Retrieved
5786:the original
5781:
5772:
5763:
5728:
5722:
5711:. Retrieved
5699:
5686:
5675:. Retrieved
5666:
5661:, p. 24
5654:
5649:, p. 22
5642:
5631:the original
5618:
5607:the original
5594:
5582:. Retrieved
5575:the original
5570:
5558:
5539:
5499:. Retrieved
5492:the original
5487:
5474:
5463:. Retrieved
5451:
5439:
5416:
5399:
5387:. Retrieved
5376:
5367:
5355:. Retrieved
5341:
5333:
5329:
5323:
5314:
5305:
5293:
5282:
5270:
5260:
5240:
5233:
5215:
5197:
5182:
5157:. Retrieved
5150:the original
5137:
5125:. Retrieved
5121:the original
5110:
5091:
5080:
5059:
5050:
5041:
5032:
5022:20 September
5020:. Retrieved
5011:
5002:
4993:
4984:
4972:. Retrieved
4966:
4957:
4939:
4917:
4905:. Retrieved
4896:
4887:
4867:
4860:
4849:. Retrieved
4845:
4835:
4824:. Retrieved
4815:
4806:
4795:. Retrieved
4783:
4775:
4769:. Retrieved
4755:
4727:Flash memory
4688:
4666:
4662:
4658:
4596:
4558:
4525:memory banks
4518:
4491:
4475:
4456:framebuffers
4449:
4446:Graphics RAM
4441:
4422:motherboards
4417:
4413:
4412:
4391:
4387:
4385:
4343:
4327:
4324:
4316:
4308:
4084:
4070:
4067:
4052:
4045:
4037:
4033:
4014:
4000:
3994:
3960:
3959:
3950:
3949:
3941:
3921:
3917:
3915:
3907:
3894:
3893:
3883:
3861:
3837:
3809:
3780:
3777:
3769:
3750:
3673:
3663:
3659:
3653:
3644:
3629:
3628:) is called
3615:
3589:
3566:
3554:
3547:
3509:
3495:
3493:
3470:
3447:
3424:
3397:
3388:
3379:
3373:
3371:
3363:
3350:
3346:
3334:
3321:
3315:
3311:
3307:
3304:
3289:consortium.
3268:
3255:
3249:
3247:
3235:
3222:
3218:
3214:
3196:
3193:folded plate
3192:
3188:
3183:
3181:
3155:
3145:
3082:
3078:
3011:
3006:
3003:
2979:
2970:
2961:
2952:
2943:
2934:
2925:
2916:
2903:
2894:
2885:
2876:
2867:
2858:
2849:
2840:
2821:
2810:= 13 ns
2804:
2790:
2783:
2775:
2773:
2724:
2698:12.5 ns
2675:
2649:12.5 ns
2626:
2615:
2593:12.5 ns
2570:
2507:Description
2471:
2464:
2457:
2450:
2447:
2439:
2435:
2416:
2397:
2374:
2355:
2336:
2317:
2298:
2279:
2260:
2255:Description
2252:"60 ns"
2249:"50 ns"
2240:
2226:
2218:
2209:refresh rate
2205:
2198:
2183:Refresh rate
2177:
2095:
2091:
2087:
2076:4 DRAM array
2039:
2036:
2007:
1998:
1993:Gordon Moore
1990:
1978:
1946:
1925:
1897:
1892:
1883:
1878:World War II
1869:
1863:
1813:stacked DRAM
1799:(previously
1781:
1773:
1754:
1740:
1726:
1710:flash memory
1698:
1663:
1659:
1655:
1654:
1478:Punched tape
1472:Punched card
1438:Time crystal
1306:Hyper CD-ROM
1245:Optical disc
1137:Tape library
1072:FeFET memory
1053:Early-stage
933:CompactFlash
928:Memory Stick
888:Flash memory
850:Diode matrix
834:Non-volatile
661:
618:Kryder's law
608:Amdahl's law
533:Software rot
508:Logical disk
408:File copying
343:Data storage
298:File sharing
283:Data cluster
99:data storage
75:
66:
47:
6680:Synchronous
6500:cosmic rays
6071:Ian Poole.
6043:ece.cmu.edu
4737:Memory bank
4581:A 512-MBit
4561:bit masking
4533:interleaved
4515:MDRAM MD908
4488:Window DRAM
4478:dual-ported
4460:video cards
4458:, found on
4320:CAS latency
4085:chip select
3961:Nibble mode
3592:silicon die
3551:soft errors
3513:open source
3366:common-mode
2800:CAS latency
2271:104 ns
2127:capacitance
1742:main memory
1679:memory cell
1660:dynamic RAM
1641:Motherboard
1537:Floppy disk
1489:Drum memory
923:Memory card
890:is used in:
824:(2002â2010)
789:(1946â1947)
613:Moore's law
458:Boot sector
398:Object file
303:File system
114:Memory cell
6949:Categories
6593:2007-03-10
6417:"Hyperbus"
6347:2022-03-09
6324:2 November
6246:1 November
5906:2015-11-24
5792:2015-01-16
5713:2007-10-07
5677:2024-08-08
5571:micron.com
5501:2015-03-10
5465:2015-03-10
5159:2014-01-15
5097:US3387286A
4851:2022-08-03
4826:2018-04-16
4797:2022-03-09
4771:2016-04-02
4748:References
4660:Platform.
4541:Tseng Labs
4466:Video DRAM
4370:DDR5 SDRAM
4366:DDR4 SDRAM
4362:DDR3 SDRAM
4358:DDR2 SDRAM
4338:See also:
3676:active-low
3634:fabricated
3568:row hammer
3559:Intel 1103
3542:See also:
3504:capacitors
3496:guaranteed
3443:cosmic ray
3437:, chiefly
3421:ECC memory
3417:RAM parity
3238:Intel 1103
2998:See also:
2765:30 ns
2753:30 ns
2747:40 ns
2741:25 ns
2735:40 ns
2716:10 ns
2704:10 ns
2692:10 ns
2686:20 ns
2667:10 ns
2655:10 ns
2643:10 ns
2637:20 ns
2611:10 ns
2599:10 ns
2587:10 ns
2581:15 ns
2427:10 ns
2408:15 ns
2405:13 ns
2390:setup time
2385:30 ns
2382:25 ns
2366:25 ns
2363:20 ns
2347:40 ns
2344:30 ns
2328:60 ns
2325:50 ns
2309:14 ns
2306:11 ns
2290:60 ns
2287:50 ns
2268:84 ns
2203:standard.
2193:See also:
1970:Intel 1103
1968:DRAM, the
1870:"Aquarius"
1848:Precursors
1769:processors
1761:video game
1712:, DRAM is
1687:transistor
1460:Historical
1132:Tape drive
958:SmartMedia
781:Historical
478:Disk image
473:Disk array
348:Data store
149:MOS memory
139:Memory map
69:April 2019
61:footnoting
6929:Bandwidth
6870:XDR2 DRAM
6693:DDR SDRAM
6588:1903/2432
6434:. Wiley.
6310:1903/7456
6056:March 10,
6021:0018-9499
4426:DDR SDRAM
4354:DDR SDRAM
4340:SDR SDRAM
3922:FPM DRAMs
3820:Zilog Z80
3731:are low,
3575:Packaging
3528:FileVault
3516:TrueCrypt
3450:redundant
3310:F, where
3281:from the
3128:⋅
3106:−
3062:⋅
3007:DRAM cell
2443:"5-2-2-2"
2424:8 ns
2102:inverters
2064:×
2024:DDR SDRAM
1953:Honeywell
1941:3,387,286
1777:densities
1747:computers
1683:capacitor
1519:Disk pack
1484:Plugboard
1321:DVD-Video
1250:LaserDisc
1148:Videotape
1019:3D XPoint
1010:Memristor
650:CPU cache
418:Core dump
338:Data bank
288:Directory
6865:XDR DRAM
6783:Graphics
6670:EDO DRAM
6665:FPM DRAM
6315:Archived
6267:Archived
6240:Archived
6158:Archived
6077:Archived
6047:Archived
5953:Archived
5951:. 2011.
5929:Archived
5900:Archived
5845:Archived
5755:14952912
5704:Archived
5547:Archived
5456:Archived
5452:utah.edu
5223:Archived
5168:cite web
4947:Archived
4925:Archived
4901:Archived
4820:Archived
4765:Archived
4700:See also
4680:GameCube
4677:Nintendo
4669:embedded
4123:Command
4120:Address
3866:-before-
3850:-before-
3656:retronym
3641:Versions
3606:Embedded
3479:Security
3439:neutrons
3077:, where
3026:coulombs
2490:timing.
1983:was the
1957:Raytheon
1914:and the
1872:used at
1821:exascale
1789:SK Hynix
1645:NeXTcube
1625:bits or
1448:UltraRAM
1326:DVD card
1281:Video CD
1266:CD Video
1036:Nano-RAM
1005:Memistor
978:XQD card
953:SIM card
811:Dekatron
697:XDR DRAM
692:EDO DRAM
629:Volatile
423:Hex dump
333:Database
228:Metadata
223:Big data
57:citation
6898:UniDIMM
6762:HBM-PIM
6728:(FCRAM)
6506:schemes
6385:EETimes
6001:Bibcode
5419:. 2001.
5417:ITWorld
5389:23 June
5383:Samsung
5357:19 June
5351:Samsung
5296:. 1986.
4974:18 June
4846:EETimes
4673:1T-SRAM
4654:Toshiba
4583:Qimonda
4549:2.25 MB
4545:2.25 MB
4048:5-1-1-1
3693:is low.
3250:1T DRAM
3189:stacked
2524:Typical
2518:Typical
2512:Typical
2488:2-2-2-5
2484:3-4-4-8
2221:counter
2093:lines.
2013:Samsung
1886:Toshiba
1876:during
1843:History
1835:, with
1829:Fujitsu
1819:on the
1801:Toshiba
1643:of the
1596:megabit
1533:(~1970)
1527:(~1968)
1509:(1960s)
1346:Blu-ray
1336:MiniDVD
1331:DVD-RAM
1291:Mini CD
1233:Optical
1193:U-matic
1188:MicroMV
1168:Betamax
1032:(ECRAM)
973:MicroP2
948:SD card
938:PC Card
729:1T-SRAM
687:QDRSRAM
278:Storage
108:General
6852:Rambus
6737:RLDRAM
6652:(DRAM)
6604:MP-RAM
6466:
6438:
6213:
6083:26 Feb
6019:
5753:
5743:
5408:. CNN.
5248:
5127:27 Feb
5103:
5012:IBM100
5008:"DRAM"
4875:
4634:GDDR6X
4626:GDDR5X
4529:256 kB
4494:Matrox
4438:RLDRAM
4418:DRDRAM
4368:, and
4220:Column
4200:Column
3975:edge.
3596:IBM PC
3522:, and
3458:parity
3374:folded
3197:trench
3184:planar
3160:pumped
3087:farads
2562:cycles
2556:cycles
2550:cycles
2544:cycles
2538:cycles
2532:cycles
2161:again.
2138:charge
2122:equal.
2032:
2017:
1985:Mostek
1910:, the
1833:Nvidia
1797:Kioxia
1685:and a
1539:(1971)
1521:(1962)
1515:(1962)
1503:(1957)
1497:(1949)
1491:(1932)
1480:(1725)
1474:(1725)
1468:(1725)
1341:HD DVD
1301:CD-ROM
1257:(CDDA)
1183:MiniDV
902:(SSHD)
884:(SSS)
870:EEPROM
818:(2009)
807:(1952)
801:(1951)
795:(1947)
413:Backup
6912:Lists
6860:RDRAM
6840:GDDR7
6835:GDDR6
6830:GDDR5
6825:GDDR4
6820:GDDR3
6815:GDDR2
6805:SGRAM
6800:MDRAM
6767:HBM3E
6752:HBM2E
6732:eDRAM
6720:LPDDR
6688:SDRAM
6580:(PDF)
6532:(PDF)
6521:(PDF)
6318:(PDF)
6285:(PDF)
6128:(PDF)
6109:(PDF)
6102:(PDF)
6050:(PDF)
6039:(PDF)
5956:(PDF)
5949:(PDF)
5932:(PDF)
5925:(PDF)
5880:8 May
5751:S2CID
5707:(PDF)
5696:(PDF)
5634:(PDF)
5627:(PDF)
5610:(PDF)
5603:(PDF)
5584:8 May
5578:(PDF)
5567:(PDF)
5495:(PDF)
5484:(PDF)
5459:(PDF)
5448:(PDF)
5207:(PDF)
5153:(PDF)
5146:(PDF)
4907:8 May
4792:(PDF)
4694:JEDEC
4630:GDDR6
4622:GDDR5
4618:GDDR4
4614:GDDR3
4610:GDDR2
4602:SDRAM
4521:MoSys
4513:MoSys
4409:RDRAM
4006:Intel
3612:eDRAM
3524:Apple
3500:64 ms
3441:from
3354:noise
3279:A-RAM
3275:Z-RAM
3202:Hynix
2565:time
2527:Fast
2201:JEDEC
1974:masks
1965:Intel
1805:DIMMs
1716:(vs.
1401:ECRAM
1381:CBRAM
1316:DVD+R
1276:CD-RW
1213:D-VHS
1208:VHS-C
1203:S-VHS
1144:(DDS)
1067:ReRAM
1062:FeRAM
1055:NVRAM
1041:CBRAM
998:NVRAM
896:(SSD)
865:EPROM
822:Z-RAM
816:T-RAM
748:(CAM)
736:ReRAM
702:RDRAM
682:LPDDR
677:SGRAM
672:SDRAM
667:eDRAM
101:types
6903:CAMM
6893:DIMM
6888:SIMM
6810:GDDR
6795:WRAM
6790:VRAM
6757:HBM3
6747:HBM2
6713:DDR5
6708:DDR4
6703:DDR3
6698:DDR2
6464:ISBN
6436:ISBN
6326:2017
6248:2017
6211:ISBN
6085:2018
6058:2015
6017:ISSN
5882:2018
5741:ISBN
5586:2018
5391:2019
5359:2019
5246:ISBN
5174:link
5129:2018
5024:2019
4976:2023
4909:2018
4873:ISBN
4682:and
4650:CMOS
4632:and
4573:GDDR
4537:SRAM
4472:VRAM
4454:and
4392:DDR3
4388:DDR2
4378:The
4309:The
4300:Mode
4075:and
4071:The
3727:and
3563:DDR3
3431:soft
3419:and
3287:CNRS
2559:time
2553:time
2547:time
2541:time
2535:time
2521:Fast
2515:Fast
1864:The
1858:NMOS
1837:HBM2
1791:and
1749:and
1664:DRAM
1649:VRAM
1627:128
1391:NRAM
1363:WORM
1271:CD-R
1025:MRAM
860:PROM
855:MROM
757:VRAM
741:QRAM
724:SRAM
712:GDDR
662:DRAM
558:RAID
208:Data
97:and
59:and
21:Dram
6742:HBM
6584:hdl
6553:doi
6305:hdl
6297:doi
6009:doi
5812:EDN
5733:doi
5042:IBM
5016:IBM
4684:Wii
4667:An
4599:DDR
4527:of
4380:die
4240:Row
4111:CAS
4106:RAS
4087:or
4077:CAS
4073:RAS
4029:CAS
4025:RAS
4021:CAS
4017:CAS
3973:CAS
3969:CAS
3965:CAS
3955:CAS
3945:CAC
3938:CAS
3934:CAS
3930:CAS
3926:CAS
3911:CAC
3904:CAS
3900:RAS
3880:RAS
3876:CAS
3872:RAS
3868:RAS
3864:CAS
3852:RAS
3848:CAS
3844:RAS
3840:CAS
3816:CAS
3812:RAS
3804:RAS
3797:CAS
3793:RAS
3783:RAS
3765:RAS
3761:RAS
3757:CAS
3753:RAS
3729:CAS
3725:RAS
3715:CAS
3711:CAS
3701:CAS
3697:CAS
3691:RAS
3687:RAS
3683:RAS
3526:'s
3283:UGR
3191:or
3168:CCP
3164:CCP
2983:WTW
2974:WTR
2965:WTP
2947:RTW
2938:RTR
2929:RTP
2920:RRD
2898:RFC
2889:REF
2880:RCD
2871:RAS
2862:PTP
2816:600
2808:CAC
2787:RCD
2779:RAC
2728:RAS
2630:RCD
2619:CAC
2475:RAS
2461:RCD
2420:CAS
2401:CAC
2321:RAS
2302:RCD
2283:RAC
1936:bit
1767:in
1675:bit
1662:or
1629:KiB
1584:die
1311:DVD
1198:VHS
1015:PCM
968:SxS
843:ROM
717:HBM
707:DDR
638:RAM
6951::
6549:46
6547:.
6543:.
6523:.
6383:.
6313:.
6303:.
6293:50
6291:.
6287:.
6265:.
6234:.
6181:^
6075:.
6045:.
6041:.
6015:.
6007:.
5997:47
5995:.
5964:^
5927:.
5898:.
5868:.
5851:.
5810:.
5780:.
5749:.
5739:.
5698:.
5569:.
5510:^
5486:.
5450:.
5415:.
5381:.
5375:.
5349:.
5330:41
5328:.
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