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254:, while similar from a logical perspective to ranks, are implemented quite differently in physical hardware. Banks are sub-units inside a single memory chip, while ranks are sub-units composed of a subset of the chips on a module. Similar to chip select, banks are selected by bank select bits, which are part of the memory interface.
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RAM modules are 'keyed' by indentations on the sides, and along the bottom of the module. This designates the technology, and classification of the modules, for instance whether it is DDR2, or DDR3, and whether it is suitable for desktops, or for servers. Keying was designed to make it difficult to
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that make up each module, or module of RAM. The most important measurement of a chip is its density, measured in bits. Because memory bus width is usually larger than the number of chips, most chips are designed to have width, meaning that they are divided into equal parts internally, and when one
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common in SDR and DDR1–4 families of RAM. A memory of width of 72 would indicate an ECC module, with 8 extra bits in the data width for the error-correcting code syndrome. (The ECC syndrome allows single-bit errors to be corrected). The memory depth is the total memory capacity in bits divided by
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As the next section of this article will cover the logical architecture, which covers the logical structure spanning every populated slot in a system, the physical features of the slots themselves become important. By consulting the documentation of your motherboard, or reading the labels on the
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MT47H128M16 chips with the organization 128 Mib × 16, meaning 128 Mi memory depth and 16-bit-wide data bus per chip; if the module has 8 of these chips on each side of the board, there would be a total of 16 chips × 16-bit-wide data = 256 total bits width of data. For a 64-bit-wide memory data
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Memory geometry describes the logical configuration of a RAM module, but consumers will always find it easiest to grasp the physical configuration. Much of the confusion surrounding memory geometry occurs when the physical configuration obfuscates the logical configuration. The first defining
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address "depth" is called up, instead of returning just one value, more than one value is returned. In addition to the depth, a second addressing dimension has been added at the chip level, banks. Banks allow one bank to be available, while another bank is unavailable because it is
182:). With AMD's release of the Opteron, which integrated the memory controller into the CPU, NUMA systems that share more than one memory controller in a single system have become common in applications that require the power of more than the common desktop.
218:(CS) in low-level addressing. For example, a memory module with 8 chips on each side, with each chip having an 8-bit-wide data bus, would have one rank for each side for a total of 2 ranks, if we define a rank to be 64 bits wide. A module composed of
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board itself, you can determine the underlying logical structure of the slots. When there is more than one slot, they are numbered, and when there is more than one channel, the different slots are separated in that way as well – usually color-coded.
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module could be composed of four 8-bit wide (×8) chips. As noted in the memory channel part, one physical module can be made up of one or more logical ranks. If that 32-bit SIMM were composed of eight 8-bit chips the SIMM would have two ranks.
93:. Memory geometry is of concern to consumers upgrading their computers, since older memory controllers may not be compatible with later products. Memory geometry terminology can be confusing because of the number of overlapping terms.
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list the configurations they support: "256-Mib, 512-Mib, and 1-Gib DDR2 technologies for ×8 and ×16 devices", "four ranks for all DDR2 devices up to 512-Mibit density", "eight ranks for 1-Gibit DDR2 devices". As an example, take an
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were released, which allowed combining multiple computers that each had their own memory controller such that the software running on them could use I/O devices, memory, and CPU of all participating systems as if they were one unit
204:. Module capacity is equal to the product of the number of ranks and the rank density, and where the rank density is the product of rank depth and rank width. The standard format for expressing this specification is (rank depth)
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The geometry of a memory system can be thought of as a multi-dimensional array. Each dimension has its own characteristics and physical realization. For example, the number of data pins on a memory module is one dimension.
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Memory depth is the memory density divided by memory width. Example: for a memory chip with 128 Mib capacity and 8-bit wide data bus, it can be specified as: 16 Meg × 8. Sometimes the "Mi" is dropped, as in 16×8.
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install incorrect modules in a system (but there are more requirements than are embodied in keys). It is important to make sure that the keying of the module matches the key of the slot it is intended to occupy.
243:. Kingston describes each module as composed of 16 "64M×8-bit" chips with each chip having an 8-bit-wide data bus. 16 × 8 equals 128, therefore, each module has two ranks of 64 bits each. So, from the
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are populated. Modules with the number of RAM chips equal to some power of two do not support memory error detection or correction. If there are extra RAM chips (between powers of two), these are used for
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This is the highest level. A typical computer has only a single memory controller with only one or two channels. The logical features section described NUMA configurations, which can take the form of a
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Additional, non-memory chips on the module may be an indication that it was designed for high capacity memory systems for servers, and that the module may be incompatible with mass-market systems.
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Some measurements of modules are size, width, speed, and latency. A memory module consists of a multiple of the memory chips to equal the desired module width. So a 32-bit
189:. It is usually important that, for each module in any one channel, there is a logically identical module in the same location on each of the other populated channels.
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The memory width specifies the data width of the memory module interface in bits. For example, 64 would indicate a 64-bit data width, as is found on non-ECC
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A memory channel is made up of ranks. Physically a memory channel with just one memory module might present itself as having one or more logical ranks.
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memory width. Sometimes the memory depth is indicated in units of Meg (2), as in 32×64 or 64×64, indicating 32 Mi depth and 64 Mi depth respectively.
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interface, this equates to having 4 ranks, where each rank can be selected by a 2-bit chip select signal. Memory controllers such as the
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The other physical characteristics, determined by physical examination, are the number of memory chips, and whether both sides of the
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Example: a chip with the same capacity and memory width as above but constructed with 4 banks would be specified as 4 Mi × 8 × 4.
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point of view there are four 1 GB modules. At a higher logical level, the MCH also sees two channels, each with four ranks.
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The lowest form of organization covered by memory geometry, sometimes called "memory device". These are the component
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Channels are the highest-level structure at the local memory controller level. Modern computers can have
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Various methods of specifying memory geometry can be encountered, giving different types of information.
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are sub-units of a memory module that share the same address and data buses and are selected by
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can have a two-channel memory controller, giving the system a total of four memory channels.
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DIMM with heat-spreader, DDR2 DIMM without heat-spreader, SO-DIMM DDR2, DDR, SO-DIMM DDR
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KHX6400D2/1G memory modules, where each module has a capacity of 1
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This is the total memory capacity of the chip. Example: 128 Mib.
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of memory controllers. For example, each socket of a two-socket
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feature of RAM is form factor. RAM modules can be in compact
385:(memory depth per bank) × (memory width) × (number of banks)
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122:form for space constrained applications like
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16:Internal structure of random-access memory
69:Learn how and when to remove this message
175:cache-coherent non-uniform memory access
142:format, which is used in most desktops.
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32:This article includes a list of general
582:(data sheet), Value RAM, archived from
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208:× (rank width) × (number of ranks).
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89:describes the internal structure of
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38:it lacks sufficient corresponding
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305:Multi-channel memory architecture
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476:, Kingston, 2007, archived from
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187:two, three or even more channels
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376:(memory depth) × (memory width)
346:(memory depth) × (memory width)
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196:space in a module measured in
173:In the 1990s, computers using
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409:Dynamic random access memory
235:memory controller with four
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200:, or – more generally – in
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538:, RAMpedia, archived from
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444:Dual-channel architecture
404:List of device bandwidths
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258:Hierarchy of organization
333:Memory geometry notation
81:In the design of modern
362:
313:Controller organization
192:Module capacity is the
53:more precise citations.
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625:Computing terminology
527:(FAQ), IXT labs, 2006
470:Ultimate Memory Guide
449:Page address register
108:
414:Random-access memory
91:random-access memory
609:(data sheet), Intel
503:Kingston Technology
419:Memory organisation
180:single system image
138:computers, and in
132:embedded computers
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220:Micron Technology
136:small form factor
101:Physical features
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439:Double-sided RAM
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45:Please help to
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496:"KHX6400D2/1G"
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284:Main article:
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147:memory "stick"
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59:September 2010
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429:Memory bank
263:Memory chip
216:chip select
51:introducing
619:Categories
593:2010-08-05
568:, PC guide
455:References
357:non-parity
303:See also:
274:refreshing
34:references
553:RAM guide
525:Mainboard
225:Intel 945
194:aggregate
109:Top L-R,
83:computers
549:"Part 1"
514:External
393:See also
237:Kingston
128:printers
562:"Banks"
320:network
228:Chipset
124:laptops
120:SO-DIMM
47:improve
603:307502
341:Module
134:, and
36:, but
607:(PDF)
587:(PDF)
580:(PDF)
521:"RAM"
499:(PDF)
481:(PDF)
474:(PDF)
352:DIMMs
252:banks
212:Ranks
202:words
198:bytes
399:DIMM
363:Chip
355:the
292:SIMM
233:i945
206:Mbit
140:DIMM
111:DDR2
566:RAM
535:FAQ
324:AMD
269:ICs
245:MCH
241:GiB
152:ECC
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327:K8
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