3001:---<___>~~~<XXXXXXXX___X_______X___X___ (If a read) ___ _______________ _______ ___ ___ C/BE# ---<___X_______________X_______X___X___ (Must always be valid) _______________ | ___ | | | IRDY# x \_______/ x \___________ ___________________ | | | | TRDY# x x \___________________ ___________ | | | | DEVSEL# \___________________________ ___ | | | | FRAME# \___________________________________ _ _ _ _ _ |_ _ |_ |_ |_ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ 0 1 2 3 4 5 6 7 8 9
1979:
3232:| | | ___ IRDY# ^^^^^^^\_______________________/ _____ | | | | _______ TRDY# ^^^^^^^ \______________/ ________________ | ___ STOP# ^^^^^^^ | | | \_______/ | | | | ___ DEVSEL# ^^^^^^^\_______________________/ ___ | | | | ___ FRAME# \_______________________/ ^^^^ _ _ _ |_ |_ |_ |_ _ _ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ 0 1 2 3 4 5 6 7 8
1912:
872:
2035:
2908:
2007:
3225:| | | | ___ IRDY# ^^^^\___________________/ ^^^^^ ___ _____ | | | | ___ TRDY# ^^^^ \______________/ ^^^^^ ___ | | | | ___ DEVSEL# ^^^^\___________________/ ^^^^^ ___ | | | ___ FRAME# \___________________/ | ^^^^\____ _ _ _ |_ |_ |_ |_ _ _ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ 0 1 2 3 4 5 6 7 8
3245:
device is driving the AD lines computes even parity over them and the C/BE# lines, and sends that out the PAR line one cycle later. All access rules and turnaround cycles for the AD bus apply to the PAR line, just one cycle later. The device listening on the AD bus checks the received parity and asserts the PERR# (parity error) line one cycle after that. This generally generates a processor interrupt, and the processor can search the PCI bus for the device which detected the error.
896:, but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side. Side A refers to the 'solder side' and side B refers to the 'component side': if the card is held with the connector pointing down, a view of side A will have the backplate on the right, whereas a view of side B will have the backplate on the left. The pinout of B and A sides are as follows, looking down into the motherboard connector (pins A1 and B1 are closest to backplate).
1991:
736:-enabled x86 systems. Interrupt lines are not wired in parallel as are the other PCI bus lines. The positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the one after that. Single-function devices usually use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines. This alleviates a common problem with sharing interrupts.
2976:. In case of a write, the asserted signals indicate which of the four bytes on the AD bus are to be written to the addressed location. In the case of a read, they indicate which bytes the initiator is interested in. For reads, it is always legal to ignore the byte-enable signals and simply return all 32 bits; cacheable memory resources are required to always return 32 valid bits. The byte enables are mainly useful for I/O space accesses where reads have side effects.
1904:
5271:
3218:
As the initiator is also ready, a data transfer occurs. This repeats for three more cycles, but before the last one (clock edge 5), the master deasserts FRAME#, indicating that this is the end. On clock edge 6, the AD bus and FRAME# are undriven (turnaround cycle) and the other control lines are driven high for 1 cycle. On clock edge 7, another initiator can start a different transaction. This is also the turnaround cycle for the other control lines.
52:
761:. In this system, a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts. It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message
439:
424:
2723:
61:
3388:
3214:
IRDY# ^^^^^^^^\______________/ ^^^^^ | | | | ___ TRDY# ^^^^^^^^\______________/ ^^^^^ | | | | ___ DEVSEL# ^^^^^^^^\______________/ ^^^^^ ___ | | | ___ FRAME# \_______________/ | ^^^^\____ _ _ |_ |_ |_ |_ _ _ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ 0 1 2 3 4 5 6 7
3042:, when no target responds with DEVSEL#. Obviously, it is pointless to wait for TRDY# in such a case. However, even in this case, the master must assert IRDY# for at least one cycle after deasserting FRAME#. (Commonly, a master will assert IRDY# before receiving DEVSEL#, so it must simply hold IRDY# asserted for one cycle longer.) This is to ensure that bus turnaround timing rules are obeyed on the FRAME# line.
784:
2015:
2027:
2671:
internally (if it has room) and signal completion of the write before the forwarded write has completed. Or, indeed, before it has begun. Such "sent but not yet arrived" writes are referred to as "posted writes", by analogy with a postal mail message. Although they offer great opportunity for performance gains, the rules governing what is permissible are somewhat intricate.
2944:
___ ___ _______________ C/BE# -------<___X___X_______________ (DAC, then actual command) ___________________________ DEVSEL# \___\___\___\___ Fast Med Slow _ _ _ _ _ _ _ _ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ 0 1 2 3 4 5 6
3005:
and a data transfer takes place (as indicated by the vertical lines). For clock 6, the target is ready to transfer, but the initiator is not. On clock 7, the initiator becomes ready, and data is transferred. For clocks 8 and 9, both sides remain ready to transfer data, and data is transferred at the maximum possible rate (32 bits per clock cycle).
2340:. The direction of the data phases may be from initiator to target (write transaction) or vice versa (read transaction), but all of the data phases must be in the same direction. Either party may pause or halt the data phases at any point. (One common example is a low-performance PCI device that does not support
407:, lane-based architecture. PCI's heyday in the desktop computer market was approximately 1995 to 2005. PCI and PCI-X have become obsolete for most purposes and has largely disappeared from many other modern motherboards since 2013; however they are still common on some modern desktops as of 2020 for the purposes of
2127:: Type I, Type II, and Type III cards. The card connector used for each type include: Type I and II use a 100-pin stacking connector, while Type III uses a 124-pin edge connector, i.e. the connector for Types I and II differs from that for Type III, where the connector is on the edge of a card, like with a
3282:
Additional timing constraints may come from the need to turn around are the target control lines, particularly DEVSEL#. The target deasserts DEVSEL#, driving it high, in the cycle following the final data phase, which in the case of back-to-back transactions is the first cycle of the address phase.
3231:
0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ ___ ___ ___ ___ ___ AD ---<___>---<___X___X___X___XXXX>---- ___ _______ ___ ___ ___ ___ C/BE# ---<___X_______X___X___X___X___>---- |
3224:
0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ ___ ___ ___ ___ ___ AD ---<___>---<___X___X___X___>---<___> ___ _______ ___ ___ ___ C/BE# ---<___X_______X___X___X___>---<___> ___
3034:
The initiator can mark any data phase as the final one in a transaction by deasserting FRAME# at the same time as it asserts IRDY#. The cycle after the target asserts TRDY#, the final data transfer is complete, both sides deassert their respective RDY# signals, and the bus is idle again. The master
3025:
Either side may request that a burst end after the current data phase. Simple PCI devices that do not support multi-word bursts will always request this immediately. Even devices that do support bursts will have some limit on the maximum length they can support, such as the end of their addressable
2993:
Once one of the participants asserts its ready signal, it may not become un-ready or otherwise alter its control signals until the end of the data phase. The data recipient must latch the AD bus each cycle until it sees both IRDY# and TRDY# asserted, which marks the end of the current data phase and
2943:
_ 0_ 1_ 2_ 3_ 4_ 5_ 6_ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ ___ GNT# \___/XXXXXXXXXXXXXXXXXXXXXXX _______ FRAME# \_______________________ ___ ___ AD -------<___X___>--------------- (Low, then high bits)
2783:
PCI bus transactions are controlled by five main control signals, two driven by the initiator of a transaction (FRAME# and IRDY#), and three driven by the target (DEVSEL#, TRDY#, and STOP#). There are two additional arbitration signals (REQ# and GNT#) that are used to obtain permission to initiate a
2393:
provides access to 256 bytes of special configuration registers per PCI device. Each PCI slot gets its own configuration space address range. The registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators. When a computer is first turned
1844:
The PCI SIG strongly encourages 3.3 V PCI signaling, requiring support for it since standard revision 2.3, but most PC motherboards use the 5 V variant. Thus, while many currently available PCI cards support both, and have two key notches to indicate that, there are still a large number of
3338:
If the initiator sees DEVSEL# asserted without ACK64#, it performs 32-bit data phases. The data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase. Typically, the initiator drives all 64 bits of data before
3322:
Starting from revision 2.1, the PCI specification includes optional 64-bit support. This is provided via an extended connector which provides the 64-bit bus extensions AD, C/BE#, and PAR64, and a number of additional power and ground pins. The 64-bit PCI connector can be distinguished from a 32-bit
3264:
Due to the need for a turnaround cycle between different devices driving PCI bus signals, in general it is necessary to have an idle cycle between PCI bus transactions. However, in some circumstances it is permitted to skip this idle cycle, going directly from the final cycle of one transfer (IRDY#
3244:
The PCI bus detects parity errors, but does not attempt to correct them by retrying operations; it is purely a failure indication. Due to this, there is no need to detect the parity error before it has happened, and the PCI bus actually detects it a few cycles later. During a data phase, whichever
3217:
On clock edge 1, the initiator starts a transaction by driving an address, command, and asserting FRAME# The other signals are idle (indicated by ^^^), pulled high by the motherboard's pull-up resistors. That might be their turnaround cycle. On cycle 2, the target asserts both DEVSEL# and TRDY#.
3004:
This continues the address cycle illustrated above, assuming a single address cycle with medium DEVSEL, so the target responds in time for clock 3. However, at that time, neither side is ready to transfer data. For clock 4, the initiator is ready, but the target is not. On clock 5, both are ready,
2828:
The combination of this turnaround cycle and the requirement to drive a control line high for one cycle before ceasing to drive it means that each of the main control lines must be high for a minimum of two cycles when changing owners. The PCI bus protocol is designed so this is rarely a limitation;
2670:
Generally, when a bus bridge sees a transaction on one bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready. One notable exception occurs in the case of memory writes. Here, the bridge may record the write data
2453:
This performs a read from I/O space. All 32 bits of the read address are provided, so that a device may (for compatibility reasons) implement less than 4 bytes worth of I/O registers. If the byte enables request data not within the address range supported by the PCI device (e.g. a 4-byte read from a
363:
variant as well. These have one locating notch in the card. Version 2.0 of the PCI standard introduced 3.3 V slots, physically distinguished by a flipped physical connector to prevent accidental insertion of 5 V cards. Universal cards, which can operate on either voltage, have two notches.
3375:
In the case of a write to data that was clean in the cache, the cache would only have to invalidate its copy and would assert SDONE as soon as this was established. However, if the cache contained dirty data, the cache would have to write it back before the access could proceed. so it would assert
3190:
Cache line toggle and cache line wrap modes are two forms of critical-word-first cache line fetching. Toggle mode XORs the supplied address with an incrementing counter. This is the native order for Intel 486 and
Pentium processors. It has the advantage that it is not necessary to know the cache
3058:
If the target asserts STOP# and TRDY# at the same time, this indicates that the target wishes this to be the last data phase. For example, a target that does not support burst transfers will always do this to force single-word PCI transactions. This is the most efficient way for a target to end a
2939:
To allow 64-bit addressing, a master will present the address over two consecutive cycles. First, it sends the low-order address bits with a special "dual-cycle address" command on the C/BE#. On the following cycle, it sends the high-order address bits and the actual command. Dual-address cycles
2845:
may initiate a transaction with any other device. To ensure that only one transaction is initiated at a time, each master must first wait for a bus grant signal, GNT#, from an arbiter located on the motherboard. Each device has a separate request line REQ# that requests the bus, but the arbiter may
2557:
When accessing a memory address that requires more than 32 bits to represent, the address phase begins with this command and the low 32 bits of the address, followed by a second cycle with the actual command and the high 32 bits of the address. PCI targets that do not support 64-bit addressing may
2528:
Configuration space accesses often have a few cycles of delay to allow the IDSEL lines to stabilize, which makes them slower than other forms of access. Also, a configuration space access requires a multi-step operation rather than a single machine instruction. Thus, it is best to avoid them during
2444:
This cycle is a special broadcast write of system events that PCI card may be interested in. The address field of a special cycle is ignored, but it is followed by a data phase containing a payload message. The currently defined messages announce that the processor is stopping for some reason (e.g.
2397:
If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation. In case of reads, it is customary to supply all-ones for the read data value (0xFFFFFFFF) in this case. PCI devices therefore generally attempt to avoid
3330:
To initiate a 64-bit transaction, the initiator drives the starting address on the AD bus and asserts REQ64# at the same time as FRAME#. If the selected target can support a 64-bit transfer for this transaction, it replies by asserting ACK64# at the same time as DEVSEL#. A target may decide on a
3121:
For memory space accesses, the words in a burst may be accessed in several orders. The unnecessary low-order address bits AD are used to convey the initiator's requested order. A target which does not support a particular order must terminate the burst after the first word. Some of these orders
2952:
Addresses for PCI configuration space access use special decoding. For these, the low-order address lines specify the offset of the desired PCI configuration register, and the high-order address lines are ignored. Instead, an additional address signal, the IDSEL input, must be high before a device
2816:
All PCI bus signals are sampled on the rising edge of the clock. Signals nominally change on the falling edge of the clock, giving each PCI device approximately one half a clock cycle to decide how to respond to the signals it observed on the rising edge, and one half a clock cycle to transmit its
883:
Typical PCI cards have either one or two key notches, depending on their signaling voltage. Cards requiring 3.3 volts have a notch 56.21 mm from the card backplate; those requiring 5 volts have a notch 104.41 mm from the backplate. This allows cards to be fitted only into slots
718:
How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the
Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the
3334:
If REQ64# is asserted during the address phase, the initiator also drives the high 32 bits of the address and a copy of the bus command on the high half of the bus. If the address requires 64 bits, a dual address cycle is still required, but the high half of the bus carries the upper half of the
2575:
This command is identical to a generic memory write, but comes with the guarantee that one or more whole cache lines will be written, with all byte selects enabled. This is an optimization for write-back caches snooping the bus. Normally, a write-back cache holding dirty data must interrupt the
2485:
This performs a read cycle from memory space. Because the smallest memory space a PCI device is permitted to implement is 16 bytes, the two least significant bits of the address are not needed during the address phase; equivalent information will arrive during the data phases in the form of byte
3213:
0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ ___ ___ ___ ___ ___ AD ---<___X___X___X___X___>---<___> ___ ___ ___ ___ ___ C/BE# ---<___X___X___X___X___>---<___> | | | | ___
3016:
A target that supports fast DEVSEL could in theory begin responding to a read on the cycle after the address is presented. This cycle is, however, reserved for AD bus turnaround. Thus, a target may not drive the AD bus (and thus may not assert TRDY#) on the second cycle of a transaction. Most
2633:
If the target has a limit on the number of delayed transactions that it can record internally (simple targets may impose a limit of 1), it will force those transactions to retry without recording them. They will be dealt with when the current delayed transaction is completed. If two initiators
3108:
If the initiator has already asserted IRDY# (without deasserting FRAME#) by the time it observes the target's STOP#, it is committed to an additional data phase. The target must wait through an additional data phase without data, holding STOP# asserted without TRDY#, before the transaction can
2873:
Each other device examines the address and command and decides whether to respond as the target by asserting DEVSEL#. A device must respond by asserting DEVSEL# within 3 cycles. Devices that promise to respond within 1 or 2 cycles are said to have "fast DEVSEL" or "medium DEVSEL", respectively.
2363:
bytes are to be considered significant. In particular, a write must affect only the enabled bytes in the target PCI device. They are of little importance for memory reads, but I/O reads might have side effects. The PCI standard explicitly allows a data phase with no bytes enabled, which must
3326:
Memory transactions between 64-bit devices may use all 64 bits to double the data transfer rate. Non-memory transactions (including configuration and I/O space accesses) may not use the 64-bit extension. During a 64-bit burst, burst addressing works just as in a 32-bit transfer, but the
3286:
One case where this problem cannot arise is if the initiator knows somehow (presumably because the addresses share sufficient high-order bits) that the second transfer is addressed to the same target as the prior one. In that case, it may perform back-to-back transactions. All PCI targets must
3050:
The target requests the initiator end a burst by asserting STOP#. The initiator will then end the transaction by deasserting FRAME# at the next legal opportunity; if it wishes to transfer more data, it will continue in a separate transaction. There are several ways for the target to do this:
2927:
On the rising edge of clock 0, the initiator observes FRAME# and IRDY# both high, and GNT# low, so it drives the address, command, and asserts FRAME# in time for the rising edge of clock 1. Targets latch the address and begin decoding it. They may respond with DEVSEL# in time for clock 2 (fast
2853:
The arbiter may also provide GNT# at any time, including during another master's transaction. During a transaction, either FRAME# or IRDY# or both are asserted; when both are deasserted, the bus is idle. A device may initiate a transaction at any time that GNT# is asserted and the bus is idle.
2427:
This is a special form of read cycle implicitly addressed to the interrupt controller, which returns an interrupt vector. The 32-bit address field is ignored. One possible implementation is to generate an interrupt acknowledge cycle on an ISA bus using a PCI/ISA bus bridge. This command is for
1848:
The M66EN pin is an additional ground on 5 V PCI buses found in most PC motherboards. Cards and motherboards that do not support 66 MHz operation also ground this pin. If all participants support 66 MHz operation, a pull-up resistor on the motherboard raises this signal high and
2412:
There are 16 possible 4-bit command codes, and 12 of them are assigned. With the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read (data sent from target to initiator) or a write (data sent from an
2355:
64-bit addressing is done using a two-stage address phase. The initiator broadcasts the low 32 address bits, accompanied by a special "dual address cycle" command code. Devices that do not support 64-bit addressing can simply not respond to that command code. The next cycle, the initiator
1840:
IOPWR is +3.3 V or +5 V, depending on the backplane. The slots also have a ridge in one of two places which prevents insertion of cards that do not have the corresponding key notch, indicating support for that voltage standard. Universal cards have both key notches and use IOPWR to
1919:
Most 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus clock rate will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology. For example, when a PCI 2.3, 66-MHz peripheral is installed into a PCI-X bus capable of
2687:
Write transactions to consecutive addresses may be combined into a longer burst write, as long as the order of the accesses in the burst is the same as the order of the original writes. It is permissible to insert extra data phases with all byte enables turned off if the writes are almost
2520:
This is similar to an I/O read, but reads from PCI configuration space. A device must respond only if the low 11 bits of the address specify a function and register that it implements, and if the special IDSEL signal is asserted. It must ignore the high 21 bits. Burst reads (using linear
2356:
transmits the high 32 address bits, plus the real command code. The transaction operates identically from that point on. To ensure compatibility with 32-bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order address bits are all zero.
2057:. The standard size for Mini PCI cards is approximately a quarter of their full-sized counterparts. There is no access to the card from outside the case, unlike desktop PCI cards with brackets carrying connectors. This limits the kinds of functions a Mini PCI card can perform.
1920:
133 MHz, the entire bus backplane will be limited to 66 MHz. To get around this limitation, many motherboards have two or more PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals, and the other bus intended for general-purpose peripherals.
3371:
The cache would watch all memory accesses, without asserting DEVSEL#. If it noticed an access that might be cached, it would drive SDONE low (snoop not done). A coherence-supporting target would avoid completing a data phase (asserting TRDY#) until it observed SDONE high.
1930:
Installing a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card edge connector not connected and overhanging. This requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge
415:, where many specialized expansion cards, used here, never transitioned to PCI Express, just as with some ISA cards. Many kinds of devices formerly available on PCI expansion cards are now commonly integrated onto motherboards or available in USB and PCI Express versions.
2881:
the address on the first cycle; the initiator is required to remove the address and command from the bus on the following cycle, even before receiving a DEVSEL# response. The additional time is available only for interpreting the address and command after it is captured.
2637:
A target abandons a delayed transaction when a retry succeeds in delivering the buffered result, the bus is reset, or when 2=32768 clock cycles (approximately 1 ms) elapse without seeing a retry. The latter should never happen in normal operation, but it prevents a
526:, and the adaptation of PCI signaling to other form factors. Both PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards. These revisions were used on server hardware but consumer PC hardware remained nearly all 32-bit, 33 MHz and 5 volt.
2347:
Any PCI device may initiate a transaction. First, it must request permission from a PCI bus arbiter on the motherboard. The arbiter grants permission to one of the requesting devices. The initiator begins the address phase by broadcasting a 32-bit address plus a
2696:
Multiple writes to disjoint portions of the same word may be merged into a single write with multiple byte enables asserted. In this case, writes that were presented to the bus bridge in a particular order are merged so they occur at the same time when forwarded.
3000:
0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ 9_ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ ___ _______ ___ ___ ___ AD ---<___XXXXXXXXX_______XXXXX___X___X___ (If a write) ___ ___ _______ ___ ___ AD
2621:(for memory writes) and delayed transactions (for other writes and all reads). In a delayed transaction, the target records the transaction (including the write data) internally and aborts (asserts STOP# rather than TRDY#) the first data phase. The initiator
3194:
PCI version 2.1 obsoleted toggle mode and added the cache line wrap mode, where fetching proceeds linearly, wrapping around at the end of each cache line. When one cache line is completely fetched, fetching jumps to the starting offset in the next cache line.
2897:
and it is customary for PCI bus bridges to return all-ones data (0xFFFFFFFF) in this case. PCI devices, therefore, are generally designed to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.
2603:
Additionally, as of revision 2.1, all initiators capable of bursting more than two data phases must implement a programmable latency timer. The timer starts counting clock cycles when a transaction starts (initiator asserts FRAME#). If the timer has expired
2119:
Mini PCI cards have a 2 W maximum power consumption, which limits the functionality that can be implemented in this form factor. They also are required to support the CLKRUN# PCI signal used to start and stop the PCI clock for power management purposes.
2524:
Unlike I/O space, standard PCI configuration registers are defined so that reads never disturb the state of the device. It is possible for a device to have configuration space registers beyond the standard 64 bytes which have read side effects, but this is
3376:
SBO# when raising SDONE. This would signal the active target to assert STOP# rather than TRDY#, causing the initiator to disconnect and retry the operation later. In the meantime, the cache would arbitrate for the bus and write its data back to memory.
3094:
It will always take at least one cycle for the initiator to notice a target-initiated disconnection request and respond by deasserting FRAME#. There are two sub-cases, which take the same amount of time, but one requires an additional data phase:
713:
devices to share the PCI bus fairly. "Fair" in this case means that devices will not use such a large portion of the available PCI bus bandwidth that other devices are not able to get needed work done. Note, this does not apply to PCI Express.
3248:
The PERR# line is only used during data phases, once a target has been selected. If a parity error is detected during an address phase (or the data phase of a
Special Cycle), the devices which observe it assert the SERR# (System error) line.
862:
The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master.
2608:
the arbiter has removed GNT#, then the initiator must terminate the transaction at the next legal opportunity. This is usually the next data phase, but Memory Write and
Invalidate transactions must continue to the end of the cache line.
2928:
DEVSEL), 3 (medium) or 4 (slow). Subtractive decode devices, seeing no other response by clock 4, may respond on clock 5. If the master does not see a response by clock 5, it will terminate the transaction and remove FRAME# on clock 6.
3201:
PCI also supports burst access to I/O and configuration space, but only linear mode is supported. (This is rarely used, and may be buggy in some devices; they may not support it, but not properly force single-word access either.)
3345:
The PAR64 line operates just like the PAR line, but provides even parity over AD and C/BE#. It is only valid for address phases if REQ64# is asserted. PAR64 is only valid for data phases if both REQ64# and ACK64# are asserted.
2629:
A device may be the target of other transactions while completing one delayed transaction; it must remember the transaction type, address, byte selects and (if a write) data value, and only complete the correct transaction.
2576:
write operation long enough to write its own dirty data first. If the write is performed using this command, the data to be written back is guaranteed to be irrelevant, and may simply be invalidated in the write-back cache.
3327:
address is incremented twice per data phase. The starting address must be 64-bit aligned; i.e. AD2 must be 0. The data corresponding to the intervening addresses (with AD2 = 1) is carried on the upper half of the AD bus.
3065:
If the target asserts STOP# without asserting TRDY#, this indicates that the target wishes to stop without transferring data. STOP# is considered equivalent to TRDY# for the purpose of ending a data phase, but no data is
682:
The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.
2824:
must elapse between the time the one device stops driving the signal and the other device starts. Without this, there might be a period when both devices were driving the signal, which would interfere with bus operation.
2143:, phone-line interface). Type II cards have RJ11 and RJ45 mounted connectors. These cards must be located at the edge of the computer or docking station so that the RJ11 and RJ45 ports can be mounted for external access.
457:. A team of primarily IAL engineers defined the architecture and developed a proof of concept chipset and platform (Saturn) partnering with teams in the company's desktop PC systems and core logic product organizations.
2625:
retry exactly the same transaction later. In the interim, the target internally performs the transaction, and waits for the retried transaction. When the retried transaction is seen, the buffered result is delivered.
2566:
This command is identical to a generic memory read, but includes the hint that the read will continue to the end of the cache line. A target is always permitted to consider this a synonym for a generic memory
2849:
The arbiter may remove GNT# at any time. A device that loses GNT# may complete its current transaction, but may not start one (by asserting FRAME#) unless it observes GNT# asserted the cycle before it begins.
1864:
protocol, a pull-up resistor on the motherboard raises this signal high and PCI-X operation is enabled. The pin is still connected to ground via coupling capacitors on each card to preserve its AC shielding
3235:
On clock edge 6, the target indicates that it wants to stop (with data), but the initiator is already holding IRDY# low, so there is a fifth data phase (clock edge 7), during which no data is transferred.
732:(IRQ) lines can be shared. The PCI bus includes four interrupt lines, INTA# through INTD#, all of which are available to each device. Up to eight PCI devices share the same IRQ line (LNKA through LNKH) in
679:) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates the resources and tells each device what its allocation is.
2885:
On the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all "subtractive decoding" is allowed for some address ranges. This is commonly used by an
2500:
Generally, PCI writes are faster than PCI reads, because a device may buffer the incoming write data and release the bus faster. For a read, it must delay the data phase until the data has been fetched.
2558:
simply treat this as another reserved command code and not respond to it. This command code may only be used with a non-zero high-order address word; it is forbidden to use this cycle if not necessary.
1825:
PRSNT1# and PRSNT2# for each slot have their own pull-up resistors on the motherboard. The motherboard may (but does not have to) sense these pins to determine the presence of PCI cards and their power
3943:
3283:
The second cycle of the address phase is then reserved for DEVSEL# turnaround, so if the target is different from the prior one, it must not assert DEVSEL# until the third cycle (medium DEVSEL speed).
2650:
The PCI standard permits multiple independent PCI buses to be connected by bus bridges that will forward operations on one bus to another when required. Although PCI tends not to use many bus bridges,
2979:
A data phase with all four C/BE# lines deasserted is explicitly permitted by the PCI standard, and must have no effect on the target other than to advance the address in the burst access in progress.
3102:
If the initiator observes STOP# before asserting its own IRDY#, then it can end the burst by deasserting FRAME# at the same time as it asserts IRDY#, ending the burst after the current data phase.
660:, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or
2969:. In all cases, the initiator drives active-low byte select signals on the C/BE# lines, but the data on the AD may be driven by the initiator (in case of writes) or target (in case of reads).
2870:), seeing that it has GNT# and the bus is idle, drives the target address onto the AD lines, the associated command (e.g. memory read, or I/O write) on the C/BE# lines, and pulls FRAME# low.
2588:
Soon after promulgation of the PCI specification, it was discovered that lengthy transactions by some devices, due to slow acknowledgments, long data bursts, or some combination, could cause
2709:
be combined, for example, by performing only the second write and skipping the first write that was overwritten. This is because the PCI specification permits writes to have side effects.
2486:
select signals. They instead specify the order in which burst data must be returned. If a device does not support the requested order, it must provide the first word and then disconnect.
2454:
device which only supports 2 bytes of I/O address space), it must be terminated with a target abort. Multiple data cycles are permitted, using linear (simple incrementing) burst ordering.
540:. Since then, motherboard manufacturers have included progressively fewer PCI slots in favor of the new standard. Many new motherboards do not provide PCI slots at all, as of late 2013.
3959:
Although the
Adaptec SCSI Card 29160 is a 64-bit PCI card, it also works in a 32-bit PCI slot. When installed in a 32-bit PCI slot, the card automatically runs in the slower 32-bit mode.
2931:
TRDY# and STOP# are deasserted (high) during the address phase. The initiator may assert IRDY# as soon as it is ready to transfer data, which could theoretically be as soon as clock 2.
2545:
This command is identical to a generic memory read, but includes the hint that a long read burst will continue beyond the end of the current cache line, and the target should internally
3304:
Targets that have this ability indicate it by a special bit in a PCI configuration register, and if all targets on a bus have it, all initiators may use back-to-back transfers freely.
3290:
It is also possible for the target to keep track of the requirements. If it never does fast DEVSEL, they are met trivially. If it does, it must wait until medium DEVSEL time unless:
3082:
Normally, a target holds DEVSEL# asserted through the last data phase. However, if a target deasserts DEVSEL# before disconnecting without data (asserting STOP#), this indicates a
1923:
Many 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-bit connectors, with some loss of performance. An example of this is the
Adaptec 29160 64-bit
1868:
At least one of PRSNT1# and PRSNT2# must be grounded by the card. The combination chosen indicates the total power requirements of the card (25 W, 15 W, or 7.5 W).
2679:
The PCI standard permits bus bridges to convert multiple bus transactions into one larger transaction under certain situations. This can improve the efficiency of the PCI bus.
2386:'s I/O port address space. Although the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O.
719:
counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data.
3894:
The ZX370 Series is a true 64-bit adapter, widening the network pipeline to achieve higher throughput while offering backward compatibility with standard 32-bit PCI slots.
4393:
3342:
The REQ64# and ACK64# lines are held asserted for the entire transaction save the last data phase and deasserted at the same time as FRAME# and DEVSEL#, respectively.
3198:
Most PCI devices only support a limited range of typical cache line sizes; if the cache line size is programmed to an unexpected value, they force single-word access.
3008:
In case of a read, clock 2 is reserved for turning around the AD bus, so the target is not permitted to drive data on the bus even if it is capable of fast DEVSEL.
2413:
initiator to target). PCI targets must examine the command code as well as the address and not respond to address phases that specify an unsupported command code.
3628:
1907:
A semi-inserted PCI-X card in a 32-bit PCI slot, illustrating the need for the rightmost notch and the extra room on the motherboard to remain backward compatible
1871:
SBO# and SDONE are signals from a cache controller to the current target. They are not initiator outputs, but are colored that way because they are target inputs.
2394:
on, all PCI devices respond only to their configuration space accesses. The computer's BIOS scans for devices and assigns Memory and I/O address ranges to them.
743:
or operating system code is meant to know this, and set the "interrupt line" field in each device's configuration space indicating which IRQ it is connected to.
1832:
The interrupt pins INTA# through INTD# are connected to all slots in different orders. (INTA# on one slot is INTB# on the next and INTC# on the one after that.)
2874:(Actually, the time to respond is 2.5 cycles, since PCI devices must transmit all signals half a cycle early so that they can be received three cycles later.)
3361:. This required support by cacheable memory targets, which would listen to two pins from the cache on the bus, SDONE (snoop done) and SBO# (snoop backoff).
2997:
To maintain full burst speed, the data sender then has half a clock cycle after seeing both IRDY# and TRDY# asserted to drive the next word onto the AD bus.
3076:, and unlike other PCI transactions, PCI initiators are required to pause slightly before continuing the operation. See the PCI specification for details.
2489:
If a memory space is marked as "prefetchable", then the target device must ignore the byte-select signals on a memory read and always return 32 valid bits.
2445:
to save power). No device ever responds to this cycle; it is always terminated with a master abort after leaving the data on the bus for at least 4 cycles.
1724:
64-bit PCI extends this by an additional 32 contacts on each side which provide AD, C/BE#, the PAR64 parity signal, and a number of power and ground pins.
3972:
3335:
address and the final command code during both address phase cycles; this allows a 64-bit target to see the entire address and begin responding earlier.
2579:
This optimization only affects the snooping cache, and makes no difference to the target, which may treat this as a synonym for the memory write command.
2940:
are forbidden if the high-order address bits are zero, so devices that do not support 64-bit addressing can simply not respond to dual-cycle commands.
2744:
372:, was introduced in version 2.2 of the PCI specification. The PCI bus was also adopted for an external laptop connector standard – the
2497:
This operates similarly to a memory read. The byte select signals are more important in a write, as unselected bytes must not be written to memory.
2049:
and some routers; it uses a 32-bit, 33 MHz bus with powered connections (3.3 V only; 5 V is limited to 100 mA) and support for
5313:
4446:
2982:
The data phase continues until both parties are ready to complete the transfer and continue to the next data phase. The initiator asserts IRDY# (
1890:, active low signal. PCI cards may use this signal to send and receive PME via the PCI socket directly, which eliminates the need for a special
368:) operated at frequencies up to 133 MHz for PCI-X 1.0 and up to 533 MHz for PCI-X 2.0. An internal connector for laptop cards, called
3307:
A subtractive decoding bus bridge must know to expect this extra delay in the event of back-to-back cycles, to advertise back-to-back support.
3221:
The equivalent read burst takes one more cycle, because the target must wait 1 cycle for the AD bus to turn around before it may assert TRDY#:
3035:
may not deassert FRAME# before asserting IRDY#, nor may it deassert FRAME# while waiting, with IRDY# asserted, for the target to assert TRDY#.
2457:
The PCI standard is discouraging the use of I/O space in new devices, preferring that as much as possible be done through main memory mapping.
4135:
739:
The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is implementation-dependent. Platform-specific
3907:
5266:
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
5293:
4711:
2352:
command code, then waits for a target to respond. All other devices examine this address and one of them responds a few cycles later.
733:
295:(VLB) slot as the bus configuration. It has subsequently been adopted for other computer types. Typical PCI cards used in PCs include:
2592:
or overrun in other devices. Recommendations on the timing of individual phases in
Revision 2.0 were made mandatory in revision 2.1:
5239:
3364:
Because this was rarely implemented in practice, it was deleted from revision 2.2 of the PCI specification, and the pins re-used for
503:
Outside the server market, the 64-bit version of plain PCI remained rare in practice though, although it was used for example by all
4488:
2596:
A target must be able to complete the initial data phase (assert TRDY# and/or STOP#) within 16 cycles of the start of a transaction.
4868:
2893:
On the sixth cycle, if there has been no response, the initiator may abort the transaction by deasserting FRAME#. This is known as
4731:
465:
114:
4538:
2634:
attempt the same transaction, a delayed transaction begun by one may have its result delivered to the other; this is harmless.
702:. These are typically needed for devices used during system startup, before device drivers are loaded by the operating system.
3877:
2359:
While the PCI bus transfers 32 bits per data phase, the initiator transmits 4 active-low byte enable signals indicating which
4390:
4351:
4331:
4311:
4291:
4271:
3715:
3681:
3654:
3613:
3586:
3090:. A target may not deassert DEVSEL# while waiting with TRDY# or STOP# low; it must do this at the beginning of a data phase.
859:
bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards.
754:
to gain an advantage when servicing a shared interrupt line, and for robustness: edge-triggered interrupts are easy to miss.
4919:
4590:
364:
Version 2.1 of the PCI standard introduced optional 66 MHz operation. A server-oriented variant of PCI, PCI Extended (
5298:
3113:
If the initiator ends the burst at the same time as the target requests disconnection, there is no additional bus cycle.
4625:
2658:; each PCI Express slot appears to be a separate bus, connected by a bridge to the others. The PCI host bridge (usually
2104:
controllers and combination cards. Mini PCI cards can be used with regular PCI-equipped hardware, using Mini PCI-to-PCI
1990:
4972:
4811:
4741:
3491:
3539:
2770:
1978:
4458:
2965:
After the address phase (specifically, beginning with the cycle that DEVSEL# goes low) comes a burst of one or more
2752:
4899:
4475:
3858:
3450:
4422:
2953:
may assert DEVSEL#. Each slot connects a different high-order address line to the IDSEL pin and is selected using
2398:
using the all-ones value in important status registers, so that such an error can be easily detected by software.
4691:
2748:
288:
110:
3976:
3696:
VLB was designed for 486-based systems, yet even the more generic PCI was to gain prominence on that platform.
5243:
4894:
4863:
1860:
The PCIXCAP pin is an additional ground on PCI buses and cards. If all cards and the motherboard support the
4516:
3403:
When developing and/or troubleshooting the PCI bus, examination of hardware signals can be very important.
5303:
4841:
4506:
2549:
a large amount of data. A target is always permitted to consider this a synonym for a generic memory read.
2093:
5308:
5167:
5106:
4961:
4233:
2639:
758:
3379:
Targets supporting cache coherency are also required to terminate bursts before they cross cache lines.
4766:
4531:
4086:
2990:). Whichever side is providing the data must drive it on the AD bus before asserting its ready signal.
461:
118:
5136:
4441:
4821:
3272:
they are by the same initiator (or there would be no time to turn around the C/BE# and FRAME# lines),
2085:
600:
335:
132:
4161:
3187:
If the starting offset within the cache line is zero, all of these modes reduce to the same order.
2733:
849:
816:
per second) for 32-bit bus width (33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s)
17:
4144:
3492:"PCIe (Peripheral Component Interconnect Express) | On the Motherboard | Pearson IT Certification"
1891:
5274:
5249:
5141:
4796:
3420:
3265:
asserted, FRAME# deasserted) to the first cycle of the next (FRAME# asserted, IRDY# deasserted).
2737:
2659:
2417:
2407:
2390:
676:
657:
447:
775:
does not have physical interrupt lines at all. It uses message-signaled interrupts exclusively.
4831:
3914:
3086:, which is a fatal error condition. The initiator may not retry, and typically treats it as a
2420:
cache line size register being set up properly; they may not be used until that has been done.
2341:
2332:
PCI bus traffic consists of a series of PCI bus transactions. Each transaction consists of an
884:
with a voltage they support. "Universal cards" accepting either voltage have both key notches.
473:
408:
256:
178:
3743:
3603:
411:
and the relative low cost to produce. Another common modern application of parallel PCI is in
5095:
5048:
4904:
4676:
4524:
3671:
3644:
3576:
3017:
targets will not be this fast and will not need any special logic to enforce this condition.
2109:
497:
331:
244:
4244:
3339:
seeing DEVSEL#. If ACK64# is missing, it may cease driving the upper half of the data bus.
514:
Later revisions of PCI added new features and performance improvements, including a 66
5091:
4944:
4826:
4447:
Good diagrams and text on how to recognize the difference between 5 volt and 3.3 volt slots
2124:
2054:
1927:
interface card. However, some 64-bit PCI-X cards do not work in standard 32-bit PCI slots.
468:(EISA) as the server expansion bus of choice. In mainstream PCs, PCI was slower to replace
404:
4409:
4114:
1911:
879:
expansion card with both 5 V and 3.3 V support notches, side B toward the camera
8:
5003:
4558:
3730:
2878:
1854:
802:
260:
3252:
Even when some bytes are masked by the C/BE# lines and not in use, they must still have
871:
334:
needs outgrew the abilities of PCI. The preferred interface for video cards then became
4547:
3859:"archive.org/zuavra.net - Using Wake-On-LAN WOL/PME to power up your computer remotely"
3396:
1850:
504:
493:
472:, and did not gain significant market penetration until late 1994 in second-generation
268:
3411:
are tools that collect, analyze, and decode signals for users to view in useful ways.
3275:
the first transaction was a write (so there is no need to turn around the AD bus), and
2820:
The PCI bus requires that every time the device driving a PCI bus signal changes, one
251:
to be connected directly to its own bus and are assigned addresses in the processor's
4993:
4615:
4551:
4347:
4327:
4307:
4287:
4267:
4207:
4068:
4046:
4024:
4002:
3711:
3677:
3650:
3609:
3582:
3535:
3473:
2805:
2429:
2376:
762:
747:
729:
637:
284:
228:
30:"Conventional PCI" redirects here. For the related standard that supersedes PCI, see
4251:($ 1000 for non-members or $ 50 for members. PCI-SIG membership is $ 3000 per year.)
4240:($ 1000 for non-members or $ 50 for members. PCI-SIG membership is $ 3000 per year.)
3646:
Digital VLSI Design with
Verilog: A Textbook from Silicon Valley Technical Institute
3210:
This is the highest-possible speed four-word write burst, terminated by the master:
2034:
751:
4726:
3881:
3814:
2800:) if not driven by any device, but the PCI bus does not depend on the resistors to
2383:
876:
856:
819:
766:
687:
672:
649:
645:
360:
342:
66:
4495:
3555:
2796:. Pull-up resistors on the motherboard ensure they will remain high (inactive or
1812:
Each slot has its own REQ# output to, and GNT# input from the motherboard arbiter.
791:
These specifications represent the most common version of PCI used in normal PCs:
765:, it resolves some synchronization problems that can occur with posted writes and
476:
PCs. By 1996, VLB was all but extinct, and manufacturers had adopted PCI even for
4856:
4706:
4686:
4561:
4397:
3404:
3358:
3228:
A high-speed burst terminated by the target will have an extra cycle at the end:
2589:
2546:
2360:
2349:
1898:
485:
320:
2890:
bridge for addresses within its range (24 bits for memory and 16 bits for I/O).
1878:) – Power management event (optional) which is supported in PCI
5157:
4851:
4776:
4701:
4605:
4580:
3294:
the current transaction was preceded by an idle cycle (is not back-to-back), or
1887:
893:
481:
469:
292:
280:
122:
4442:
Brief overview of PCI power requirements and compatibility with a nice diagram
3780:
2907:
2006:
380:, but subsequent development of the standard became the responsibility of the
5287:
5229:
5116:
5008:
4956:
4939:
4721:
4620:
4610:
4585:
4546:
4463:
2097:
2065:
2050:
1094:
695:
653:
412:
316:
252:
248:
3278:
the initiator still has permission (from its GNT# input) to use the PCI bus.
2846:"park" the bus grant signal at any device if there are no current requests.
4966:
4909:
4761:
4666:
4403:
3832:
3515:
3408:
2617:
Devices unable to meet those timing restrictions must use a combination of
2512:
A PCI device must not respond to an address cycle with these command codes.
2477:
A PCI device must not respond to an address cycle with these command codes.
2132:
1849:
66 MHz operation is enabled. The pin is still connected to ground via
798:
787:
Diagram showing the different key positions for 32-bit and 64-bit PCI cards
661:
508:
323:
296:
264:
224:
2804:
the signal level; all devices drive the signals high for one cycle before
2599:
An initiator must complete each data phase (assert IRDY#) within 8 cycles.
1815:
Each slot has its own IDSEL line, usually connected to a specific AD line.
442:
A motherboard with two 32-bit PCI slots and two sizes of PCI Express slots
5234:
5213:
5131:
4976:
4914:
4889:
4816:
4600:
4595:
4143:(Application Note). Intel Corporation. March 1997. AP-753. Archived from
3433:
3122:
depend on the cache line size, which is configurable on all PCI devices.
2651:
2436:
style interrupt controller on the PCI bus, this cycle need never be used.
1903:
772:
530:
477:
400:
312:
272:
155:
136:
70:
31:
5053:
3862:
2923:
C/BE will provide the command following by first data phase byte enables
2375:
Memory addresses are 32 bits (optionally 64 bits) in size, support
1808:
Most lines are connected to each slot in parallel. The exceptions are:
5087:
4786:
4575:
3425:
3355:
2842:
2833:) is it necessary to insert additional delay to meet this requirement.
2785:
2433:
2081:
1789:
892:
The PCI connector is defined as having 62 contacts on each side of the
699:
480:(486) computers. EISA continued to be used alongside PCI through 2000.
327:
300:
240:
164:/s (32-bit at 33 MHz – the standard configuration)
2372:
PCI has three address spaces: memory, I/O address, and configuration.
1167:
Power management event (optional) 3.3 V, open drain, active low.
855:
The PCI specification also provides options for 3.3 V signaling,
614:
Incorporated ECNs, errata, and deleted 5 volt only keyed add-in cards
5111:
5101:
5068:
5063:
4998:
4873:
4661:
4646:
4641:
3392:
3087:
2662:
in x86 platforms) interconnect between CPU, main memory and PCI bus.
2131:. The additional 24 pins provide the extra signals required to route
2077:
2069:
515:
438:
423:
399:
to distinguish them technologically from their more recent successor
348:
220:
51:
3578:
Inside PC Card: CardBus and PCMCIA Design: CardBus and PCMCIA Design
2994:
indicates that the just-latched data is the word to be transferred.
2722:
5121:
5058:
4791:
4651:
3944:"Adaptec SCSI Card 29160 Ultra160 SCSI Controller User's Reference"
2986:) when it no longer needs to wait, while the target asserts TRDY# (
2136:
830:
826:
813:
809:
740:
668:
232:
161:
60:
4092:
3387:
3256:
defined value, and this value must be used to compute the parity.
2972:
During data phases, the C/BE# lines are interpreted as active-low
1829:
REQ64# and ACK64# are individually pulled up on 32-bit only slots.
283:
that fits into a slot. The PCI Local Bus was first implemented in
5254:
5208:
5192:
5018:
4836:
4781:
4716:
4671:
4211:
4162:"Bus Specifics - Writing Device Drivers for Oracle® Solaris 11.3"
4072:
4050:
4028:
4006:
3818:
3477:
3438:
2954:
2887:
2867:
2793:
2128:
691:
432:
385:
373:
341:
The first version of PCI found in retail desktop computers was a
3530:
Hamacher, V. Carl; Vranesic, Zvonko G.; Zaky, Safwat G. (2002).
1818:
TDO is daisy-chained to the following slot's TDI. Cards without
5187:
5078:
5043:
5038:
5033:
5028:
4846:
4736:
4696:
4656:
4324:
PCI & PCI-X Hardware and
Software Architecture & Design
2046:
2014:
5172:
5083:
3268:
An initiator may only perform back-to-back transactions when:
2344:, and always halts a transaction after the first data phase.)
2026:
1899:
Mixing of 32-bit and 64-bit PCI cards in different width slots
243:
but in a standardized format that is independent of any given
5182:
5073:
5013:
4951:
4924:
4806:
4756:
4681:
4375:
3444:
3429:
3365:
3316:
2073:
2061:
2019:
1861:
1822:
support must connect TDI to TDO so as not to break the chain.
1768:
May be driven by initiator or target, depending on operation
1434:
1397:
783:
656:
are assigned by software. A third address space, called the
523:
489:
377:
365:
304:
197:
100:
3072:
A Disconnect without data before transferring any data is a
2642:
of the whole bus if one initiator is reset or malfunctions.
338:(AGP), a superset of PCI, before giving way to PCI Express.
247:'s native bus. Devices connected to the PCI bus appear to a
5177:
5162:
5023:
4934:
4929:
4771:
3159:
Cacheline toggle (0x0C, 0x08, 0x04, 0x00, 0x1C, 0x18, ...)
2101:
2089:
1924:
1819:
928:
840:
519:
428:
355:
4184:
4137:
PCI Local Bus Specification: Revision 2.1 vs. Revision 2.0
3331:
per-transaction basis whether to allow a 64-bit transfer.
3300:
the current transaction began with a double address cycle.
625:
Removed support for 5.0 volt keyed system board connector
588:
Incorporated clarifications and added 66 MHz chapter
427:
A typical 32-bit, 5 V-only PCI card, in this case, a
5126:
4751:
4746:
4428:
3170:
Cacheline wrap (0x0C, 0x00, 0x04, 0x08, 0x1C, 0x10, ...)
2140:
1961:
PCI Card lengths (Low Profile Bracket & 3.3 V):
757:
Later revisions of the PCI specification add support for
641:
308:
3148:
Linear incrementing (0x0C, 0x10, 0x14, 0x18, 0x1C, ...)
664:(I/O) port space via its configuration space registers.
359:
signaling, although the PCI 1.0 standard provided for a
239:
standard. The PCI bus supports the functions found on a
4115:"Re: sym53c875: reading /proc causes SCSI parity error"
3710:(8th ed.). McGraw Hill Professional. p. 339.
2841:
Any device on a PCI bus that is capable of acting as a
2521:
incrementing) are permitted in PCI configuration space.
1776:
Driven by the target, received by the initiator/master
1760:
Driven by the master/initiator, received by the target
778:
3930:
Backward compatible with 32 bit, 33 MHz PCI slots
3908:"ZX370 Series Multi-Channel PCI Fast Ethernet Adapter"
3315:
This section explains only basic 64-bit PCI; the full
1950:
PCI Card lengths (Standard Bracket & 3.3 V):
728:
Devices are required to follow a protocol so that the
2674:
2416:
The commands that refer to cache lines depend on the
1694:
For 64-bit extension; no connect for 32-bit devices.
577:
Incorporated connector and add-in card specification
460:
PCI was immediately put to use in servers, replacing
287:, where it displaced the combination of several slow
3529:
2108:. Mini PCI has been superseded by the much narrower
1784:
Driven by the motherboard, received by the PCI card
1752:
Driven by the PCI card, received by the motherboard
2830:
2382:I/O addresses are for compatibility with the Intel
2654:systems use many PCI-to-PCI bridge usually called
2537:This operates analogously to a configuration read.
1794:May be pulled low and/or sensed by multiple cards
1055:Pulled low to indicate 7.5 or 15 W power required
1027:Pulled low to indicate 7.5 or 25 W power required
391:PCI and PCI-X sometimes are referred to as either
267:. Attached devices can take either the form of an
4464:Decoding PCI data and lspci output on Linux hosts
3848:PCI Power Management Interface Specification v1.2
3595:
3259:
27:Local computer bus for attaching hardware devices
5285:
3973:"LaCie support: Identify a variety of PCI slots"
3297:the prior transaction was to the same target, or
2114:
4869:Coherent Accelerator Processor Interface (CAPI)
3556:"PCI Edition AMD HD 4350 Graphic Card from HIS"
2038:MiniPCI and MiniPCI Express cards in comparison
376:. The first PCI specification was developed by
3708:CompTIA A+ Certification All-in-One Exam Guide
3663:
3638:
3636:
3605:LabVIEW based Advanced Instrumentation Systems
3601:
3462:
3029:
2705:Multiple writes to the same byte or bytes may
4532:
4286:(4th ed.). Addison-Wesley Professional.
3875:
3447:, PCI Industrial Computer Manufacturers Group
3354:PCI originally included optional support for
2324:Mini PCI is distinct from 144-pin Micro PCI.
2060:Many Mini PCI devices were developed such as
1996:A low-profile card with a full-height bracket
1915:64-bit SCSI card working in a 32-bit PCI slot
675:) queries all PCI buses at startup time (via
4130:
4128:
3673:System Design for Telecommunication Gateways
3349:
3323:connector by the additional 64-bit segment.
690:(ROM) containing executable code for x86 or
307:, extra ports such as Universal Serial Bus (
3844:
3842:
3633:
3574:
3181:Reserved (disconnect after first transfer)
3045:
2751:. Unsourced material may be challenged and
825:32- or 64-bit memory address space (4
4539:
4525:
3699:
3669:
3319:protocol extension is much more extensive.
2135:back through the system connector (audio,
866:
59:
50:
4246:PCI Local Bus Specification: Revision 3.0
4235:PCI Local Bus Specification: Revision 2.3
4193:PCI Local Bus Specification, revision 2.1
4125:
3905:
3770:PCI Local Bus Specification, revision 3.0
2771:Learn how and when to remove this message
450:(IAL, also Architecture Development Lab)
4204:PCI Local Bus Specification Revision 2.2
4178:
4065:PCI Local Bus Specification Revision 3.0
4043:PCI Local Bus Specification Revision 3.0
4021:PCI Local Bus Specification Revision 3.0
3999:PCI Local Bus Specification Revision 3.0
3839:
3811:PCI Local Bus Specification Revision 2.3
3805:
3803:
3801:
3799:
3797:
3783:. Reric.NET by Eric Seppanen. 2004-11-14
3766:
3764:
3762:
3760:
3758:
3756:
3642:
3568:
3470:PCI Local Bus Specification Revision 2.2
3386:
3011:
2045:was added to PCI version 2.2 for use in
2033:
2025:
2013:
2005:
1910:
1902:
1717:
1714:
1704:
1701:
1690:
1687:
1677:
1674:
1666:
1663:
1655:
1652:
1644:
1641:
1633:
1630:
1622:
1619:
1611:
1608:
1597:
1594:
1586:
1583:
1572:
1569:
1561:
1547:
1544:
1536:
1533:
1525:
1522:
1514:
1511:
1500:
1497:
1486:
1483:
1472:
1469:
1447:
1421:
1410:
1407:
1393:
1376:
1373:
1362:
1359:
1348:
1345:
1334:
1331:
1323:
1320:
1312:
1309:
1301:
1298:
1290:
1287:
1279:
1276:
1268:
1265:
1257:
1254:
1246:
1243:
1235:
1232:
1224:
1221:
1213:
1210:
1202:
1199:
1191:
1188:
1177:
1174:
1163:
1160:
1149:
1146:
1135:
1132:
1121:
1118:
1107:
1104:
1090:
1087:
1079:
1076:
1065:
1062:
1051:
1048:
1037:
1034:
1023:
1020:
1012:
1009:
1001:
998:
987:
984:
974:
971:
963:
960:
952:
949:
941:
938:
924:
921:
870:
782:
437:
422:
330:replaced ISA and VLB cards until rising
4341:
4301:
4281:
4112:
3941:
3205:
2947:
2917:GNT# Irrelevant after cycle has started
2901:
2612:
2327:
1069:Key notch for 3.3 V-capable cards
466:Extended Industry Standard Architecture
14:
5314:Computer-related introductions in 1993
5286:
4380:, PCI Special Interest Group (PCI-SIG)
4321:
4261:
3705:
3137:Burst order (with 16-byte cache line)
3020:
1934:
4520:
4196:
4187:
3794:
3753:
3676:. John Wiley & Sons. p. 81.
2957:encoding on the upper address lines.
2934:
2862:A PCI bus transaction begins with an
2829:only in a few special cases (notably
2572:1111: Memory Write and Invalidate
2367:
1576:Key notch for 5 V-capable cards
1153:Bus request from card to motherboard
631:
170:533 MB/s (64-bit at 66 MHz)
166:266 MB/s (32-bit at 66 MHz)
4431:, a project to collect all known IDs
3382:
2920:Address is only valid for one cycle.
2749:adding citations to reliable sources
2716:
2401:
779:Conventional hardware specifications
652:, respectively. Addresses in these
3116:
2465:This performs a write to I/O space.
2318:Smaller Y dimension (44.6 mm)
2297:Larger Y dimension (50.95 mm)
1802:Not presently used, do not connect
1139:Bus grant from motherboard to card
887:
24:
4344:PCI HotPlug Application and Design
4266:(2nd ed.). Elsevier Science.
4221:
3399:(POST) numbers during BIOS startup
2712:
2675:Combining, merging, and collapsing
2645:
2618:
2583:
2529:routine operation of a PCI device.
2271:Smaller Z dimension (5.5 mm)
2246:Large Z dimension (17.44 mm)
2225:Smaller Z dimension (5.5 mm)
1845:5 V-only cards on the market.
1841:determine their I/O signal levels.
529:The PCI-SIG introduced the serial
25:
5325:
5294:Peripheral Component Interconnect
4362:
4227:Official technical specifications
3970:
3602:Sumathi, S.; Surekha, P. (2007).
2030:PCI-to-MiniPCI converter Type III
636:PCI provides separate memory and
213:Peripheral Component Interconnect
5270:
5269:
4306:(1st ed.). Addison-Wesley.
3451:Eurocard (printed circuit board)
2906:
2857:
2811:
2721:
2665:
2200:Large Z dimension (7.5 mm)
1989:
1977:
843:(per device) configuration space
492:) in mid-1995, and the consumer
279:in the PCI specification) or an
168:266 MB/s (64-bit at 33 MHz)
4154:
4106:
4079:
4075:. February 3, 2004. Figure 5-7.
4057:
4053:. February 3, 2004. Figure 5-6.
4035:
4031:. February 3, 2004. Figure 5-9.
4013:
4009:. February 3, 2004. Figure 5-8.
3991:
3964:
3935:
3899:
3876:ZNYX Networks (June 16, 2009).
3869:
3851:
3825:
3773:
3736:
3731:Identify a variety of PCI slots
3724:
3690:
2424:0000: Interrupt Acknowledge
2379:and can be burst transactions.
1744:Supplies power to the PCI card
1504:Address/data bus (higher half)
808:Peak transfer rate of 133
4417:Lists of Vendors, Devices, IDs
4113:Roudier, Gérard (2001-11-28).
3670:Bachmutsky, Alexander (2011).
3622:
3548:
3523:
3518:. Web-o-pedia. September 1996.
3508:
3496:www.pearsonitcertification.com
3484:
3260:Fast back-to-back transactions
3038:The only minor exception is a
2960:
2836:
2831:fast back-to-back transactions
2817:response to the other device.
2542:1100: Memory Read Multiple
1601:Address/data bus (lower half)
1490:Even parity over AD and C/BE#
1400:capable; Target requests halt
1181:Address/data bus (upper half)
289:Industry Standard Architecture
13:
1:
4864:Intel Ultra Path Interconnect
3534:(5th ed.). McGraw-Hill.
3480:. December 18, 1998. page ii.
3456:
3310:
2788:, meaning that the active or
2700:
2534:1011: Configuration Write
2115:Technical details of Mini PCI
1853:on each card to preserve its
723:
686:Devices may have an on-board
534:
484:adopted PCI for professional
451:
4842:Intel QuickPath Interconnect
4832:Direct Media Interface (DMI)
4391:Introduction to PCI protocol
4091:(FAQ), iBASE, archived from
3575:Imdad-Haque, Faisal (1996).
3441:, PCI Special Interest Group
2682:
2554:1101: Dual Address Cycle
2517:1010: Configuration Read
2301:
2275:
2250:
2229:
2204:
2171:
1558:
1555:
1453:
1450:
1427:
1424:
1390:
1387:
991:Interrupt pins (open-drain)
900:32-bit PCI connector pinout
640:port address spaces for the
509:G4 Power Macintosh computers
7:
4508:IP Search for PCI Bus Cores
4423:PCI Vendor and Device Lists
4404:PCI bus pin-out and signals
4346:(1st ed.). Annabooks.
4326:(5th ed.). Annabooks.
4249:. PCI-SIG. August 12, 2002.
3414:
3191:line size to implement it.
3030:Initiator burst termination
2866:. The initiator (usually a
2001:
1954:Short Card: 169.52 mm;
1946:Low Profile: 79.20 mm.
759:message-signaled interrupts
603:, and improved readability
496:product line (replacing LC
10:
5330:
5299:Motherboard expansion slot
4827:Compute Express Link (CXL)
4238:. PCI-SIG. March 29, 2002.
4212:PCI Special Interest Group
4073:PCI Special Interest Group
4051:PCI Special Interest Group
4029:PCI Special Interest Group
4007:PCI Special Interest Group
3819:PCI Special Interest Group
3478:PCI Special Interest Group
3314:
2691:
2563:1110: Memory Read Line
2405:
2086:cryptographic accelerators
1957:Long Card: 313.78 mm.
1180:
522:standard and 133 MHz
462:Micro Channel architecture
418:
382:PCI Special Interest Group
29:
5263:
5222:
5201:
5150:
5064:IEEE-1284 (parallel port)
4986:
4979:logical device interface)
4882:
4634:
4568:
4304:PCI-X System Architecture
3781:"PCI Latency Timer Howto"
3608:. Springer. p. 305.
3350:Cache snooping (obsolete)
3239:
2281:
2278:
2232:
2177:
2174:
1943:Standard: 120.02 mm;
1707:
1600:
1575:
1503:
1338:Bus transfer in progress
1068:
1041:+5 V or +3.3 V
990:
927:
910:
907:
709:that are a mechanism for
667:In a typical system, the
446:Work on PCI began at the
336:Accelerated Graphics Port
291:(ISA) slots and one fast
192:
184:
174:
151:
143:
128:
106:
96:
78:
73:(PC bracket on left side)
69:PCI expansion slots on a
58:
49:
44:
4459:Linux with miniPCI cards
3942:Adaptec (January 2000).
3706:Meyers, Michael (2012).
3649:. Springer. p. 67.
3368:access in revision 2.3.
3046:Target burst termination
3040:master abort termination
2895:master abort termination
2336:followed by one or more
1461:Snoop backoff (obsolete)
850:Reflected-wave switching
746:PCI interrupt lines are
4491:, Lattice Semiconductor
4476:Active PCI Bus Extender
4284:PCI System Architecture
3643:Williams, John (2008).
3421:PCI configuration space
3062:Disconnect without data
2441:0001: Special Cycle
2418:PCI configuration space
2408:PCI configuration space
2391:PCI configuration space
867:Card voltage and keying
750:. This was chosen over
705:In addition, there are
677:PCI Configuration Space
658:PCI Configuration Space
448:Intel Architecture Labs
4626:List of bus bandwidths
4342:Goodrum, Alan (1998).
3833:"PCI Connector Pinout"
3581:. Newnes. p. 39.
3400:
2784:transaction. All are
2494:0111: Memory Write
2039:
2031:
2023:
2011:
1939:PCI brackets heights:
1916:
1908:
880:
788:
721:
443:
435:
409:backward compatibility
84:; 32 years ago
4302:Shanley, Tom (2000).
4282:Shanley, Tom (1999).
4262:Abbott, Doug (2004).
3532:Computer Organization
3390:
3012:Fast DEVSEL# on reads
2656:PCI Express Root Port
2482:0110: Memory Read
2123:There are three card
2110:PCI Express Mini Card
2037:
2029:
2017:
2009:
1984:A full-height bracket
1914:
1906:
1439:Snoop done (obsolete)
1125:33/66 MHz clock
931:port pins (optional)
874:
836:32-bit I/O port space
786:
716:
498:Processor Direct Slot
488:computers (replacing
441:
426:
185:Hotplugging interface
135:for graphics (1997),
5069:IEEE-1394 (FireWire)
4807:PCI Extended (PCI-X)
4400:, electrofriends.com
4214:. December 18, 1998.
4088:Micro PCI, Micro AGP
3744:"PCI Family History"
3206:Transaction examples
3055:Disconnect with data
2948:Configuration access
2902:Address phase timing
2745:improve this section
2613:Delayed transactions
2430:IBM PC compatibility
2328:PCI bus transactions
1971:MD3: 243.18 mm.
1968:MD2: 169.52 mm;
1965:MD1: 121.79 mm;
1882:and higher. It is a
1736:Zero volt reference
763:signaling is in-band
500:(PDS)) in mid-1996.
5304:Macintosh internals
4910:Parallel ATA (PATA)
4410:PCI card dimensions
4322:Solari, Ed (2001).
4264:PCI Bus Demystified
3127:
3126:PCI burst ordering
3021:Ending transactions
2462:0011: I/O Write
2364:behave as a no-op.
1935:Physical dimensions
1857:shielding function.
1851:coupling capacitors
1729:
1414:Locked transaction
1091:3.3 V aux
901:
545:
235:and is part of the
41:
5309:IBM PC compatibles
4817:PCI Express (PCIe)
4489:PCI Interface Core
4412:, interfacebus.com
4396:2013-01-19 at the
3401:
3397:power-on self-test
3125:
2935:Dual-cycle address
2450:0010: I/O Read
2368:PCI address spaces
2342:burst transactions
2040:
2032:
2024:
2012:
1917:
1909:
1727:
899:
881:
789:
707:PCI Latency Timers
644:processor family,
632:Auto configuration
543:
444:
436:
403:, which adopted a
285:IBM PC compatibles
269:integrated circuit
82:June 22, 1992
39:
5281:
5280:
5267:
4994:Apple Desktop Bus
4971:PCI Express (via
4930:Serial ATA (SATA)
4616:Network on a chip
4470:Development Tools
4429:PCI ID Repository
4425:, pcidatabase.com
4385:Technical Details
4353:978-0-929392-60-8
4333:978-0-929392-63-9
4313:978-0-201-72682-4
4293:978-0-201-30974-4
4273:978-0-7506-7739-4
4208:Hillsboro, Oregon
4069:Hillsboro, Oregon
4047:Hillsboro, Oregon
4025:Hillsboro, Oregon
4003:Hillsboro, Oregon
3821:. March 29, 2002.
3717:978-0-07-179512-8
3683:978-1-119-95642-6
3656:978-1-4020-8446-1
3629:PCI Bus Variation
3615:978-3-540-48501-8
3588:978-0-08-053473-2
3474:Hillsboro, Oregon
3383:Development tools
3185:
3184:
2781:
2780:
2773:
2432:; if there is no
2402:PCI command codes
2322:
2321:
1892:Wake-on-LAN cable
1806:
1805:
1757:Initiator output
1722:
1721:
769:interrupt lines.
730:interrupt-request
711:PCI Bus-Mastering
638:memory-mapped I/O
629:
628:
210:
209:
16:(Redirected from
5321:
5273:
5272:
5265:
4727:HP Precision Bus
4541:
4534:
4527:
4518:
4517:
4512:
4501:
4379:
4378:
4376:Official website
4357:
4337:
4317:
4297:
4277:
4250:
4239:
4216:
4215:
4200:
4194:
4191:
4185:
4182:
4176:
4175:
4173:
4172:
4158:
4152:
4151:
4149:
4142:
4132:
4123:
4122:
4110:
4104:
4102:
4101:
4100:
4083:
4077:
4076:
4061:
4055:
4054:
4039:
4033:
4032:
4017:
4011:
4010:
3995:
3989:
3988:
3986:
3984:
3979:on April 4, 2012
3975:. Archived from
3968:
3962:
3961:
3956:
3954:
3948:
3939:
3933:
3932:
3927:
3925:
3920:on July 20, 2013
3919:
3913:. Archived from
3912:
3903:
3897:
3896:
3891:
3889:
3880:. Archived from
3873:
3867:
3866:
3865:on 8 March 2007.
3861:. Archived from
3855:
3849:
3846:
3837:
3836:
3829:
3823:
3822:
3815:Portland, Oregon
3807:
3792:
3791:
3789:
3788:
3777:
3771:
3768:
3751:
3750:
3748:
3740:
3734:
3728:
3722:
3721:
3703:
3697:
3694:
3688:
3687:
3667:
3661:
3660:
3640:
3631:
3626:
3620:
3619:
3599:
3593:
3592:
3572:
3566:
3565:
3563:
3562:
3552:
3546:
3545:
3527:
3521:
3519:
3512:
3506:
3505:
3503:
3502:
3488:
3482:
3481:
3466:
3128:
3124:
3117:Burst addressing
2910:
2822:turnaround cycle
2806:ceasing to drive
2776:
2769:
2765:
2762:
2756:
2725:
2717:
2384:x86 architecture
2315:
2311:
2307:
2293:
2289:
2268:
2264:
2260:
2256:
2243:
2239:
2222:
2218:
2214:
2210:
2197:
2193:
2189:
2185:
2146:
2145:
1993:
1981:
1885:
1881:
1877:
1730:
1726:
1380:Target selected
1352:Initiator ready
902:
898:
888:Connector pinout
877:Gigabit Ethernet
846:5-volt signaling
797:
688:read-only memory
673:operating system
546:
542:
539:
536:
456:
453:
397:Conventional PCI
358:
351:
271:fitted onto the
206:
203:
201:
199:
92:
90:
85:
63:
54:
42:
38:
21:
5329:
5328:
5324:
5323:
5322:
5320:
5319:
5318:
5284:
5283:
5282:
5277:
5268:
5259:
5218:
5197:
5146:
5059:IEEE-488 (GPIB)
4982:
4878:
4857:Infinity Fabric
4687:Europe Card Bus
4630:
4564:
4545:
4505:
4497:PCI Bridge Core
4494:
4478:, dinigroup.com
4398:Wayback Machine
4374:
4373:
4365:
4354:
4334:
4314:
4294:
4274:
4243:
4232:
4224:
4222:Further reading
4219:
4202:
4201:
4197:
4192:
4188:
4183:
4179:
4170:
4168:
4166:docs.oracle.com
4160:
4159:
4155:
4147:
4140:
4134:
4133:
4126:
4121:(Mailing list).
4111:
4107:
4098:
4096:
4085:
4084:
4080:
4063:
4062:
4058:
4041:
4040:
4036:
4019:
4018:
4014:
3997:
3996:
3992:
3982:
3980:
3969:
3965:
3952:
3950:
3946:
3940:
3936:
3923:
3921:
3917:
3910:
3906:ZNYX Networks.
3904:
3900:
3887:
3885:
3874:
3870:
3857:
3856:
3852:
3847:
3840:
3831:
3830:
3826:
3809:
3808:
3795:
3786:
3784:
3779:
3778:
3774:
3769:
3754:
3746:
3742:
3741:
3737:
3729:
3725:
3718:
3704:
3700:
3695:
3691:
3684:
3668:
3664:
3657:
3641:
3634:
3627:
3623:
3616:
3600:
3596:
3589:
3573:
3569:
3560:
3558:
3554:
3553:
3549:
3542:
3528:
3524:
3514:
3513:
3509:
3500:
3498:
3490:
3489:
3485:
3468:
3467:
3463:
3459:
3417:
3405:Logic analyzers
3385:
3359:cache coherence
3352:
3320:
3313:
3262:
3242:
3233:
3226:
3215:
3208:
3119:
3048:
3032:
3023:
3014:
3002:
2984:initiator ready
2963:
2950:
2945:
2937:
2904:
2860:
2839:
2814:
2792:state is a low
2777:
2766:
2760:
2757:
2742:
2726:
2715:
2713:PCI bus signals
2703:
2694:
2685:
2677:
2668:
2648:
2646:PCI bus bridges
2615:
2590:buffer underrun
2586:
2584:PCI bus latency
2410:
2404:
2370:
2330:
2313:
2309:
2305:
2291:
2287:
2283:
2266:
2262:
2258:
2254:
2241:
2237:
2220:
2216:
2212:
2208:
2195:
2191:
2187:
2183:
2179:
2163:
2155:
2153:
2117:
2010:A Mini PCI slot
2004:
1997:
1994:
1985:
1982:
1937:
1901:
1883:
1879:
1875:
890:
869:
795:
781:
752:edge-triggering
748:level-triggered
726:
694:processors, an
634:
566:Original issue
555:Change summary
537:
486:Power Macintosh
454:
421:
353:
346:
321:hard disk drive
196:
169:
167:
165:
159:
88:
86:
83:
74:
35:
28:
23:
22:
15:
12:
11:
5:
5327:
5317:
5316:
5311:
5306:
5301:
5296:
5279:
5278:
5264:
5261:
5260:
5258:
5257:
5252:
5247:
5237:
5232:
5226:
5224:
5220:
5219:
5217:
5216:
5211:
5205:
5203:
5199:
5198:
5196:
5195:
5190:
5185:
5180:
5175:
5170:
5168:Intel HD Audio
5165:
5160:
5158:ADAT Lightpipe
5154:
5152:
5148:
5147:
5145:
5144:
5139:
5134:
5129:
5124:
5119:
5114:
5109:
5104:
5099:
5081:
5076:
5071:
5066:
5061:
5056:
5051:
5046:
5041:
5036:
5031:
5026:
5021:
5016:
5011:
5006:
5001:
4996:
4990:
4988:
4984:
4983:
4981:
4980:
4969:
4964:
4959:
4954:
4949:
4948:
4947:
4942:
4932:
4927:
4922:
4917:
4912:
4907:
4902:
4897:
4892:
4886:
4884:
4880:
4879:
4877:
4876:
4871:
4866:
4861:
4860:
4859:
4852:HyperTransport
4849:
4844:
4839:
4834:
4829:
4824:
4819:
4814:
4809:
4804:
4799:
4794:
4789:
4784:
4779:
4774:
4769:
4764:
4759:
4754:
4749:
4744:
4739:
4734:
4729:
4724:
4719:
4714:
4709:
4704:
4699:
4694:
4689:
4684:
4679:
4674:
4669:
4664:
4659:
4654:
4649:
4644:
4638:
4636:
4632:
4631:
4629:
4628:
4623:
4618:
4613:
4608:
4606:Bus contention
4603:
4598:
4593:
4588:
4583:
4581:Front-side bus
4578:
4572:
4570:
4566:
4565:
4562:computer buses
4544:
4543:
4536:
4529:
4521:
4515:
4514:
4503:
4492:
4485:
4484:
4480:
4479:
4472:
4471:
4467:
4466:
4461:
4455:
4454:
4450:
4449:
4444:
4438:
4437:
4433:
4432:
4426:
4419:
4418:
4414:
4413:
4407:
4401:
4387:
4386:
4382:
4381:
4370:
4369:
4364:
4363:External links
4361:
4360:
4359:
4352:
4339:
4332:
4319:
4312:
4299:
4292:
4279:
4272:
4258:
4257:
4253:
4252:
4241:
4229:
4228:
4223:
4220:
4218:
4217:
4195:
4186:
4177:
4153:
4150:on 2015-04-30.
4124:
4105:
4078:
4056:
4034:
4012:
3990:
3963:
3934:
3898:
3884:on May 2, 2011
3878:"ZX370 Series"
3868:
3850:
3838:
3824:
3793:
3772:
3752:
3735:
3723:
3716:
3698:
3689:
3682:
3662:
3655:
3632:
3621:
3614:
3594:
3587:
3567:
3547:
3540:
3522:
3507:
3483:
3460:
3458:
3455:
3454:
3453:
3448:
3442:
3436:
3423:
3416:
3413:
3395:that displays
3384:
3381:
3351:
3348:
3312:
3309:
3302:
3301:
3298:
3295:
3287:support this.
3280:
3279:
3276:
3273:
3261:
3258:
3241:
3238:
3230:
3223:
3212:
3207:
3204:
3183:
3182:
3179:
3176:
3172:
3171:
3168:
3165:
3161:
3160:
3157:
3154:
3150:
3149:
3146:
3143:
3139:
3138:
3135:
3132:
3118:
3115:
3111:
3110:
3106:
3103:
3100:
3092:
3091:
3080:
3077:
3070:
3067:
3063:
3060:
3056:
3047:
3044:
3031:
3028:
3022:
3019:
3013:
3010:
2999:
2962:
2959:
2949:
2946:
2942:
2936:
2933:
2925:
2924:
2921:
2918:
2903:
2900:
2877:A device must
2859:
2856:
2838:
2835:
2813:
2810:
2779:
2778:
2729:
2727:
2720:
2714:
2711:
2702:
2699:
2693:
2690:
2684:
2681:
2676:
2673:
2667:
2664:
2647:
2644:
2614:
2611:
2601:
2600:
2597:
2585:
2582:
2581:
2580:
2577:
2573:
2569:
2568:
2564:
2560:
2559:
2555:
2551:
2550:
2543:
2539:
2538:
2535:
2531:
2530:
2526:
2522:
2518:
2514:
2513:
2510:
2509:: Reserved
2502:
2501:
2498:
2495:
2491:
2490:
2487:
2483:
2479:
2478:
2475:
2474:: Reserved
2467:
2466:
2463:
2459:
2458:
2455:
2451:
2447:
2446:
2442:
2438:
2437:
2425:
2403:
2400:
2369:
2366:
2329:
2326:
2320:
2319:
2316:
2303:
2299:
2298:
2295:
2294:× 59.6 × 50.95
2285:
2280:
2277:
2273:
2272:
2269:
2252:
2248:
2247:
2244:
2234:
2231:
2227:
2226:
2223:
2206:
2202:
2201:
2198:
2181:
2176:
2173:
2169:
2168:
2165:
2164:(mm × mm × mm)
2160:
2157:
2150:
2116:
2113:
2022:card Type IIIB
2003:
2000:
1999:
1998:
1995:
1988:
1986:
1983:
1976:
1973:
1972:
1969:
1966:
1959:
1958:
1955:
1948:
1947:
1944:
1936:
1933:
1900:
1897:
1896:
1895:
1872:
1869:
1866:
1858:
1846:
1842:
1834:
1833:
1830:
1827:
1823:
1816:
1813:
1804:
1803:
1800:
1796:
1795:
1792:
1786:
1785:
1782:
1778:
1777:
1774:
1773:Target output
1770:
1769:
1766:
1762:
1761:
1758:
1754:
1753:
1750:
1746:
1745:
1742:
1738:
1737:
1734:
1720:
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1716:
1713:
1709:
1708:
1706:
1703:
1700:
1696:
1695:
1692:
1689:
1686:
1682:
1681:
1679:
1676:
1673:
1669:
1668:
1665:
1662:
1658:
1657:
1654:
1651:
1647:
1646:
1643:
1640:
1636:
1635:
1632:
1629:
1625:
1624:
1621:
1618:
1614:
1613:
1610:
1607:
1603:
1602:
1599:
1596:
1593:
1589:
1588:
1585:
1582:
1578:
1577:
1574:
1571:
1568:
1564:
1563:
1560:
1557:
1554:
1550:
1549:
1546:
1543:
1539:
1538:
1535:
1532:
1528:
1527:
1524:
1521:
1517:
1516:
1513:
1510:
1506:
1505:
1502:
1499:
1496:
1492:
1491:
1488:
1485:
1482:
1478:
1477:
1474:
1471:
1468:
1464:
1463:
1459:SMBus data or
1457:
1452:
1449:
1446:
1442:
1441:
1433:Parity error;
1431:
1426:
1423:
1420:
1416:
1415:
1412:
1409:
1406:
1402:
1401:
1395:
1392:
1389:
1386:
1382:
1381:
1378:
1375:
1372:
1368:
1367:
1364:
1361:
1358:
1354:
1353:
1350:
1347:
1344:
1340:
1339:
1336:
1333:
1330:
1326:
1325:
1322:
1319:
1315:
1314:
1311:
1308:
1304:
1303:
1300:
1297:
1293:
1292:
1289:
1286:
1282:
1281:
1278:
1275:
1271:
1270:
1267:
1264:
1260:
1259:
1256:
1253:
1249:
1248:
1245:
1242:
1238:
1237:
1234:
1231:
1227:
1226:
1223:
1220:
1216:
1215:
1212:
1209:
1205:
1204:
1201:
1198:
1194:
1193:
1190:
1187:
1183:
1182:
1179:
1176:
1173:
1169:
1168:
1165:
1162:
1159:
1155:
1154:
1151:
1148:
1145:
1141:
1140:
1137:
1134:
1131:
1127:
1126:
1123:
1120:
1117:
1113:
1112:
1109:
1106:
1103:
1099:
1098:
1092:
1089:
1086:
1082:
1081:
1078:
1075:
1071:
1070:
1067:
1064:
1061:
1057:
1056:
1053:
1050:
1047:
1043:
1042:
1039:
1036:
1033:
1029:
1028:
1025:
1022:
1019:
1015:
1014:
1011:
1008:
1004:
1003:
1000:
997:
993:
992:
989:
986:
983:
979:
978:
976:
973:
970:
966:
965:
962:
959:
955:
954:
951:
948:
944:
943:
940:
937:
933:
932:
926:
923:
920:
916:
915:
912:
909:
906:
894:edge connector
889:
886:
868:
865:
853:
852:
847:
844:
837:
834:
823:
817:
806:
780:
777:
725:
722:
698:driver, or an
654:address spaces
633:
630:
627:
626:
623:
620:
616:
615:
612:
609:
605:
604:
597:
594:
590:
589:
586:
583:
579:
578:
575:
572:
568:
567:
564:
561:
557:
556:
553:
550:
505:(post-iMac) G3
482:Apple Computer
420:
417:
413:industrial PCs
352:bus clock and
317:TV tuner cards
293:VESA Local Bus
281:expansion card
227:for attaching
208:
207:
194:
190:
189:
186:
182:
181:
176:
172:
171:
153:
149:
148:
145:
141:
140:
130:
126:
125:
108:
104:
103:
98:
94:
93:
80:
76:
75:
64:
56:
55:
47:
46:
26:
9:
6:
4:
3:
2:
5326:
5315:
5312:
5310:
5307:
5305:
5302:
5300:
5297:
5295:
5292:
5291:
5289:
5276:
5262:
5256:
5253:
5251:
5248:
5245:
5241:
5238:
5236:
5233:
5231:
5230:Multidrop bus
5228:
5227:
5225:
5221:
5215:
5212:
5210:
5207:
5206:
5204:
5200:
5194:
5191:
5189:
5186:
5184:
5181:
5179:
5176:
5174:
5171:
5169:
5166:
5164:
5161:
5159:
5156:
5155:
5153:
5149:
5143:
5140:
5138:
5137:External PCIe
5135:
5133:
5130:
5128:
5125:
5123:
5120:
5118:
5117:Parallel SCSI
5115:
5113:
5110:
5108:
5105:
5103:
5100:
5097:
5093:
5089:
5085:
5082:
5080:
5077:
5075:
5072:
5070:
5067:
5065:
5062:
5060:
5057:
5055:
5052:
5050:
5047:
5045:
5042:
5040:
5037:
5035:
5032:
5030:
5027:
5025:
5022:
5020:
5017:
5015:
5012:
5010:
5009:Commodore bus
5007:
5005:
5002:
5000:
4997:
4995:
4992:
4991:
4989:
4985:
4978:
4974:
4970:
4968:
4965:
4963:
4960:
4958:
4957:Fibre Channel
4955:
4953:
4950:
4946:
4943:
4941:
4938:
4937:
4936:
4933:
4931:
4928:
4926:
4923:
4921:
4918:
4916:
4913:
4911:
4908:
4906:
4903:
4901:
4898:
4896:
4893:
4891:
4888:
4887:
4885:
4881:
4875:
4872:
4870:
4867:
4865:
4862:
4858:
4855:
4854:
4853:
4850:
4848:
4845:
4843:
4840:
4838:
4835:
4833:
4830:
4828:
4825:
4823:
4820:
4818:
4815:
4813:
4810:
4808:
4805:
4803:
4800:
4798:
4795:
4793:
4790:
4788:
4785:
4783:
4780:
4778:
4775:
4773:
4770:
4768:
4765:
4763:
4760:
4758:
4755:
4753:
4750:
4748:
4745:
4743:
4740:
4738:
4735:
4733:
4730:
4728:
4725:
4723:
4720:
4718:
4715:
4713:
4710:
4708:
4705:
4703:
4700:
4698:
4695:
4693:
4690:
4688:
4685:
4683:
4680:
4678:
4675:
4673:
4670:
4668:
4665:
4663:
4660:
4658:
4655:
4653:
4650:
4648:
4645:
4643:
4640:
4639:
4637:
4633:
4627:
4624:
4622:
4621:Plug and play
4619:
4617:
4614:
4612:
4611:Bus mastering
4609:
4607:
4604:
4602:
4599:
4597:
4594:
4592:
4589:
4587:
4586:Back-side bus
4584:
4582:
4579:
4577:
4574:
4573:
4571:
4567:
4563:
4560:
4556:
4554:
4549:
4542:
4537:
4535:
4530:
4528:
4523:
4522:
4519:
4510:
4509:
4504:
4499:
4498:
4493:
4490:
4487:
4486:
4482:
4481:
4477:
4474:
4473:
4469:
4468:
4465:
4462:
4460:
4457:
4456:
4452:
4451:
4448:
4445:
4443:
4440:
4439:
4435:
4434:
4430:
4427:
4424:
4421:
4420:
4416:
4415:
4411:
4408:
4405:
4402:
4399:
4395:
4392:
4389:
4388:
4384:
4383:
4377:
4372:
4371:
4367:
4366:
4355:
4349:
4345:
4340:
4335:
4329:
4325:
4320:
4315:
4309:
4305:
4300:
4295:
4289:
4285:
4280:
4275:
4269:
4265:
4260:
4259:
4255:
4254:
4248:
4247:
4242:
4237:
4236:
4231:
4230:
4226:
4225:
4213:
4209:
4205:
4199:
4190:
4181:
4167:
4163:
4157:
4146:
4139:
4138:
4131:
4129:
4120:
4116:
4109:
4095:on 2001-12-11
4094:
4090:
4089:
4082:
4074:
4070:
4066:
4060:
4052:
4048:
4044:
4038:
4030:
4026:
4022:
4016:
4008:
4004:
4000:
3994:
3978:
3974:
3967:
3960:
3945:
3938:
3931:
3916:
3909:
3902:
3895:
3883:
3879:
3872:
3864:
3860:
3854:
3845:
3843:
3834:
3828:
3820:
3816:
3812:
3806:
3804:
3802:
3800:
3798:
3782:
3776:
3767:
3765:
3763:
3761:
3759:
3757:
3745:
3739:
3732:
3727:
3719:
3713:
3709:
3702:
3693:
3685:
3679:
3675:
3674:
3666:
3658:
3652:
3648:
3647:
3639:
3637:
3630:
3625:
3617:
3611:
3607:
3606:
3598:
3590:
3584:
3580:
3579:
3571:
3557:
3551:
3543:
3541:9780071122184
3537:
3533:
3526:
3517:
3511:
3497:
3493:
3487:
3479:
3475:
3471:
3465:
3461:
3452:
3449:
3446:
3443:
3440:
3437:
3435:
3431:
3427:
3424:
3422:
3419:
3418:
3412:
3410:
3409:bus analyzers
3406:
3398:
3394:
3389:
3380:
3377:
3373:
3369:
3367:
3362:
3360:
3357:
3347:
3343:
3340:
3336:
3332:
3328:
3324:
3318:
3308:
3305:
3299:
3296:
3293:
3292:
3291:
3288:
3284:
3277:
3274:
3271:
3270:
3269:
3266:
3257:
3255:
3250:
3246:
3237:
3229:
3222:
3219:
3211:
3203:
3199:
3196:
3192:
3188:
3180:
3177:
3174:
3173:
3169:
3166:
3163:
3162:
3158:
3155:
3152:
3151:
3147:
3144:
3141:
3140:
3136:
3133:
3130:
3129:
3123:
3114:
3107:
3104:
3101:
3098:
3097:
3096:
3089:
3085:
3081:
3078:
3075:
3071:
3068:
3064:
3061:
3057:
3054:
3053:
3052:
3043:
3041:
3036:
3027:
3018:
3009:
3006:
2998:
2995:
2991:
2989:
2985:
2980:
2977:
2975:
2970:
2968:
2958:
2956:
2941:
2932:
2929:
2922:
2919:
2916:
2915:
2914:
2911:
2909:
2899:
2896:
2891:
2889:
2883:
2880:
2875:
2871:
2869:
2865:
2864:address phase
2858:Address phase
2855:
2851:
2847:
2844:
2834:
2832:
2826:
2823:
2818:
2812:Signal timing
2809:
2808:the signals.
2807:
2803:
2799:
2795:
2791:
2787:
2775:
2772:
2764:
2761:February 2020
2754:
2750:
2746:
2740:
2739:
2735:
2730:This section
2728:
2724:
2719:
2718:
2710:
2708:
2698:
2689:
2688:consecutive.
2680:
2672:
2666:Posted writes
2663:
2661:
2657:
2653:
2643:
2641:
2635:
2631:
2627:
2624:
2620:
2619:posted writes
2610:
2607:
2598:
2595:
2594:
2593:
2591:
2578:
2574:
2571:
2570:
2565:
2562:
2561:
2556:
2553:
2552:
2548:
2544:
2541:
2540:
2536:
2533:
2532:
2527:
2523:
2519:
2516:
2515:
2511:
2508:
2504:
2503:
2499:
2496:
2493:
2492:
2488:
2484:
2481:
2480:
2476:
2473:
2469:
2468:
2464:
2461:
2460:
2456:
2452:
2449:
2448:
2443:
2440:
2439:
2435:
2431:
2426:
2423:
2422:
2421:
2419:
2414:
2409:
2399:
2395:
2392:
2387:
2385:
2380:
2378:
2373:
2365:
2362:
2357:
2353:
2351:
2345:
2343:
2339:
2335:
2334:address phase
2325:
2317:
2312:× 59.6 × 44.6
2304:
2300:
2296:
2286:
2274:
2270:
2253:
2249:
2245:
2235:
2228:
2224:
2207:
2203:
2199:
2182:
2170:
2166:
2161:
2158:
2154:outer edge of
2151:
2148:
2147:
2144:
2142:
2138:
2134:
2130:
2126:
2121:
2112:
2111:
2107:
2103:
2099:
2095:
2091:
2087:
2083:
2079:
2075:
2071:
2067:
2066:Fast Ethernet
2063:
2058:
2056:
2052:
2051:bus mastering
2048:
2044:
2036:
2028:
2021:
2016:
2008:
1992:
1987:
1980:
1975:
1974:
1970:
1967:
1964:
1963:
1962:
1956:
1953:
1952:
1951:
1945:
1942:
1941:
1940:
1932:
1928:
1926:
1921:
1913:
1905:
1893:
1889:
1873:
1870:
1867:
1863:
1859:
1856:
1852:
1847:
1843:
1839:
1838:
1837:
1831:
1828:
1826:requirements.
1824:
1821:
1817:
1814:
1811:
1810:
1809:
1801:
1798:
1797:
1793:
1791:
1788:
1787:
1783:
1780:
1779:
1775:
1772:
1771:
1767:
1764:
1763:
1759:
1756:
1755:
1751:
1748:
1747:
1743:
1740:
1739:
1735:
1732:
1731:
1725:
1711:
1710:
1698:
1697:
1693:
1684:
1683:
1680:
1671:
1670:
1660:
1659:
1649:
1648:
1638:
1637:
1627:
1626:
1616:
1615:
1605:
1604:
1591:
1590:
1580:
1579:
1566:
1565:
1552:
1551:
1541:
1540:
1530:
1529:
1519:
1518:
1508:
1507:
1494:
1493:
1489:
1480:
1479:
1476:System error
1475:
1466:
1465:
1462:
1458:
1456:
1444:
1443:
1440:
1436:
1432:
1430:
1418:
1417:
1413:
1404:
1403:
1399:
1396:
1384:
1383:
1379:
1370:
1369:
1366:Target ready
1365:
1356:
1355:
1351:
1342:
1341:
1337:
1328:
1327:
1317:
1316:
1306:
1305:
1295:
1294:
1284:
1283:
1273:
1272:
1262:
1261:
1251:
1250:
1240:
1239:
1229:
1228:
1218:
1217:
1207:
1206:
1196:
1195:
1185:
1184:
1171:
1170:
1166:
1157:
1156:
1152:
1143:
1142:
1138:
1129:
1128:
1124:
1115:
1114:
1110:
1101:
1100:
1096:
1095:Standby power
1093:
1084:
1083:
1073:
1072:
1059:
1058:
1054:
1045:
1044:
1040:
1031:
1030:
1026:
1017:
1016:
1006:
1005:
995:
994:
981:
980:
977:
968:
967:
957:
956:
946:
945:
935:
934:
930:
918:
917:
913:
904:
903:
897:
895:
885:
878:
873:
864:
860:
858:
851:
848:
845:
842:
838:
835:
832:
828:
824:
821:
818:
815:
811:
807:
804:
800:
794:
793:
792:
785:
776:
774:
770:
768:
764:
760:
755:
753:
749:
744:
742:
737:
735:
731:
720:
715:
712:
708:
703:
701:
697:
696:Open Firmware
693:
689:
684:
680:
678:
674:
670:
665:
663:
659:
655:
651:
647:
643:
639:
624:
621:
618:
617:
613:
610:
607:
606:
602:
599:Incorporated
598:
595:
592:
591:
587:
584:
581:
580:
576:
573:
570:
569:
565:
562:
559:
558:
554:
551:
548:
547:
541:
532:
527:
525:
521:
517:
512:
510:
506:
501:
499:
495:
491:
487:
483:
479:
475:
471:
467:
463:
458:
449:
440:
434:
431:adapter from
430:
425:
416:
414:
410:
406:
402:
398:
394:
389:
387:
383:
379:
375:
371:
367:
362:
357:
350:
344:
339:
337:
333:
329:
325:
324:host adapters
322:
318:
314:
310:
306:
302:
298:
297:network cards
294:
290:
286:
282:
278:
277:planar device
274:
270:
266:
262:
258:
254:
253:address space
250:
246:
242:
241:processor bus
238:
237:PCI Local Bus
234:
231:devices in a
230:
226:
222:
218:
214:
205:
195:
191:
187:
183:
180:
177:
173:
163:
157:
154:
150:
146:
144:Width in bits
142:
138:
134:
131:
129:Superseded by
127:
124:
120:
116:
112:
109:
105:
102:
99:
95:
81:
77:
72:
68:
65:Three 5-volt
62:
57:
53:
48:
45:PCI Local Bus
43:
37:
33:
19:
4801:
4762:TURBOchannel
4552:
4507:
4496:
4406:, pinouts.ru
4343:
4323:
4303:
4283:
4263:
4245:
4234:
4203:
4198:
4189:
4180:
4169:. Retrieved
4165:
4156:
4145:the original
4136:
4119:linux-kernel
4118:
4108:
4097:, retrieved
4093:the original
4087:
4081:
4064:
4059:
4042:
4037:
4020:
4015:
3998:
3993:
3981:. Retrieved
3977:the original
3966:
3958:
3951:. Retrieved
3937:
3929:
3922:. Retrieved
3915:the original
3901:
3893:
3886:. Retrieved
3882:the original
3871:
3863:the original
3853:
3827:
3810:
3785:. Retrieved
3775:
3738:
3726:
3707:
3701:
3692:
3672:
3665:
3645:
3624:
3604:
3597:
3577:
3570:
3559:. Retrieved
3550:
3531:
3525:
3510:
3499:. Retrieved
3495:
3486:
3469:
3464:
3402:
3378:
3374:
3370:
3363:
3353:
3344:
3341:
3337:
3333:
3329:
3325:
3321:
3306:
3303:
3289:
3285:
3281:
3267:
3263:
3253:
3251:
3247:
3243:
3234:
3227:
3220:
3216:
3209:
3200:
3197:
3193:
3189:
3186:
3120:
3112:
3105:Disconnect-B
3099:Disconnect-A
3093:
3084:target abort
3083:
3079:Target abort
3073:
3066:transferred.
3049:
3039:
3037:
3033:
3024:
3015:
3007:
3003:
2996:
2992:
2988:target ready
2987:
2983:
2981:
2978:
2974:byte enables
2973:
2971:
2966:
2964:
2951:
2938:
2930:
2926:
2912:
2905:
2894:
2892:
2884:
2876:
2872:
2863:
2861:
2852:
2848:
2840:
2827:
2821:
2819:
2815:
2801:
2797:
2789:
2782:
2767:
2758:
2743:Please help
2731:
2706:
2704:
2695:
2686:
2678:
2669:
2655:
2649:
2636:
2632:
2628:
2622:
2616:
2605:
2602:
2587:
2506:
2471:
2415:
2411:
2396:
2388:
2381:
2374:
2371:
2358:
2354:
2346:
2337:
2333:
2331:
2323:
2125:form factors
2122:
2118:
2105:
2059:
2042:
2041:
1960:
1949:
1938:
1929:
1922:
1918:
1835:
1807:
1723:
1612:+3.3 V
1515:+3.3 V
1460:
1454:
1438:
1428:
1324:+3.3 V
1258:+3.3 V
1192:+3.3 V
891:
882:
861:
854:
790:
771:
756:
745:
738:
727:
717:
710:
706:
704:
685:
681:
666:
662:input/output
635:
544:PCI history
528:
513:
502:
459:
445:
396:
393:Parallel PCI
392:
390:
381:
369:
345:bus using a
340:
276:
263:to a single
236:
216:
212:
211:
79:Year created
36:
5235:CoreConnect
5214:ExpressCard
5142:Thunderbolt
5132:Camera Link
4915:Bus and Tag
4601:Address bus
4596:Control bus
4591:Daisy chain
4338:1140 pages.
3949:. p. 1
3434:PCI Express
2967:data phases
2961:Data phases
2837:Arbitration
2660:northbridge
2652:PCI Express
2338:data phases
2156:host system
2082:sound cards
1880:version 2.2
1765:I/O signal
1749:Output pin
1733:Ground pin
1620:+3.3 V
1484:+3.3 V
1448:+3.3 V
1411:+3.3 V
1360:+3.3 V
1299:+3.3 V
1233:+3.3 V
1097:(optional)
942:+12 V
829:or 16
803:synchronous
773:PCI Express
767:out-of-band
538: 2004
531:PCI Express
478:Intel 80486
455: 1990
401:PCI Express
328:video cards
301:sound cards
273:motherboard
261:synchronous
156:Half-duplex
137:PCI Express
71:motherboard
32:PCI Express
5288:Categories
5088:ACCESS.bus
4987:Peripheral
4787:InfiniBand
4782:HP GSC bus
4576:System bus
4511:, Berkeley
4500:, OpenCore
4483:FPGA Cores
4358:162 pages.
4318:752 pages.
4298:832 pages.
4278:250 pages.
4171:2020-12-18
4099:2010-11-20
3787:2008-07-17
3561:2009-07-27
3501:2020-09-25
3457:References
3426:CompactPCI
3356:write-back
3311:64-bit PCI
2843:bus master
2798:deasserted
2786:active-low
2701:Collapsing
2434:Intel 8259
2406:See also:
2236:17.44 × 70
2106:converters
1931:connector.
1888:open drain
1790:Open drain
1741:Power pin
1718:+5 V
1111:Bus reset
1013:+5 V
922:−12 V
724:Interrupts
700:Option ROM
464:(MCA) and
275:(called a
255:. It is a
249:bus master
107:Supersedes
97:Created by
89:1992-06-22
5049:Lightning
4999:Atari SIO
4874:SpaceWire
4707:Zorro III
4647:S-100 bus
4642:SS-50 bus
4635:Standards
4555:standards
4548:Technical
3393:POST card
3088:bus error
2732:does not
2683:Combining
2389:Finally,
2284:card edge
2167:comments
2159:Connector
2078:Winmodems
2070:Bluetooth
2018:Mini PCI
1865:function.
1799:Reserved
1715:+5 V
1705:+5 V
1702:+5 V
1437:clock or
985:+5 V
975:+5 V
972:+5 V
914:Comments
822:bus width
814:megabytes
805:transfers
796:33.33 MHz
518:3.3
332:bandwidth
265:bus clock
245:processor
223:computer
160:133
5275:Category
5250:Wishbone
5223:Embedded
5202:Portable
5122:Profibus
5054:DMX512-A
4940:Parallel
4792:Ethernet
4702:Zorro II
4652:Multibus
4553:de facto
4394:Archived
4368:Official
3983:July 13,
3953:July 13,
3924:July 13,
3888:July 13,
3415:See also
3026:memory.
2790:asserted
2640:deadlock
2547:prefetch
2180:stacking
2043:Mini PCI
2002:Mini PCI
1088:Reserved
1052:Reserved
1035:Reserved
1024:Reserved
875:A PCI-X
812:/s (133
741:firmware
669:firmware
494:Performa
370:Mini PCI
347:33
257:parallel
233:computer
229:hardware
188:Optional
179:Parallel
147:32 or 64
18:PCI card
5255:SLIMbus
5209:PC Card
5193:TOSLINK
4883:Storage
4837:RapidIO
4717:FASTBUS
4672:STD Bus
4569:General
3971:LaCie.
3733:, LaCie
3439:PCI-SIG
2955:one-hot
2913:Notes:
2888:ISA bus
2868:chipset
2794:voltage
2753:removed
2738:sources
2692:Merging
2377:caching
2282:124-pin
2178:100-pin
2152:Card on
2137:AC-Link
2129:SO-DIMM
2076:(often
2047:laptops
1836:Notes:
1728:Legend
1645:Ground
1587:Ground
1548:Ground
1388:PCIXCAP
1374:DEVSEL#
1291:Ground
1225:Ground
1080:Ground
1049:PRSNT2#
1021:PRSNT1#
692:PA-RISC
650:32 bits
619:PCI 3.0
608:PCI 2.3
593:PCI 2.2
582:PCI 2.1
571:PCI 2.0
560:PCI 1.0
474:Pentium
433:Adaptec
419:History
386:PCI-SIG
374:CardBus
354:5
219:) is a
200:.pcisig
193:Website
87: (
5188:S/PDIF
5079:1-Wire
5044:RS-485
5039:RS-423
5034:RS-422
5029:RS-232
4890:ST-506
4847:NVLink
4697:STEbus
4657:Unibus
4350:
4330:
4310:
4290:
4270:
3714:
3680:
3653:
3612:
3585:
3538:
3391:A PCI
3240:Parity
3059:burst.
2802:change
2074:modems
1874:PME# (
1781:Input
1691:REQ64#
1688:ACK64#
1653:Ground
1584:Ground
1573:Ground
1570:Ground
1559:Ground
1523:Ground
1473:Ground
1451:SMBDAT
1425:SMBCLK
1391:Ground
1377:Ground
1349:Ground
1335:FRAME#
1332:Ground
1266:Ground
1247:IDSEL
1200:Ground
1150:Ground
1133:Ground
1105:Ground
1077:Ground
1066:Ground
1063:Ground
1002:INTC#
950:Ground
911:Side A
908:Side B
857:64-bit
820:32-bit
405:serial
361:64-bit
343:32-bit
326:. PCI
313:serial
305:modems
139:(2004)
67:32-bit
5183:McASP
5151:Audio
5096:SMBus
5092:PMBus
5074:UNI/O
5014:HP-IL
4967:SATAe
4952:ESCON
4925:HIPPI
4757:NuBus
4712:CAMAC
4682:Q-Bus
4677:SMBus
4662:VAXBI
4559:wired
4453:Linux
4256:Books
4148:(PDF)
4141:(PDF)
3947:(pdf)
3918:(PDF)
3911:(PDF)
3747:(PDF)
3516:"PCI"
3445:PICMG
3430:PCI-X
3366:SMBus
3317:PCI-X
3074:retry
3069:Retry
2879:latch
2567:read.
2525:rare.
2361:8-bit
2350:4-bit
2062:Wi-Fi
2020:Wi-Fi
1884:3.3 V
1862:PCI-X
1678:IOPWR
1675:IOPWR
1598:C/BE#
1556:M66EN
1498:C/BE#
1470:SERR#
1435:SMBus
1429:SDONE
1422:PERR#
1408:LOCK#
1398:PCI-X
1394:STOP#
1363:TRDY#
1346:IRDY#
1321:C/BE#
1244:C/BE#
1161:IOPWR
1122:IOPWR
1038:IOPWR
1010:INTD#
999:INTB#
988:INTA#
925:TRST#
801:with
799:clock
524:PCI-X
490:NuBus
378:Intel
366:PCI-X
311:) or
259:bus,
221:local
204:/home
175:Style
152:Speed
101:Intel
5240:AMBA
5178:MADI
5163:AES3
5024:MIDI
4977:NVMe
4973:AHCI
4935:SCSI
4920:DSSI
4895:ESDI
4772:SBus
4732:EISA
4667:MBus
4557:for
4550:and
4436:Tips
4348:ISBN
4328:ISBN
4308:ISBN
4288:ISBN
4268:ISBN
3985:2012
3955:2012
3926:2012
3890:2012
3712:ISBN
3678:ISBN
3651:ISBN
3610:ISBN
3583:ISBN
3536:ISBN
3407:and
3254:some
3109:end.
2736:any
2734:cite
2623:must
2302:IIIB
2276:IIIA
2265:× 45
2261:× 78
2240:× 45
2219:× 45
2215:× 70
2194:× 45
2190:× 70
2162:Size
2149:Type
2102:SATA
2090:SCSI
2053:and
1925:SCSI
1876:19 A
1820:JTAG
1455:SBO#
1164:PME#
1147:REQ#
1136:GNT#
1108:RST#
964:TDI
953:TMS
929:JTAG
841:byte
839:256-
734:APIC
671:(or
648:and
622:2004
611:2002
601:ECNs
596:1998
585:1995
574:1993
563:1992
552:Year
549:Spec
507:and
429:SCSI
319:and
202:.com
115:EISA
5244:AXI
5173:I²S
5127:USB
5112:D²B
5107:SPI
5102:I3C
5084:I²C
5019:HIL
5004:DCB
4975:or
4962:SSA
4945:SAS
4905:SMD
4900:IPI
4822:AGP
4812:PXI
4802:PCI
4797:UPA
4777:VLB
4767:MCA
4752:VPX
4747:VXS
4742:VXI
4737:VME
4722:LPC
4692:ISA
2747:by
2707:not
2606:and
2505:100
2470:010
2308:2.4
2290:2.4
2267:.00
2257:5.5
2251:IIB
2242:.00
2233:Yes
2230:IIA
2221:.00
2211:5.5
2196:.00
2186:7.5
2141:LAN
2133:I/O
2098:ATA
2094:IDE
2080:),
2055:DMA
1712:62
1699:61
1685:60
1672:59
1667:AD
1661:58
1656:AD
1650:57
1639:56
1634:AD
1628:55
1623:AD
1617:54
1606:53
1592:52
1581:51
1567:50
1562:AD
1553:49
1542:48
1537:AD
1531:47
1526:AD
1520:46
1509:45
1495:44
1487:PAR
1481:43
1467:42
1445:41
1419:40
1405:39
1385:38
1371:37
1357:36
1343:35
1329:34
1318:33
1313:AD
1307:32
1302:AD
1296:31
1285:30
1280:AD
1274:29
1269:AD
1263:28
1252:27
1241:26
1236:AD
1230:25
1219:24
1214:AD
1208:23
1203:AD
1197:22
1186:21
1172:20
1158:19
1144:18
1130:17
1119:CLK
1116:16
1102:15
1085:14
1074:13
1060:12
1046:11
1032:10
961:TDO
939:TCK
905:Pin
831:EiB
827:GiB
642:x86
533:in
516:MHz
470:VLB
395:or
388:).
349:MHz
309:USB
225:bus
217:PCI
198:www
133:AGP
123:VLB
119:MCA
111:ISA
40:PCI
5290::
5094:,
5090:,
4210::
4206:.
4164:.
4127:^
4117:.
4071::
4067:.
4049::
4045:.
4027::
4023:.
4005::
4001:.
3957:.
3928:.
3892:.
3841:^
3817::
3813:.
3796:^
3755:^
3635:^
3494:.
3476::
3472:.
3432:,
3428:,
2279:No
2263:.0
2238:.0
2217:.0
2205:IB
2192:.0
2175:No
2172:IA
2139:,
2100:,
2092:,
2088:,
2084:,
2072:,
2068:,
2064:,
1886:,
1855:AC
1664:AD
1642:AD
1631:AD
1609:AD
1595:AD
1545:AD
1534:AD
1512:AD
1501:AD
1310:AD
1288:AD
1277:AD
1255:AD
1222:AD
1211:AD
1189:AD
1178:AD
1175:AD
1018:9
1007:8
996:7
982:6
969:5
958:4
947:3
936:2
919:1
810:MB
646:64
535:c.
511:.
452:c.
315:,
303:,
299:,
162:MB
158::
121:,
117:,
113:,
5246:)
5242:(
5098:)
5086:(
4540:e
4533:t
4526:v
4513:.
4502:.
4356:.
4336:.
4316:.
4296:.
4276:.
4174:.
4103:.
3987:.
3835:.
3790:.
3749:.
3720:.
3686:.
3659:.
3618:.
3591:.
3564:.
3544:.
3520:.
3504:.
3178:1
3175:1
3167:0
3164:1
3156:1
3153:0
3145:0
3142:0
3134:A
3131:A
2774:)
2768:(
2763:)
2759:(
2755:.
2741:.
2507:x
2472:x
2314:0
2310:0
2306:0
2292:0
2288:0
2259:0
2255:0
2213:0
2209:0
2188:0
2184:0
2096:–
1894:.
833:)
520:V
384:(
356:V
215:(
91:)
34:.
20:)
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