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twice, once for each possible value of B, and as more "don't care" inputs are added, the duplication grows exponentially); therefore, a programmable logic array can often implement a piece of logic using fewer transistors than the equivalent in read-only memory. This is particularly valuable when it is part of a processing chip where transistors are scarce (for example, the original
214:
possible combination of inputs, including combinations that are never supposed to occur, and also duplicating data for "don't care" conditions (for example, logic like "if input A is 1, then, as far as output X is concerned, we don't care what input B is": in a ROM this would have to be written out
72:
planes, which can then be conditionally complemented to produce an output. It has 2 AND gates for N input variables, and for M outputs from the PLA, there should be M OR gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in
242:
home computers released in 1982 (into early 1983) initially used a programmed
Signetics 82S100 PLA, but as the demand increased, MOS Technology / Commodore Semiconductor Group began producing a mask-programmed PLA, which bore part number 906114-01.
343:
116:
or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8
231:. It defines various states in an instruction set, and produces the next state (by conditional branching). . Programmable logic arrays should correspond to a
210:, with the inputs being driven by the address bus and the outputs being read out as data. However, that would require a separate memory location for
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92:) in that both the AND and OR gate planes are programmable. PAL has programmable AND gates but fixed OR gates
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Decide the input connection of the AND matrix for generating the required product term.
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Obtain the minimum SOP form to reduce the number of product terms to a minimum.
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Then decide the input connections of the OR matrix to generate the sum terms.
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A Texas
Instruments Application Report: MOS programmable logic arrays
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chip contained a PLA to direct various operations of the processor).
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One application of a PLA is to implement the control over a
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arcadecomponents.com - Commodore 906114-01 64 PLA IC
202:The desired outputs for each combination of inputs
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149:Decide the connections of the inversion matrix.
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68:planes, which link to a set of programmable
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297:How MOS 6502 Illegal Opcodes really work
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1122:Application-specific integrated circuit
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286:. Texas Instruments. Bulletin CA-158.
1057:Three-dimensional integrated circuit
64:. The PLA has a set of programmable
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1069:Erasable programmable logic device
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1104:Complex programmable logic device
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27:Type of programmable logic device
344:"PLA (programmable logic array)"
324:"Programmable Logic Array (PLA)"
198:Advantages over read-only memory
1116:Field-programmable object array
1052:Mixed-signal integrated circuit
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120:for memory. TI coined the term
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290:
108:-programmable IC based on the
13:
1:
1242:Hardware description language
1110:Field-programmable gate array
282:Andres, Kent (October 1970).
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253:Field-programmable gate array
1385:Electronic design automation
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1254:Formal equivalence checking
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1274:Hierarchical state machine
1232:Transaction-level modeling
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1160:Logic in computer science
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188:INVERT/ NON INVERT MATRIX
55:programmable logic device
1187:Switching circuit theory
1092:Programmable Array Logic
1080:Programmable logic array
484:Circuit underutilization
467:Reconfigurable computing
263:Programmable Array Logic
191:FLIP-FLOP OUTPUT BUFFER
128:Implementation procedure
122:Programmable Logic Array
82:programmable array logic
47:programmable logic array
32:Programmable Array Logic
30:Not to be confused with
18:Programmable Logic Array
1237:Register-transfer level
1128:Tensor Processing Unit
334:. 2003. Archived from
332:University of Maryland
42:
1343:Electronic literature
1297:Hardware acceleration
1165:Computer architecture
1063:Emitter-coupled logic
1000:Printed circuit board
494:Hardware acceleration
352:University of Hamburg
206:be programmed into a
41:PLA schematic example
40:
1269:Finite-state machine
1247:High-level synthesis
1182:Circuit minimization
684:Microchip Technology
489:High-level synthesis
133:Preparation in SOP (
73:the sum of products
1316:Digital photography
1098:Generic Array Logic
1020:Combinational logic
995:Printed electronics
959:Digital electronics
753:Intel Quartus Prime
479:Soft microprocessor
156:PLA block diagram:
59:combinational logic
1264:Asynchronous logic
1040:Integrated circuit
1005:Electronic circuit
401:Programmable logic
114:associative memory
57:used to implement
43:
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1321:Digital telephone
1292:Computer hardware
1259:Synchronous logic
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704:Texas Instruments
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124:for this device.
102:Texas Instruments
80:PLAs differ from
16:(Redirected from
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208:read-only memory
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152:Program the PLA.
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53:) is a kind of
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358:on 2013-01-15
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238:The earliest
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233:state diagram
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1285:Applications
1079:
822:LatticeMico8
812:ARM Cortex-M
788:Intellectual
446:
360:. Retrieved
356:the original
347:
336:the original
327:
303:
292:
283:
277:
240:Commodore 64
237:
226:
223:Applications
211:
203:
201:
179:INPUT BUFFER
155:
121:
104:developed a
99:
79:
50:
46:
44:
1390:Gate arrays
1015:Memory cell
852:Open-source
799:Proprietary
608:Flow to HDL
430:Logic block
348:Java Applet
1379:Categories
1364:Runt pulse
1336:television
1030:Logic gate
975:Transistor
967:Components
827:MicroBlaze
778:Simulators
758:Xilinx ISE
362:2010-04-07
269:References
258:Gate array
182:AND MATRIX
174:5TH BLOCK
112:read-only
1220:Placement
1010:Flip-flop
990:Capacitor
897:Microwatt
892:Libre-SOC
887:Power ISA
870:OpenCores
832:PicoBlaze
639:Accellera
632:Companies
504:Languages
185:OR MATRIX
171:4TH BLOCK
168:3RD BLOCK
165:2ND BLOCK
162:1ST BLOCK
100:In 1970,
84:devices (
985:Inductor
980:Resistor
875:OpenRISC
790:property
768:ModelSim
746:Software
720:Hardware
713:Products
699:Synopsys
669:Infineon
644:Achronix
603:C to HDL
568:Handel-C
408:Concepts
247:See also
229:datapath
66:AND gate
62:circuits
1225:Routing
1059:(3D IC)
842:Nios II
732:Stratix
694:Siemens
679:Lattice
664:Cadence
558:SystemC
512:Verilog
328:cmsc311
137:) form.
96:History
70:OR gate
1202:Design
1138:Theory
1124:(ASIC)
1118:(FPOA)
1112:(FPGA)
1106:(CPLD)
1071:(EPLD)
904:RISC-V
763:Vivado
737:Virtex
623:Chisel
588:PALASM
472:Xputer
1309:radio
1130:(TPU)
1100:(GAL)
1094:(PAL)
1088:(PLD)
1082:(PLA)
1065:(ECL)
1048:(HIC)
674:Intel
654:Aldec
613:MyHDL
539:VITAL
212:every
204:could
1042:(IC)
880:1200
837:Nios
817:LEON
618:ELLA
598:CUPL
593:ABEL
573:Lola
563:AHDL
529:VHDL
462:PSoC
442:EPLD
437:CPLD
425:FPGA
415:ASIC
217:6502
106:mask
90:GALs
88:and
86:PALs
909:Zet
860:JOP
807:ARC
773:VTR
727:iCE
689:NXP
659:Arm
649:AMD
583:UPF
578:PSL
551:DPI
534:AMS
522:AMS
457:GAL
452:PAL
447:PLA
420:SoC
110:IBM
51:PLA
1381::
350:.
346:.
330:.
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77:.
45:A
951:e
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517:A
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49:(
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20:)
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
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