501:. J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine-generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA. Additional instructions are easy to add. J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support. Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire in 2016–2017.
2174:
279:
were only 16 general registers, requiring four bits for the source and another four for the destination; however some instructions have an implied R0, R15, or a system register as an extra operand. The instruction opcode is four, eight, twelve, or sixteen bits long, and the remaining four-bit fields are used for register or immediate operands in various ways: there are twelve classes of instructions, for a total of 142 instructions in SH-2.
1711:
2186:
201:
586:
702:
792:
231:, with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, a "long multiply" (multiplying two 32-bit registers to produce a 64-bit product) might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models.
391:(jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5;
278:
and the implementation cost of cache. As of 2023, code density is still important for small embedded systems and massively multicore processors. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value. In the original SuperH ISA, there
238:
concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that
1029:
Hitachi created the SH family of processors and developed its first four major iterations, but has worked with ST since 1997, when the companies agreed to share a common high-end microprocessor road map. They jointly developed the 32-bit SH4 RISC processor core, and began development of the SH5
635:
SH-2A – The SH-2A core is an extension of the SH-2 core including a few extra instructions but most importantly moving to a superscalar architecture (it is capable of executing more than one instruction in a single cycle) and two five-stage pipelines. It also incorporates 15 register banks to
382:
The SH-5 design supported two modes of operation: SHcompact mode, which is equivalent to the user-mode instructions of the SH-4 instruction set; and SHmedia mode, which is very different in that it uses 32-bit instructions with sixty-four 64-bit integer registers and
254:
The SH-1 was the basic model, supporting a total of 56 instructions. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions. The SH-1 and the SH-2 were used in the
375:, with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores. Renesas Technology later became Renesas Electronics, following their merger with
423:
and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms. The system-on-chip products based on SH-3, SH-4 and SH-4A microprocessors were subsequently replaced by newer generations based on licensed CPU cores from
406:
The last evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which formed a kind of instruction set superset of the previous architectures, and added support for
726:
Today the SH-2 family stretches from 32 KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.
363:
SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. The earlier SH-1 through 3 remained the property of
Hitachi.
431:
As of 2021, the SH72xx microcontrollers based on the SH-2A continue to be marketed by
Renesas with guaranteed availability until February 2029, along with newer products based on several other architectures including
159:
to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a
636:
facilitate an interrupt latency of 6 clock cycles. It is also strong in motor control application but also in multimedia, car audio, powertrain, automotive body control and office + building automation
155:
Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the
807:
game systems. It includes a much more powerful floating-point unit and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.
882:
144:
At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. Using smaller instructions had consequences: the
239:
didn't include hardware support. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication; the SH-2 supported
148:
was smaller and instructions were generally two-operand format. However for the market the SuperH was aimed at, this was a small price to pay for the improved memory and
1030:
architecture, which will now be completed by SuperH. SuperH's initial product will be the SH4 core. Earlier SH versions will not be part of the spin-off agreement.
978:
3530:
763:
The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as
689:
SH-X – mainstream core used in various flavours (with/without DSP or FPU unit) in engine control unit, car multimedia equipment, set-top boxes or mobile phones
1103:
403:
processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.
302:(MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68. The SH-3 was
2502:
4445:
3641:
2824:
1182:
3343:
1409:
1231:
317:-type DSP engine, this core unified the DSP and the RISC processor world. A derivative of the DSP was also used with the original SH-2 core.
2621:
2224:
1043:"SuperH, Inc. formed by Hitachi and STMicroelectronics to Boost the Proliferation of SuperH Cores in Embedded Microprocessor Applications"
3500:
3066:
2883:
608:
SH-2 – used in microcontrollers with higher performance requirements, networking applications, and also in video game consoles, like the
3854:
890:
4850:
1300:
2846:
1200:
4814:
3495:
3567:
1594:
804:
4893:
3849:
3320:
1866:
1042:
999:
313:
extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated
856:
Almost no non-simulated SH-5 hardware was ever released, and, unlike the still-live SH-4, support for SH-5 was dropped from
709:
The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware
4264:
3388:
2651:
2495:
428:, with many of the existing models still marketed and sold until March 2025 through the Renesas Product Longevity Program.
1351:
4438:
4274:
3415:
1783:
4716:
4539:
4457:
2542:
274:
instructions for better code density than 32-bit instructions, which was important at the time due to the high cost of
4495:
1326:
4903:
4888:
4820:
4699:
4575:
4465:
3582:
3410:
3383:
2762:
1520:
1402:
384:
114:
4838:
4830:
4469:
4397:
3960:
2853:
2819:
2814:
2733:
2698:
2233:
2217:
822:
666:
hardware's CPU, also made use of this CPU. The Korg
Electribe EMX and ESX music production units also use the SH-3.
4844:
1157:
723:
It provides 16 general-purpose registers, a vector-base register, global-base register, and a procedure register.
4913:
4372:
4269:
3670:
3577:
3378:
2599:
2488:
1921:
1891:
692:
SH-Mobile – SuperH Mobile
Application Processor; designed to offload application processing from the baseband LSI
830:
64-bit external data bus with 32-bit memory addressing, allowing a maximum of 4 GB addressable memory (see
4431:
3398:
3117:
2552:
2073:
2057:
1856:
1581:
814:
FPU with four floating-point multipliers, supporting 32-bit single-precision and 64-bit double-precision floats
471:
735:
The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006.
504:
Several features of SuperH have been cited as motivations for designing new cores based on this architecture:
4918:
4908:
3572:
3420:
3393:
3254:
2868:
2829:
2686:
669:
SH-3-DSP – used mainly in multimedia terminals and networking applications, also in printers and fax machines
4527:
4898:
4883:
4009:
3771:
3247:
3208:
2863:
2858:
2792:
2604:
2119:
1881:
1395:
516:
118:
17:
3636:
3333:
3031:
2728:
2210:
2114:
1571:
2202:
573:
CPU and SoC RTL generation and integration tools, producing FPGA and ASIC portable RTL and documentation
4724:
4674:
4638:
4286:
3933:
3350:
2841:
2809:
2579:
2567:
2547:
1931:
161:
4789:
4745:
4600:
4483:
4377:
4340:
4330:
2718:
1817:
1734:
1437:
1057:
554:
437:
408:
388:
310:
799:
The SH-4 is a RISC CPU and was developed for primary use in multimedia applications, such as Sega's
4392:
3799:
3735:
3712:
3562:
3524:
3360:
3310:
3305:
2782:
2676:
2584:
2190:
1775:
1563:
1368:
1175:
282:
Delayed branches are introduced for both SH-1 and SH-2. Unconditional branch instructions have one
1224:
4795:
4500:
4490:
4345:
4128:
4022:
3986:
3903:
3887:
3729:
3518:
3477:
3465:
3328:
3242:
3163:
2928:
2589:
2532:
2287:
1770:
857:
764:
710:
576:
Clean, modern design with open source design, generation, simulation and verification environment
314:
1124:
1000:"360-MIPS SuperH RISC Processor Enables Personal Access Systems SH7750 Launches the SH-4 Series"
4563:
4151:
4123:
4033:
3998:
3747:
3741:
3723:
3457:
3451:
3355:
3259:
3150:
3089:
2951:
2594:
2461:
2124:
360:
299:
659:
4765:
4588:
4325:
4234:
3980:
3692:
3510:
3269:
3237:
3195:
3107:
2908:
2723:
2713:
2703:
2693:
2663:
2646:
2511:
1655:
1513:
818:
62:
4806:
4777:
4522:
4355:
4291:
3877:
3599:
3489:
3436:
2968:
2681:
2537:
2519:
2408:
2292:
1607:
780:
745:
180:
1207:
303:
8:
4759:
4656:
4650:
4402:
4387:
4207:
4058:
4040:
4004:
3992:
3646:
3593:
3370:
3286:
3168:
3023:
2918:
2777:
2326:
1982:
1827:
1418:
617:
468:
420:
396:
372:
368:
344:
169:
294:
A few years later, the SH-3 core was added to the family; new features included another
4259:
4251:
4103:
4078:
3882:
3757:
3281:
3222:
3102:
2834:
2562:
2352:
2134:
1886:
1748:
1647:
1602:
673:
329:
145:
4729:
4507:
4212:
4179:
4095:
4027:
3928:
3918:
3908:
3839:
3834:
3829:
3752:
3681:
3587:
3547:
3180:
3130:
3080:
3056:
2938:
2878:
2873:
2755:
2671:
2311:
2052:
1992:
1876:
1758:
1676:
1619:
1020:
827:
128-bit floating-point bus allowing 3.2 GB/sec transfer rate from the data cache
625:
524:
457:
400:
217:
672:
SH-4 – used whenever high performance is required such as car multimedia terminals,
4691:
4382:
4315:
4301:
4156:
4063:
4017:
3824:
3819:
3814:
3809:
3804:
3794:
3664:
3631:
3542:
3537:
3446:
3298:
3293:
3276:
3264:
3203:
2767:
2745:
2631:
2609:
2527:
2437:
2178:
2078:
1987:
1906:
1807:
1640:
1506:
1248:
776:
717:
543:
535:
520:
433:
392:
341:
165:
1003:
4734:
4454:
4296:
4281:
4229:
4133:
4108:
3945:
3938:
3789:
3784:
3779:
3718:
3626:
3616:
3338:
3173:
3125:
2888:
2772:
2740:
2641:
2636:
2557:
2282:
2163:
2129:
1822:
1355:
831:
602:
376:
213:
149:
138:
130:
72:
4407:
4241:
4224:
4217:
4113:
3970:
3707:
3621:
3552:
3135:
3097:
3046:
3041:
3036:
2750:
2574:
2447:
2418:
2274:
2144:
2139:
2109:
2042:
1997:
1901:
1802:
1624:
1280:
940:
643:
market, used later in many consumer applications requiring DSP performance for
570:
Availability of low cost hardware development platform for zero cost FPGA tools
134:
1634:
4877:
4423:
4202:
4118:
3158:
3140:
2933:
2626:
2306:
2258:
2253:
2083:
2047:
1812:
1681:
1557:
783:
controllers and peripherals dedicated to automotive powertrain applications.
651:
460:
of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired
3061:
2088:
4412:
4350:
4166:
4143:
3955:
3676:
2614:
2395:
2302:
2007:
1972:
1871:
1753:
640:
509:
320:
Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.
264:
156:
179:
for the SuperH architecture expired and the SH-2 CPU was reimplemented as
4753:
4197:
4161:
3872:
3844:
3702:
3557:
2480:
2413:
2390:
2232:
2012:
2002:
1967:
1916:
1896:
1686:
1552:
1482:
1262:
681:
658:
applications and market for many years in the car navigation market. The
609:
348:
337:
256:
1176:"Exploring the Limits of Code Density (Tech Report with Newest Results)"
4083:
4073:
4068:
4050:
3950:
3923:
3185:
3018:
2988:
2708:
2432:
2428:
2365:
2022:
2017:
1150:
663:
655:
531:
461:
283:
84:
1387:
1308:. STMicroelectronics and Hitachi Ltd. 12 September 2002. ADCS 7182230F
498:
227:
In the past, this sort of design problem would have been solved using
4783:
4705:
4546:
4478:
4174:
4171:
3913:
2983:
2961:
2423:
2385:
2369:
2321:
2104:
1952:
1477:
800:
677:
419:
Since 2010, the SuperH CPU cores, architecture and products are with
333:
295:
228:
2451:
1346:
742:
Superscalar architecture: execution of 2 instructions simultaneously
164:
and is also used by other companies, the most notable example being
4189:
3008:
2469:
2316:
2297:
2277:
1977:
1467:
768:
613:
453:
425:
260:
221:
775:
and more as well as more application-specific peripherals such as
597:
SH-1 – used in microcontrollers for deeply embedded applications (
4668:
4551:
4534:
4517:
2998:
2956:
2465:
2456:
2357:
2248:
2159:
Now integrated into other
Hitachi divisions or business groupings
1957:
1629:
1612:
1587:
1576:
1529:
1089:
1085:
464:). Subsequently, a design walkthrough was presented at ELC 2016.
351:). Standard chips based on the SH-4 were introduced around 1998.
251:, whereas the SH-1 would cause a trap if these were encountered.
209:
126:
122:
39:
4771:
4594:
3013:
2943:
2442:
2362:
2342:
1763:
1696:
1341:
845:
There is no FPU in the custom SH-4 made for Casio, the SH7305.
621:
598:
494:
479:
306:, running in either big-endian or little-endian byte ordering.
271:
200:
176:
111:
713:(MAC) block for DSP algorithms and has a five-stage pipeline.
585:
399:
mode (ARM licensed several patents from SuperH for Thumb) and
332:(STM) started collaborating on the design of the SH-4 for the
4680:
4618:
4558:
3471:
3003:
2973:
2403:
2400:
2347:
1962:
1947:
1861:
1487:
1361:
650:
SH-3 – used for mobile and handheld applications such as the
629:
539:
1337:
791:
701:
4662:
4644:
4630:
4624:
4612:
4606:
4512:
4335:
3483:
3403:
2993:
2337:
2329:
1911:
1691:
1660:
1472:
1452:
1442:
1432:
644:
513:
490:
486:
482:
475:
441:
275:
235:
1498:
756:
15 register banks for interrupt response in 6 cycles.
234:
One of the key realizations during the development of the
4579:
2923:
2913:
1462:
1457:
1021:"STMicro, Hitachi plan new company to develop RISC cores"
837:
Built-in interrupt, DMA, and power management controllers
772:
547:
616:
add-on. The SH-2 has also found home in many automotive
212:
in the early 1990s. The design concept was for a single
208:
The SuperH processor core family was first developed by
1384:
A 15-part series on programming for the microprocessor.
1263:"GCC 7 Release Series Changes, New Features, and Fixes"
959:
561:
for a dual-core J2 core on TSMC's 180 nm process).
979:"SH7020 and SH7021 Hardware ManualSuperH™ RISC engine"
923:
921:
919:
686:
SH-5 – used in high-end 64-bit multimedia applications
564:
Patent- and royalty-free (BSD-licensed) implementation
1332:
1128:
911:
527:
important for cache and memory bandwidth performance
916:
883:"The Story of the Hitachi SH-2 and the Sega Saturn"
387:instructions. In SHmedia mode the destination of a
1329:, Products, Tools, Manuals, App.Notes, Information
79:SH-2A and newer: mixed 16- and 32-bit instructions
452:The last of the SH-2 patents expired in 2014. At
4875:
557:costs now that the patents are expiring (around
1282:SuperH RISC Engine SH-1/SH-2 Programming Manual
4702:(ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)
4453:
4439:
2496:
2218:
1514:
1403:
1083:
1119:
1117:
3501:Computer performance by orders of magnitude
1173:
1058:"Renesas to take over SuperH core business"
4446:
4432:
2510:
2503:
2489:
2225:
2211:
1521:
1507:
1410:
1396:
1167:
456:Japan 2015, j-core developers presented a
359:In early 2001, Hitachi and STM formed the
1776:Johnson Controls-Hitachi Air Conditioning
1114:
834:) with a transfer rate of 800 MB/sec
593:The family of SuperH CPU cores includes:
414:
1288:. Hitachi Americal Ltd. 3 September 1996
1198:
941:"CP System III (CPS3) Hardware (Capcom)"
790:
738:New features on the SH-2A core include:
700:
584:
478:code for the J2 core has been proven on
199:
4762:(2008); ARMv8 also has AES instructions
1595:Hitachi Construction Machinery (Europe)
1417:
1279:
965:
927:
27:Instruction set architecture by Hitachi
14:
4876:
1225:"SH-5 CPU Core, Volume1: Architecture"
1086:"Resurrecting the SuperH architecture"
1079:
1077:
1075:
1073:
1071:
1055:
4427:
2484:
2206:
1502:
1391:
1015:
1013:
639:SH-DSP – initially developed for the
3472:Floating-point operations per second
2185:
1369:"The SuperH-3, part 1: Introduction"
1366:
753:Mixed 16-bit and 32-bit instructions
340:(2-way) instruction execution and a
1818:Casio Hitachi Mobile Communications
1784:Tata Hitachi Construction Machinery
1692:Hitachi Global Storage Technologies
1068:
1056:Clarke, Peter (28 September 2004).
497:process, and is capable of booting
24:
1104:""SuperH RISC Engine Family MCUs""
1010:
841:
567:Full and vibrant community support
25:
4930:
1320:
115:reduced instruction set computing
4862:Suspended extensions' dates are
4398:Semiconductor device fabrication
2234:Reduced instruction set computer
2184:
2173:
2172:
1709:
1352:DCTP - Hitachi 200 MHz SH-4
1237:from the original on 2009-03-20.
1188:from the original on 2015-07-13.
1163:from the original on 2016-06-17.
204:SH-2 on Sega 32X and Sega Saturn
195:
4373:History of general-purpose CPUs
2600:Nondeterministic Turing machine
1922:Stacked Volumetric Optical Disk
1367:Chen, Raymond (5 August 2019).
1362:in-progress Debian port for SH4
1358: (archived August 10, 2016)
1273:
1255:
1241:
1217:
1201:"Korg EMX / ESX Service Manual"
1192:
1143:
1096:
1084:Nathan Willis (June 10, 2015).
1049:
1002:. November 1997. Archived from
853:The SH-5 is a 64-bit RISC CPU.
2553:Deterministic finite automaton
2074:Hitachi Kashiwa Soccer Stadium
1867:Adaptable Modular Storage 2000
1582:Hitachi Construction Machinery
1035:
992:
971:
933:
905:
875:
371:formed a joint-venture called
175:In 2015, many of the original
13:
1:
4894:Instruction set architectures
3344:Simultaneous and heterogenous
1347:Linux SuperH development list
1199:Kuwabara, M. (25 July 2019).
1174:V.M. Weaver (17 March 2015).
863:
4028:Integrated memory controller
4010:Translation lookaside buffer
3209:Memory dependence prediction
2652:Random-access stored program
2605:Probabilistic Turing machine
2120:Hitachi Data Systems History
868:
823:matrix–vector multiplication
716:The SH-2 has a cache on all
354:
119:instruction set architecture
7:
3484:Synaptic updates per second
2115:Hitachi 3Tours Championship
1572:Hitachi Canadian Industries
1528:
1249:"Wasabi SH-5 Press Release"
1151:"j-core Design Walkthrough"
309:The SH-3 core also added a
184:
10:
4935:
3888:Heterogeneous architecture
2810:Orthogonal instruction set
2580:Alternating Turing machine
2568:Quantum cellular automaton
1932:Universal Storage Platform
1302:SH-4 CPU Core Architecture
190:
162:compressed instruction set
125:and currently produced by
4860:
4829:
4805:
4743:
4715:
4690:
4574:
4464:
4378:Microprocessor chronology
4365:
4341:Dynamic frequency scaling
4314:
4250:
4188:
4142:
4094:
4049:
3969:
3896:
3865:
3770:
3691:
3655:
3609:
3509:
3496:Cache performance metrics
3435:
3369:
3319:
3230:
3221:
3194:
3149:
3116:
3088:
3079:
2899:
2802:
2791:
2662:
2518:
2378:
2267:
2241:
2153:
2097:
2066:
2035:
1940:
1849:
1840:
1795:
1735:GE Hitachi Nuclear Energy
1727:
1718:
1707:
1669:
1545:
1536:
1425:
889:. Renesas. Archived from
786:
580:
512:compared to other 32-bit
447:
409:symmetric multiprocessing
395:processors have a 16-bit
248:
244:
240:
93:
83:
77:SH-2: 16-bit instructions
71:
61:
53:
45:
35:
4904:Renesas microcontrollers
4889:Embedded microprocessors
4659:(FMA4: 2011, FMA3: 2012)
4393:Hardware security module
3736:Digital signal processor
3713:Graphics processing unit
3525:Graphics processing unit
1564:Hitachi Cable Manchester
1127:. j-core. Archived from
730:
620:applications, including
458:cleanroom reimplemention
347:(particularly suited to
4717:Compressed instructions
4346:Dynamic voltage scaling
4129:Memory address register
4023:Branch target predictor
3987:Address generation unit
3730:Physics processing unit
3519:Central processing unit
3478:Transactions per second
3466:Instructions per second
3389:Array processing (SIMT)
2533:Stored-program computer
1771:Hitachi-LG Data Storage
1630:Hitachi Medical Systems
848:
810:SH-4 features include:
696:
323:
289:
129:. It is implemented by
4914:32-bit microprocessors
4152:Hardwired control unit
4034:Memory management unit
3999:Memory management unit
3748:Secure cryptoprocessor
3742:Tensor Processing Unit
3724:Vision processing unit
3458:Cycles per instruction
3452:Instructions per cycle
3399:Associative processing
3090:Instruction pipelining
2512:Processor technologies
2125:The Hitachi Foundation
796:
706:
590:
415:Continued availability
300:memory management unit
205:
4235:Sum-addressed decoder
3981:Arithmetic logic unit
3108:Classic RISC pipeline
3062:Epiphany architecture
2909:Motorola 68000 series
1656:Horizon Nuclear Power
1333:J-core Open Processor
912:J-core Open Processor
819:dot-product operation
794:
750:Two 5-stage pipelines
704:
588:
367:In 2003, Hitachi and
328:In 1997, Hitachi and
203:
97:Yes, and royalty-free
4919:Open microprocessors
4909:Open-source hardware
4807:Transactional memory
4356:Performance per watt
3934:replacement policies
3600:Package on a package
3490:Performance per watt
3394:Pipelined processing
3164:Tomasulo's algorithm
2969:Clipper architecture
2825:Application-specific
2538:Finite-state machine
2236:(RISC) architectures
1608:Hitachi Data Systems
746:Harvard architecture
216:(ISA) that would be
181:open source hardware
4899:Japanese inventions
4884:SuperH architecture
4388:Digital electronics
4041:Instruction decoder
3993:Floating-point unit
3647:Soft microprocessor
3594:System in a package
3169:Reservation station
2699:Transport-triggered
1983:Hitachi Flora Prius
1828:Renesas Electronics
1620:Hitachi Electronics
1419:Renesas Electronics
1108:Renesas Electronics
711:multiply–accumulate
676:, most notably the
674:video game consoles
618:engine control unit
553:Extremely low ASIC
421:Renesas Electronics
369:Mitsubishi Electric
345:floating-point unit
220:across a series of
121:(ISA) developed by
32:
4260:Integrated circuit
4104:Processor register
3758:Baseband processor
3103:Operand forwarding
2563:Cellular automaton
2135:Hitachi SunRockers
1887:Hitachi Magic Wand
1841:Products, services
1719:Joint ventures and
1648:Hitachi Rail Italy
1603:Hitachi Consulting
1265:. 2 February 2018.
817:4D floating-point
797:
707:
591:
373:Renesas Technology
330:STMicroelectronics
206:
30:
4871:
4870:
4421:
4420:
4310:
4309:
3929:Instruction cache
3919:Scratchpad memory
3766:
3765:
3753:Network processor
3682:Network on a chip
3637:Ultra-low-voltage
3588:Multi-chip module
3431:
3430:
3217:
3216:
3204:Branch prediction
3181:Register renaming
3075:
3074:
3057:VISC architecture
2879:Quantum computing
2874:VISC architecture
2756:Secondary storage
2672:Microarchitecture
2632:Register machines
2478:
2477:
2200:
2199:
2053:Hiroaki Nakanishi
2031:
2030:
1993:Hitachi Hatsukaze
1877:Hitachi Starboard
1836:
1835:
1705:
1704:
1496:
1495:
1373:The Old New Thing
968:, pp. 30–33.
662:, similar to the
218:upward compatible
172:instruction set.
101:
100:
16:(Redirected from
4926:
4692:Bit manipulation
4448:
4441:
4434:
4425:
4424:
4383:Processor design
4275:Power management
4157:Instruction unit
4018:Branch predictor
3967:
3966:
3665:System on a chip
3607:
3606:
3447:Transistor count
3371:Flynn's taxonomy
3228:
3227:
3086:
3085:
2889:Addressing modes
2800:
2799:
2746:Memory hierarchy
2610:Hypercomputation
2528:Abstract machine
2505:
2498:
2491:
2482:
2481:
2227:
2220:
2213:
2204:
2203:
2188:
2187:
2176:
2175:
2167:
2079:Hitachi, Ibaraki
2058:Takashi Kawamura
1907:Hitachi TrueCopy
1847:
1846:
1808:Alaxala Networks
1788:
1780:
1745:
1739:
1725:
1724:
1713:
1712:
1650:
1643:
1641:Hitachi Rail STS
1616:
1597:
1590:
1566:
1543:
1542:
1523:
1516:
1509:
1500:
1499:
1412:
1405:
1398:
1389:
1388:
1383:
1381:
1380:
1316:
1314:
1313:
1307:
1296:
1294:
1293:
1287:
1267:
1266:
1259:
1253:
1252:
1245:
1239:
1238:
1236:
1229:
1221:
1215:
1214:
1213:on 13 July 2019.
1212:
1206:. Archived from
1205:
1196:
1190:
1189:
1187:
1180:
1171:
1165:
1164:
1162:
1155:
1147:
1141:
1140:
1138:
1136:
1121:
1112:
1111:
1100:
1094:
1093:
1081:
1066:
1065:
1053:
1047:
1046:
1039:
1033:
1032:
1027:. 3 April 2001.
1017:
1008:
1007:
1006:on 5 March 2016.
996:
990:
989:
987:
986:
975:
969:
963:
957:
956:
954:
952:
945:www.system16.com
937:
931:
925:
914:
909:
903:
902:
900:
898:
879:
844:
795:Hitachi SH-4 CPU
705:Hitachi SH-2 CPU
647:compression etc.
603:major appliances
589:Hitachi SH-3 CPU
560:
544:Windows Embedded
536:operating system
489:manufactured on
336:. SH-4 featured
250:
246:
242:
139:embedded systems
131:microcontrollers
49:32-bit (32 → 64)
33:
29:
21:
4934:
4933:
4929:
4928:
4927:
4925:
4924:
4923:
4874:
4873:
4872:
4867:
4856:
4825:
4801:
4739:
4711:
4686:
4570:
4460:
4455:Instruction set
4452:
4422:
4417:
4403:Tick–tock model
4361:
4317:
4306:
4246:
4230:Address decoder
4184:
4138:
4134:Program counter
4109:Status register
4090:
4045:
4005:Load–store unit
3972:
3965:
3892:
3861:
3762:
3719:Image processor
3694:
3687:
3657:
3651:
3627:Microcontroller
3617:Embedded system
3605:
3505:
3438:
3427:
3365:
3315:
3213:
3190:
3174:Re-order buffer
3145:
3126:Data dependency
3112:
3071:
2901:
2895:
2794:
2793:Instruction set
2787:
2773:Multiprocessing
2741:Cache hierarchy
2734:Register/memory
2658:
2558:Queue automaton
2514:
2509:
2479:
2474:
2374:
2263:
2237:
2231:
2201:
2196:
2164:Western Digital
2157:
2149:
2130:Hitachi Sundiva
2093:
2062:
2027:
1936:
1842:
1832:
1823:Nippon Columbia
1791:
1786:
1778:
1743:
1742:Hitachi Astemo
1737:
1720:
1714:
1710:
1701:
1665:
1646:
1639:
1610:
1593:
1586:
1577:Hitachi Capital
1562:
1538:
1532:
1527:
1497:
1492:
1421:
1416:
1378:
1376:
1356:Wayback Machine
1323:
1311:
1309:
1305:
1299:
1291:
1289:
1285:
1276:
1271:
1270:
1261:
1260:
1256:
1251:. 8 March 2016.
1247:
1246:
1242:
1234:
1227:
1223:
1222:
1218:
1210:
1203:
1197:
1193:
1185:
1178:
1172:
1168:
1160:
1153:
1149:
1148:
1144:
1134:
1132:
1131:on May 11, 2016
1123:
1122:
1115:
1102:
1101:
1097:
1082:
1069:
1054:
1050:
1041:
1040:
1036:
1019:
1018:
1011:
998:
997:
993:
984:
982:
981:. p. 19,48
977:
976:
972:
964:
960:
950:
948:
939:
938:
934:
926:
917:
910:
906:
896:
894:
887:www.sega-16.com
881:
880:
876:
871:
866:
851:
832:Byte addressing
789:
733:
720:-less devices.
699:
583:
558:
450:
417:
377:NEC Electronics
357:
326:
292:
214:instruction set
198:
193:
183:under the name
150:processor cache
135:microprocessors
78:
28:
23:
22:
15:
12:
11:
5:
4932:
4922:
4921:
4916:
4911:
4906:
4901:
4896:
4891:
4886:
4869:
4868:
4864:struck through
4861:
4858:
4857:
4855:
4854:
4848:
4842:
4835:
4833:
4831:Virtualization
4827:
4826:
4824:
4823:
4818:
4811:
4809:
4803:
4802:
4800:
4799:
4793:
4787:
4781:
4775:
4769:
4763:
4757:
4750:
4748:
4741:
4740:
4738:
4737:
4732:
4727:
4721:
4719:
4713:
4712:
4710:
4709:
4703:
4696:
4694:
4688:
4687:
4685:
4684:
4678:
4672:
4666:
4660:
4654:
4648:
4642:
4636:
4628:
4622:
4616:
4610:
4604:
4598:
4592:
4585:
4583:
4572:
4571:
4569:
4568:
4567:
4566:
4556:
4555:
4554:
4544:
4543:
4542:
4532:
4531:
4530:
4525:
4520:
4515:
4505:
4504:
4503:
4498:
4488:
4487:
4486:
4475:
4473:
4462:
4461:
4451:
4450:
4443:
4436:
4428:
4419:
4418:
4416:
4415:
4410:
4408:Pin grid array
4405:
4400:
4395:
4390:
4385:
4380:
4375:
4369:
4367:
4363:
4362:
4360:
4359:
4353:
4348:
4343:
4338:
4333:
4328:
4322:
4320:
4312:
4311:
4308:
4307:
4305:
4304:
4299:
4294:
4289:
4284:
4279:
4278:
4277:
4272:
4267:
4256:
4254:
4248:
4247:
4245:
4244:
4242:Barrel shifter
4239:
4238:
4237:
4232:
4225:Binary decoder
4222:
4221:
4220:
4210:
4205:
4200:
4194:
4192:
4186:
4185:
4183:
4182:
4177:
4169:
4164:
4159:
4154:
4148:
4146:
4140:
4139:
4137:
4136:
4131:
4126:
4121:
4116:
4114:Stack register
4111:
4106:
4100:
4098:
4092:
4091:
4089:
4088:
4087:
4086:
4081:
4071:
4066:
4061:
4055:
4053:
4047:
4046:
4044:
4043:
4038:
4037:
4036:
4025:
4020:
4015:
4014:
4013:
4007:
3996:
3990:
3984:
3977:
3975:
3964:
3963:
3958:
3953:
3948:
3943:
3942:
3941:
3936:
3931:
3926:
3921:
3916:
3906:
3900:
3898:
3894:
3893:
3891:
3890:
3885:
3880:
3875:
3869:
3867:
3863:
3862:
3860:
3859:
3858:
3857:
3847:
3842:
3837:
3832:
3827:
3822:
3817:
3812:
3807:
3802:
3797:
3792:
3787:
3782:
3776:
3774:
3768:
3767:
3764:
3763:
3761:
3760:
3755:
3750:
3745:
3739:
3733:
3727:
3721:
3716:
3710:
3708:AI accelerator
3705:
3699:
3697:
3689:
3688:
3686:
3685:
3679:
3674:
3671:Multiprocessor
3668:
3661:
3659:
3653:
3652:
3650:
3649:
3644:
3639:
3634:
3629:
3624:
3622:Microprocessor
3619:
3613:
3611:
3610:By application
3604:
3603:
3597:
3591:
3585:
3580:
3575:
3570:
3565:
3560:
3555:
3553:Tile processor
3550:
3545:
3540:
3535:
3534:
3533:
3522:
3515:
3513:
3507:
3506:
3504:
3503:
3498:
3493:
3487:
3481:
3475:
3469:
3463:
3462:
3461:
3449:
3443:
3441:
3433:
3432:
3429:
3428:
3426:
3425:
3424:
3423:
3413:
3408:
3407:
3406:
3401:
3396:
3391:
3381:
3375:
3373:
3367:
3366:
3364:
3363:
3358:
3353:
3348:
3347:
3346:
3341:
3339:Hyperthreading
3331:
3325:
3323:
3321:Multithreading
3317:
3316:
3314:
3313:
3308:
3303:
3302:
3301:
3291:
3290:
3289:
3284:
3274:
3273:
3272:
3267:
3257:
3252:
3251:
3250:
3245:
3234:
3232:
3225:
3219:
3218:
3215:
3214:
3212:
3211:
3206:
3200:
3198:
3192:
3191:
3189:
3188:
3183:
3178:
3177:
3176:
3171:
3161:
3155:
3153:
3147:
3146:
3144:
3143:
3138:
3133:
3128:
3122:
3120:
3114:
3113:
3111:
3110:
3105:
3100:
3098:Pipeline stall
3094:
3092:
3083:
3077:
3076:
3073:
3072:
3070:
3069:
3064:
3059:
3054:
3051:
3050:
3049:
3047:z/Architecture
3044:
3039:
3034:
3026:
3021:
3016:
3011:
3006:
3001:
2996:
2991:
2986:
2981:
2976:
2971:
2966:
2965:
2964:
2959:
2954:
2946:
2941:
2936:
2931:
2926:
2921:
2916:
2911:
2905:
2903:
2897:
2896:
2894:
2893:
2892:
2891:
2881:
2876:
2871:
2866:
2861:
2856:
2851:
2850:
2849:
2839:
2838:
2837:
2827:
2822:
2817:
2812:
2806:
2804:
2797:
2789:
2788:
2786:
2785:
2780:
2775:
2770:
2765:
2760:
2759:
2758:
2753:
2751:Virtual memory
2743:
2738:
2737:
2736:
2731:
2726:
2721:
2711:
2706:
2701:
2696:
2691:
2690:
2689:
2679:
2674:
2668:
2666:
2660:
2659:
2657:
2656:
2655:
2654:
2649:
2644:
2639:
2629:
2624:
2619:
2618:
2617:
2612:
2607:
2602:
2597:
2592:
2587:
2582:
2575:Turing machine
2572:
2571:
2570:
2565:
2560:
2555:
2550:
2545:
2535:
2530:
2524:
2522:
2516:
2515:
2508:
2507:
2500:
2493:
2485:
2476:
2475:
2473:
2472:
2459:
2454:
2448:Motorola 88000
2445:
2440:
2435:
2426:
2421:
2416:
2411:
2406:
2398:
2393:
2388:
2382:
2380:
2376:
2375:
2373:
2372:
2360:
2355:
2350:
2345:
2340:
2324:
2319:
2314:
2309:
2300:
2295:
2290:
2285:
2280:
2275:Analog Devices
2271:
2269:
2265:
2264:
2262:
2261:
2256:
2251:
2245:
2243:
2239:
2238:
2230:
2229:
2222:
2215:
2207:
2198:
2197:
2195:
2194:
2182:
2169:
2168:
2154:
2151:
2150:
2148:
2147:
2145:Kashiwa Reysol
2142:
2140:Hitachi Rivale
2137:
2132:
2127:
2122:
2117:
2112:
2110:HDMI Licensing
2107:
2101:
2099:
2095:
2094:
2092:
2091:
2086:
2081:
2076:
2070:
2068:
2064:
2063:
2061:
2060:
2055:
2050:
2045:
2043:Namihei Odaira
2039:
2037:
2033:
2032:
2029:
2028:
2026:
2025:
2020:
2015:
2010:
2005:
2000:
1998:Hitachi SR2201
1995:
1990:
1985:
1980:
1975:
1970:
1965:
1960:
1955:
1950:
1944:
1942:
1938:
1937:
1935:
1934:
1929:
1924:
1919:
1914:
1909:
1904:
1902:Hitachi SR8000
1899:
1894:
1892:Multiple units
1889:
1884:
1879:
1874:
1869:
1864:
1859:
1853:
1851:
1844:
1838:
1837:
1834:
1833:
1831:
1830:
1825:
1820:
1815:
1810:
1805:
1803:Agility Trains
1799:
1797:
1793:
1792:
1790:
1789:
1781:
1773:
1768:
1767:
1766:
1761:
1756:
1751:
1740:
1731:
1729:
1722:
1716:
1715:
1708:
1706:
1703:
1702:
1700:
1699:
1694:
1689:
1684:
1679:
1673:
1671:
1667:
1666:
1664:
1663:
1658:
1653:
1652:
1651:
1644:
1632:
1627:
1625:Hitachi Energy
1622:
1617:
1605:
1600:
1599:
1598:
1591:
1579:
1574:
1569:
1568:
1567:
1555:
1549:
1547:
1540:
1534:
1533:
1526:
1525:
1518:
1511:
1503:
1494:
1493:
1491:
1490:
1485:
1480:
1475:
1470:
1465:
1460:
1455:
1450:
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1327:Renesas SuperH
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1321:External links
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4124:Memory buffer
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4119:Register file
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4059:Combinational
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3159:Scoreboarding
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3141:False sharing
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2934:Stanford MIPS
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2795:architectures
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2764:
2763:Heterogeneous
2761:
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2714:Memory access
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2647:Random-access
2645:
2643:
2640:
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2627:Stack machine
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2543:with datapath
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2307:LatticeMico32
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2259:Stanford MIPS
2257:
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2250:
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2240:
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2084:Hitachi Tower
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2048:Kenichi Ohmae
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2024:
2021:
2019:
2016:
2014:
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1537:Divisions and
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893:on 2023-02-27
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163:
158:
153:
151:
147:
146:register file
142:
140:
136:
132:
128:
124:
120:
116:
113:
109:
105:
96:
92:
88:
86:
82:
76:
74:
70:
66:
64:
60:
56:
52:
48:
44:
41:
38:
34:
19:
4863:
4746:cryptography
4633:
4413:Chip carrier
4351:Clock gating
4270:Mixed-signal
4167:Write buffer
4144:Control unit
3956:Clock signal
3695:accelerators
3677:Cypress PSoC
3334:Simultaneous
3151:Out-of-order
2978:
2783:Neuromorphic
2664:Architecture
2622:Belt machine
2615:Zeno machine
2548:Hierarchical
2396:Apollo PRISM
2379:Discontinued
2333:
2303:LatticeMico8
2189:
2177:
2161:
2158:
2008:Hitachi TR.1
1973:Hitachi 6309
1926:
1872:Hitachi DX07
1635:Hitachi Rail
1539:subsidiaries
1447:
1377:. Retrieved
1372:
1310:. Retrieved
1301:
1290:. Retrieved
1281:
1274:Bibliography
1257:
1243:
1219:
1208:the original
1194:
1169:
1145:
1133:. Retrieved
1129:the original
1107:
1098:
1061:
1051:
1037:
1028:
1024:
1004:the original
994:
983:. Retrieved
973:
966:Program 1996
961:
949:. Retrieved
944:
935:
930:, p. 1.
928:Program 1996
907:
895:. Retrieved
891:the original
886:
877:
855:
852:
842:
840:
809:
798:
762:
759:Optional FPU
737:
734:
725:
722:
715:
708:
654:, strong in
641:mobile phone
592:
510:code density
503:
466:
451:
430:
418:
405:
381:
366:
358:
327:
319:
308:
293:
281:
269:
265:Capcom CPS-3
253:
233:
226:
207:
174:
157:machine code
154:
152:efficiency.
143:
107:
103:
102:
18:Renesas SH-3
4730:MIPS16e ASE
4198:Multiplexer
4162:Data buffer
3873:Single-core
3845:bit slicing
3703:Coprocessor
3558:Coprocessor
3439:performance
3361:Cooperative
3351:Speculative
3311:Distributed
3270:Superscalar
3255:Instruction
3223:Parallelism
3196:Speculative
3028:System/3x0
2900:Instruction
2677:Von Neumann
2590:Post–Turing
2391:AMD Am29000
2003:Hitachi T.2
1968:HITAC S-810
1897:Hitachi 917
1882:Locomotives
1553:GlobalLogic
947:. System 16
897:27 February
860:and Linux.
660:Cave CV1000
610:Sega Saturn
555:fabrication
469:open source
349:3D graphics
338:superscalar
298:concept, a
276:main memory
257:Sega Saturn
31:SuperH (SH)
4878:Categories
4458:extensions
4318:management
4213:Multiplier
4074:Logic gate
4064:Sequential
3971:Functional
3951:Clock rate
3924:Data cache
3897:Components
3878:Multi-core
3866:Core count
3356:Preemptive
3260:Pipelining
3243:Bit-serial
3186:Wide-issue
3131:Structural
3053:Tilera ISA
3019:MicroBlaze
2989:ETRAX CRIS
2884:Comparison
2729:Load–store
2709:Endianness
2429:Intel i860
2366:MicroBlaze
2089:Tsūtenkaku
2023:Travelstar
2018:Microdrive
1379:2024-01-22
1312:2020-12-06
1292:2020-12-06
985:2023-12-02
864:References
664:Sega NAOMI
656:Windows CE
626:Mitsubishi
474:-licensed
462:trademarks
361:IP company
284:delay slot
85:Endianness
54:Introduced
4547:Power ISA
4528:MIPS SIMD
4252:Circuitry
4172:Microcode
4096:Registers
3939:coherence
3914:CPU cache
3772:Word size
3437:Processor
3081:Execution
2984:DEC Alpha
2962:Power ISA
2778:Cognitive
2585:Universal
2424:DEC PRISM
2370:PicoBlaze
2322:Power ISA
2105:DKB Group
1953:H8 Family
1135:April 27,
1125:"J Cores"
869:Citations
801:Dreamcast
678:Dreamcast
538:support (
530:Existing
355:Licensing
334:Dreamcast
304:bi-endian
296:interrupt
229:microcode
222:CPU cores
4853:(AMD-Vi)
4190:Datapath
3883:Manycore
3855:variable
3693:Hardware
3329:Temporal
3009:OpenRISC
2704:Cellular
2694:Dataflow
2687:modified
2317:OpenRISC
2298:eSi-RISC
2278:Blackfin
2179:Category
2162:Sold to
1978:Deskstar
1468:R8C Tiny
1426:Products
1232:Archived
1183:Archived
1158:Archived
1062:EE Times
1025:EE Times
951:3 August
779:timers,
769:Ethernet
614:Sega 32X
601:drives,
559:US$ 0.03
532:compiler
519:such as
454:LinuxCon
426:Arm Ltd.
261:Sega 32X
168:for its
73:Encoding
36:Designer
4754:PadLock
4669:AVX-512
4535:PA-RISC
4518:MIPS-3D
4366:Related
4297:Quantum
4287:Digital
4282:Boolean
4180:Counter
4079:Quantum
3840:512-bit
3835:256-bit
3830:128-bit
3673:(MPSoC)
3658:on chip
3656:Systems
3474:(FLOPS)
3287:Process
3136:Control
3118:Hazards
3004:Itanium
2999:Unicore
2957:PowerPC
2682:Harvard
2642:Pointer
2637:Counter
2595:Quantum
2466:PowerPC
2457:PA-RISC
2409:Clipper
2358:Unicore
2327:Renesas
2249:IBM 801
2242:Origins
2191:Commons
1958:HD64180
1941:Defunct
1850:Current
1744:(66.6%)
1728:Current
1677:Clarion
1613:BlueArc
1588:Bradken
1546:Current
1530:Hitachi
1354:at the
1090:LWN.net
652:Jornada
605:, etc.)
499:ÎĽClinux
485:and on
210:Hitachi
191:History
177:patents
127:Renesas
123:Hitachi
117:(RISC)
110:) is a
40:Hitachi
4847:(2006)
4841:(2005)
4817:(2013)
4798:(2021)
4792:(2015)
4786:(2015)
4780:(2013)
4774:(2012)
4772:RDRAND
4768:(2010)
4760:AES-NI
4756:(2003)
4708:(2014)
4683:(2023)
4677:(2022)
4671:(2015)
4665:(2013)
4653:(2009)
4647:(2009)
4641:(2008)
4634:(2007)
4627:(2006)
4621:(2006)
4615:(2004)
4609:(2001)
4603:(1999)
4597:(1998)
4595:3DNow!
4591:(1996)
4302:Switch
4292:Analog
4030:(IMC)
4001:(MMU)
3850:others
3825:64-bit
3820:48-bit
3815:32-bit
3810:24-bit
3805:16-bit
3800:15-bit
3795:12-bit
3632:Mobile
3548:Stream
3543:Barrel
3538:Vector
3527:(GPU)
3486:(SUPS)
3454:(IPC)
3306:Memory
3299:Vector
3282:Thread
3265:Scalar
3067:Others
3014:RISC-V
2979:SuperH
2948:Power
2944:MIPS-X
2919:PDP-11
2768:Fabric
2520:Models
2452:M·CORE
2443:MIPS-X
2363:Xilinx
2353:Sunway
2343:RISC-V
2334:SuperH
2268:Active
2067:Places
2036:People
1927:SuperH
1796:Former
1764:Tokico
1754:Nissin
1749:Keihin
1697:Maxell
1687:Fabrik
1670:Former
1448:SuperH
1375:(blog)
1342:GitHub
1338:J-core
628:, and
622:Subaru
599:CD-ROM
581:Models
495:180 nm
480:Xilinx
448:J Core
440:, and
389:branch
342:vector
272:16-bit
112:32-bit
104:SuperH
63:Design
4845:AMD-V
4766:CLMUL
4725:Thumb
4681:AVX10
4619:SSSE3
4559:SPARC
4479:Alpha
4358:(PPW)
4316:Power
4208:Adder
4084:Array
4051:Logic
4012:(TLB)
3995:(FPU)
3989:(AGU)
3983:(ALU)
3973:units
3909:Cache
3790:8-bit
3785:4-bit
3780:1-bit
3744:(TPU)
3738:(DSP)
3732:(PPU)
3726:(VPU)
3715:(GPU)
3684:(NoC)
3667:(SoC)
3602:(PoP)
3596:(SiP)
3590:(MCM)
3531:GPGPU
3521:(CPU)
3511:Types
3492:(PPW)
3480:(TPS)
3468:(IPS)
3460:(CPI)
3231:Level
3042:S/390
3037:S/370
3032:S/360
2974:SPARC
2952:POWER
2835:TRIPS
2803:Types
2462:POWER
2419:CRISP
2404:AVR32
2401:Atmel
2386:Alpha
2348:SPARC
2098:Other
1963:HITAC
1948:D-VHS
1862:EMIEW
1787:(60%)
1779:(40%)
1759:Showa
1738:(40%)
1488:IEBus
1443:RH850
1306:(PDF)
1286:(PDF)
1235:(PDF)
1228:(PDF)
1211:(PDF)
1204:(PDF)
1186:(PDF)
1179:(PDF)
1161:(PDF)
1154:(PDF)
805:NAOMI
731:SH-2A
680:, or
630:Mazda
540:Linux
508:High
487:ASICs
483:FPGAs
442:RH850
397:Thumb
249:DMULU
245:DMULS
170:Thumb
4851:VT-d
4839:VT-x
4663:AVX2
4645:F16C
4631:SSE5
4625:SSE4
4613:SSE3
4607:SSE2
4576:SIMD
4513:MDMX
4508:MIPS
4496:NEON
4470:RISC
4466:SIMD
4336:ACPI
4069:Glue
3961:FIFO
3904:Core
3642:ASIP
3583:CPLD
3578:FPOA
3573:FPGA
3568:ASIC
3421:SPMD
3416:MIMD
3411:MISD
3404:SWAR
3384:SIMD
3379:SISD
3294:Data
3277:Task
3248:Word
2994:M32R
2939:MIPS
2902:sets
2869:ZISC
2864:NISC
2859:OISC
2854:MISC
2847:EPIC
2842:VLIW
2830:EDGE
2820:RISC
2815:CISC
2724:HUMA
2719:NUMA
2470:ROMP
2438:META
2433:i960
2414:CR16
2338:V850
2330:M32R
2312:MIPS
1912:LS-R
1857:ALiS
1661:JECS
1473:M32R
1453:V850
1433:RL78
1137:2016
953:2019
899:2023
849:SH-5
821:and
803:and
787:SH-4
697:SH-2
645:JPEG
612:and
534:and
525:MIPS
517:ISAs
514:RISC
491:TSMC
476:VHDL
467:The
401:MIPS
385:SIMD
324:SH-4
290:SH-3
263:and
247:and
236:RISC
137:for
133:and
106:(or
94:Open
67:RISC
57:1992
46:Bits
4821:ASF
4815:TSX
4796:TDX
4790:SGX
4784:MPX
4778:SHA
4735:RVC
4706:ADX
4700:BMI
4675:AMX
4657:FMA
4651:XOP
4639:AVX
4601:SSE
4589:MMX
4580:x86
4564:VIS
4552:VMX
4540:MAX
4523:MXU
4501:SVE
4491:ARM
4484:MVI
4331:APM
4326:PMU
4218:CPU
4175:ROM
3946:Bus
3563:PAL
3238:Bit
3024:LMC
2929:ARM
2924:x86
2914:VAX
2293:AVR
2288:ARM
2283:ARC
1483:740
1463:R8C
1458:78K
1340:on
858:GCC
781:TFT
773:USB
765:CAN
718:ROM
548:QNX
523:or
521:ARM
493:'s
472:BSD
434:Arm
393:ARM
315:MAC
311:DSP
241:MUL
166:ARM
4880::
4265:3D
2468:,
2464:,
2450:,
2431:,
2368:,
2336:,
2332:,
2305:,
2013:M6
1917:M8
1478:H8
1438:RX
1371:.
1230:.
1181:.
1156:.
1116:^
1106:.
1088:.
1070:^
1060:.
1023:.
1012:^
943:.
918:^
885:.
771:,
767:,
624:,
546:,
542:,
444:.
438:RX
436:,
411:.
379:.
286:.
267:.
259:,
243:,
224:.
187:.
185:J2
141:.
108:SH
89:Bi
4866:.
4582:)
4578:(
4472:)
4468:(
4447:e
4440:t
4433:v
2504:e
2497:t
2490:v
2226:e
2219:t
2212:v
1615:)
1611:(
1522:e
1515:t
1508:v
1411:e
1404:t
1397:v
1382:.
1315:.
1295:.
1139:.
1110:.
1092:.
1064:.
1045:.
988:.
955:.
901:.
632:.
550:)
20:)
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