43:.) To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool. Specman is a feature of Cadence's new Xcelium simulator, where tighter product integration offers both faster runtime performance and debugs capabilities not available with other HDL simulators. In principle, Specman can co-simulate with any HDL simulator supporting standard PLI or VHPI interface, such as Synopsys's VCS, or Mentor's Questa.
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tool that provides advanced automated functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments written in the
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