471:, for suspending and resuming load address tracking, respectively. While the tracking is suspended, any loads from memory will not be added to the transaction read set. This means that, unless these memory locations were added to the transaction read or write sets outside the suspend region, writes at these locations by other threads will not cause transaction abort. Suspending load address tracking for a portion of code within a transactional region allows to reduce the amount of memory that needs to be tracked for read-write conflicts and therefore increase the probability of successful commit of the transaction.
571:
According to Intel 64 and IA-32 Architectures
Software Developer's Manual from May 2020, Volume 1, Chapter 2.5 Intel Instruction Set Architecture And Features Removed, HLE has been removed from Intel products released in 2019 and later. RTM is not documented as removed. However, Intel 10th generation
501:
Independent research points into
Haswell’s transactional memory most likely being a deferred update system using the per-core caches for transactional data and register checkpoints. In other words, Haswell is more likely to use the cache-based transactional memory system, as it is a much less risky
315:
Restricted
Transactional Memory (RTM) is an alternative implementation to HLE which gives the programmer the flexibility to specify a fallback code path that is executed when a transaction cannot be successfully executed. Unlike HLE, RTM is not backward compatible with processors that do not support
560:
as a mitigation for TSX Asynchronous Abort (TAA) vulnerability. Earlier mitigation for memory ordering issue was removed. By default, with the updated microcode, the processor would still indicate support for RTM but would always abort the transaction. System software is able to detect this mode of
493:
Haswell's L1 data cache has an associativity of eight. This means that in this implementation, a transactional execution that writes to nine distinct locations mapping to the same cache set will abort. However, due to micro-architectural implementations, this does not mean that fewer accesses to
522:
In August 2014, Intel announced that a bug exists in the TSX/TSX-NI implementation on
Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX/TSX-NI feature on affected CPUs via a microcode update. The bug was fixed in F-0 steppings of the vPro-enabled Core
459:
TSX/TSX-NI Suspend Load
Address Tracking (TSXLDTRK) is an instruction set extension that allows to temporarily disable tracking loads from memory in a section of code within a transactional region. This feature extends HLE and RTM, and its support in the processor must be detected separately.
567:
instruction, preventing detection of TSX/TSX-NI by applications. System software may also enable the "Unsupported
Software Development Mode", where RTM is fully active, but in this case RTM usage may be subject to the issues described earlier, and therefore this mode should not be enabled on
485:
Intel's TSX/TSX-NI specification describes how the transactional memory is exposed to programmers, but withholds details on the actual transactional memory implementation. Intel specifies in its developer's and optimization manuals that
Haswell maintains both read-sets and write-sets at the
133:
of transactional code regions. The hardware monitors multiple threads for conflicting memory accesses, while aborting and rolling back transactions that cannot be successfully completed. Mechanisms are provided for software to detect and handle failed transactions.
1228:
BDM53 E-0: X, F-0:, Status: Fixed ERRATA: Intel TSX Instructions Not
Available. 1. Applies to Intel Core M-5Y70 processor. Intel TSX is supported on Intel Core M-5Y70 processor with Intel vPro Technology. Intel TSX is not supported on other processor
45:
support, speeding up execution of multi-threaded software through lock elision. According to different benchmarks, TSX/TSX-NI can provide around 40% faster applications execution in specific workloads, and 4–5 times more database
1006:
871:
Under a complex set of internal timing conditions and system events, software using the Intel TSX/TSX-NI (Transactional
Synchronization Extensions) instructions may observe unpredictable system behavior.
298:
HLE allows optimistic execution of a critical section by skipping the write to a lock, so that the lock appears to be free to other threads. A failed transaction results in execution restarting from the
800:
1150:
The whole "CPU does the fine grained locks" is based upon tagging the L1 (64 B) cachelines and there are 512 of them to be specific (64 x 512 = 32 KB). There is only one "lock tag" per cacheline.
1273:
The
October 2018 microcode update also disabled the HLE instruction prefix of Intel TSX and force all RTM transactions to abort when operating in Intel SGX mode or System Management Mode (SMM).
580:
client processors, which were released in 2020, do not support TSX/TSX-NI, including both HLE and RTM. Engineering versions of Comet Lake processors were still retaining TSX/TSX-NI support.
583:
In Intel Architecture Instruction Set Extensions Programming Reference revision 41 from October 2020, a new TSXLDTRK instruction set extension was documented. It was first included in
537:
processors. As a result of a microcode update, HLE support was disabled in the affected CPUs, and RTM was mitigated by sacrificing one performance counter when used outside of Intel
1010:
1265:
853:"Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium Processor Family, and Desktop Intel Celeron Processor Family: Specification Update (Revision 014)"
1404:
137:
In other words, lock elision through transactional execution uses memory transactions as a fast path where possible, while the slow (fallback) path is still a normal lock.
883:
852:
451:
instruction that returns whether the processor is executing a transactional region. This instruction is supported by the processor if it supports HLE or RTM or both.
106:
Support for TSX/TSX-NI emulation is provided as part of the Intel Software Development Emulator. There is also experimental support for TSX/TSX-NI emulation in a
69:
do not support TSX/TSX-NI. In August 2014, Intel announced a bug in the TSX/TSX-NI implementation on current steppings of Haswell, Haswell-E, Haswell-EP and early
1059:
1320:
1209:
1383:
1341:
1299:
1241:
486:
granularity of a cache line, tracking addresses in the L1 data cache of the processor. Intel also states that data conflicts are detected through the
498:, the L1 cache is shared between the two threads on the same core, so operations in a sibling logical processor of the same core can cause evictions.
1495:
1088:
1185:
545:). System software would have to either effectively disable RTM or update performance monitoring tools not to use the affected performance counter.
1362:
680:
2592:
2154:
95:(KASLR) on all major operating systems. In 2021, Intel released a microcode update that disabled the TSX/TSX-NI feature on CPU generations from
1137:
982:
754:
1266:"Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory Ordering Issue White Paper, June 2021, Revision 1.4"
926:
1501:
1993:
1957:
1847:
1124:
The processor tracks both the read-set addresses and the write-set addresses in the first level data cache (L1 cache) of the processor.
825:
2559:
2035:
617:
343:
instruction explicitly aborts a transaction. Transaction failure redirects the processor to the fallback code path specified by the
1554:
548:
In June 2021, Intel published a microcode update that further disables TSX/TSX-NI on various Xeon and Core processor models from
527:
2080:
316:
it. For backward compatibility, programs are required to detect support for RTM in the CPU before using the new instructions.
122:(HLE) is an instruction prefix-based interface designed to be backward compatible with processors without TSX/TSX-NI support.
1702:
1286:"Intel® Transactional Synchronization Extensions (Intel® TSX) Memory and Performance Monitoring Update for Intel® Processors"
652:
Tomas Karnagel; Roman Dementiev; Ravi Rajwar; Konrad Lai; Thomas Legler; Benjamin Schlegel; Wolfgang Lehner (February 2014).
733:
1792:
2147:
1797:
1787:
2425:
526:
The bug was found and then reported during a diploma thesis in the School of Electrical and Computer Engineering of the
2248:
2166:
2065:
2023:
2204:
2529:
2408:
2284:
2174:
1809:
1782:
1448:
1285:
596:
480:
2547:
2539:
2178:
1886:
584:
2553:
510:(MOB) for the same purpose, possibly also providing multi-versioned transactional memory that is more amenable to
2612:
1473:
390:
Set if another logical processor conflicted with a memory address that was part of the transaction that aborted.
1248:
2140:
2050:
1840:
1775:
1770:
1060:"Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, and 3C"
65:
microarchitecture. Haswell processors below 45xx as well as R-series and K-series (with unlocked multiplier)
2607:
2105:
779:
557:
70:
2236:
2617:
2085:
1952:
1547:
653:
38:
2602:
2040:
681:"Performance Evaluation of Intel Transactional Synchronization Extensions for High Performance Computing"
618:"Performance Evaluation of Intel Transactional Synchronization Extensions for High-Performance Computing"
573:
549:
534:
503:
96:
62:
1891:
568:
production systems. On some systems RTM can't be re-enabled when SGX is active. HLE is always disabled.
2433:
2383:
2347:
1896:
1750:
688:
511:
495:
118:
TSX/TSX-NI provides two software interfaces for designating code regions for transactional execution.
2597:
2498:
2454:
2309:
2192:
1833:
577:
538:
654:"Improving In-Memory Database Index Performance with Intel Transactional Synchronization Extensions"
2060:
2504:
2209:
2199:
2100:
2090:
2018:
1540:
876:
47:
16:
Extension to the x86 instruction set architecture that adds hardware transactional memory support
2622:
2272:
2121:
2045:
1911:
542:
1210:"Intel Core M Processor Family. Specification Update. December 2014. Revision 003. 330836-003"
2474:
2297:
2095:
1947:
1876:
1760:
1677:
901:
562:
130:
126:(RTM) is a new instruction set interface that provides greater flexibility for programmers.
2515:
2486:
2231:
382:
If set, the transaction may succeed on a retry. This bit is always clear if bit 0 is set.
42:
628:
8:
2468:
2365:
2359:
1814:
1765:
1755:
1588:
81:
902:"Intel sticks another nail in the coffin of TSX with feature-disabling microcode update"
615:
2028:
1672:
1479:
1454:
1433:
Proceedings of the 2014 ACM symposium on Principles of distributed computing - PODC '14
951:
66:
1186:"Intel Disables TSX Instructions: Erratum Found in Haswell, Haswell-E/EP, Broadwell-Y"
1112:
709:
494:
the same set are guaranteed to never abort. Additionally, in CPU configurations with
2438:
2216:
2003:
1962:
1444:
1458:
2400:
2013:
1906:
1436:
651:
533:
In October 2018, Intel disclosed a TSX/TSX-NI memory ordering issue found in some
2443:
2163:
2070:
1520:
487:
616:
Richard M. Yoo; Christopher J. Hughes; Konrad Lai; Ravi Rajwar (November 2013).
73:
CPUs, which resulted in disabling the TSX/TSX-NI feature on affected CPUs via a
1697:
1163:
58:
287:
prefix hint can be used both with the instructions listed above, and with the
196:
prefix hint can only be used with the following instructions with an explicit
2586:
2132:
1916:
1712:
1692:
1687:
84:
1440:
1138:"Making Sense of the Intel Haswell Transactional Synchronization eXtensions"
983:"Making Sense of the Intel Haswell Transactional Synchronization eXtensions"
339:
instructions mark the start and the end of a transactional code region; the
1921:
1035:
905:
710:"Benchmarks: Haswell's TSX and Memory Transaction Throughput (HLE and RTM)"
87:
was found by abusing the way TSX/TSX-NI handles transactional faults (i.e.
1526:
2462:
1926:
553:
100:
2008:
1967:
1881:
1707:
1647:
1642:
1598:
88:
1512:
1405:"Intel® Architecture Instruction Set Extensions Programming Reference"
826:"Errata prompts Intel to disable TSX in Haswell, early Broadwell CPUs"
2492:
2414:
2255:
2187:
2075:
2055:
1931:
1901:
1682:
1652:
1189:
986:
74:
1507:
1463:. Software-based improvements to hardware lock-elision in Intel TSX.
1871:
1825:
1722:
1717:
1485:
952:"Supporting Intel Transactional Synchronization Extensions in QEMU"
884:"Breaking Kernel Address Space Layout Randomization with Intel TSX"
414:
Set if an abort occurred during execution of a nested transaction.
1508:
Web Resources about Intel Transactional Synchronization Extensions
801:"Intel Comparison Table of Haswell Pentium, i3, i5, and i7 models"
2377:
2260:
2243:
2226:
1626:
1532:
1513:
x86, microcode: BUG: microcode update that changes x86_capability
1489:
154:
1089:"Intel 64 and IA-32 Architectures Optimization Reference Manual"
2480:
2303:
1745:
1740:
1593:
1583:
145:
Hardware Lock Elision (HLE) adds two new instruction prefixes,
303:-prefixed instruction, but treating the instruction as if the
2389:
2327:
2267:
1977:
1972:
1856:
1578:
1216:
930:
859:
92:
57:
in February 2012, and debuted in June 2013 on selected Intel
54:
2371:
2353:
2339:
2333:
2321:
2315:
2221:
1998:
1804:
1621:
1516:
107:
1083:
1081:
1079:
755:"Transactional memory going mainstream with Intel Haswell"
2288:
1563:
927:"Fun with Intel Transactional Synchronization Extensions"
35:
28:
Transactional Synchronization Extensions New Instructions
433:
argument (only valid if bit 0 set, otherwise reserved).
1076:
949:
1397:
847:
845:
506:
or later may combine this cache-based approach with
454:
1435:. Software-improved hardware lock elision, p. 212.
561:operation and mask support for TSX/TSX-NI from the
502:implementation choice. On the other hand, Intel's
347:instruction, with the abort status returned in the
181:prefixes are ignored on instructions for which the
1384:"Intel® Core™ i7-1068NG7 Processor specifications"
1321:"Intel® Core™ i9-10980HK Processor specifications"
819:
817:
310:
103:, as a mitigation for discovered security issues.
1342:"Intel® Core™ i7-10810U Processor specifications"
1300:"Intel® Core™ i9-10900K Processor specifications"
1054:
1052:
842:
189:are valid, thus enabling backward compatibility.
2584:
1430:
1202:
976:
974:
899:
481:Transactional memory § Available implementations
1363:"Intel® Xeon® W-1290P Processor specifications"
814:
2411:(ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)
2162:
1049:
980:
2148:
1841:
1548:
1029:
1027:
971:
1161:
1036:"Analysis of Haswell's Transactional Memory"
1033:
924:
823:
1183:
1164:"Haswell Transactional Memory Alternatives"
2155:
2141:
1994:Advanced Programmable Interrupt Controller
1958:Intel Communication Streaming Architecture
1848:
1834:
1555:
1541:
1024:
734:"Transactional Synchronization in Haswell"
463:TSXLDTRK introduces two new instructions,
173:). On processors that do not support HLE,
2036:High-bandwidth Digital Content Protection
1431:Afek, Y.; Levy, A.; Morrison, A. (2014).
793:
93:kernel address space layout randomization
1519:, September 2014 (there is also another
1135:
140:
20:Transactional Synchronization Extensions
2471:(2008); ARMv8 also has AES instructions
528:National Technical University of Athens
523:M-5Y70 Broadwell CPU in November 2014.
2593:Computer-related introductions in 2012
2585:
2081:Platform Environment Control Interface
1482:, Linux Plumbers Conference 2012 (PDF)
1136:De Gelas, Johan (September 20, 2012).
398:Set if an internal buffer overflowed.
2136:
1829:
1536:
1113:"Intel TSX implementation properties"
587:processors released in January 2023.
1855:
1094:. Intel. September 2013. p. 446
1065:. Intel. September 2013. p. 342
439:
276:instruction can be used without the
517:
13:
2066:Host Embedded Controller Interface
1562:
1424:
14:
2634:
1492:, January 30, 2013, by Andi Kleen
1486:Lock elision in the GNU C library
1467:
597:Advanced Synchronization Facility
474:
455:TSX Suspend Load Address Tracking
406:Set if debug breakpoint was hit.
319:RTM adds three new instructions:
2571:Suspended extensions' dates are
1271:. Intel. 2021-06-12. p. 5.
1007:"Hardware Lock Elision Overview"
541:mode or System Management Mode (
1376:
1355:
1334:
1313:
1292:
1278:
1258:
1234:
1177:
1155:
1129:
1105:
999:
950:Sebastien Dabdoub; Stephen Tu.
943:
918:
900:Gareth Halfacree (2021-06-29).
893:
687:. November 2013. Archived from
311:Restricted Transactional Memory
153:. These two prefixes reuse the
124:Restricted Transactional Memory
772:
747:
726:
702:
673:
645:
609:
1:
1504:, Volume 1, Chapter 2.5 (PDF)
981:Johan De Gelas (2012-09-20).
603:
53:TSX/TSX-NI was documented by
2024:Active Management Technology
1953:MultiProcessor Specification
1529:, Gentoo, September 19, 2015
1480:Adding lock elision to Linux
1247:. p. 12. Archived from
782:. Tom's Hardware. 2013-06-01
599:– AMD's competing technology
39:instruction set architecture
7:
1219:. December 2014. p. 10
1162:David Kanter (2012-08-21).
1034:David Kanter (2012-08-21).
1009:. intel.com. Archived from
925:Wooyoung Kim (2013-07-25).
824:Scott Wasson (2014-08-12).
590:
113:
10:
2639:
1502:Software Developers Manual
1474:Presentation from IDF 2012
1184:Ian Cutress (2014-08-12).
780:"The Core i7-4770K Review"
512:speculative multithreading
496:Hyper-Threading Technology
478:
447:TSX/TSX-NI provides a new
34:), is an extension to the
2569:
2538:
2514:
2452:
2424:
2399:
2283:
2173:
2114:
1986:
1940:
1864:
1733:
1665:
1635:
1614:
1607:
1571:
1166:. Real World Technologies
1038:. Real World Technologies
307:prefix were not present.
41:(ISA) that adds hardware
2368:(FMA4: 2011, FMA3: 2012)
2061:Serial Digital Video Out
2051:Rapid Storage Technology
2426:Compressed instructions
2106:Ultra Path Interconnect
2091:Platform Controller Hub
2019:Intel Management Engine
1441:10.1145/2611462.2611482
862:. June 2014. p. 46
370:Set if abort caused by
48:transactions per second
2613:Transaction processing
2122:Silicon Photonics Link
2086:QuickPath Interconnect
1496:TSX Optimization Guide
508:memory ordering buffer
2096:System Management Bus
2041:High Definition Audio
1948:Common Building Block
1678:High Bandwidth Memory
141:Hardware Lock Elision
120:Hardware Lock Elision
2608:Transactional memory
2516:Transactional memory
1288:. Intel. 2021-06-12.
736:. Software.intel.com
131:optimistic execution
91:) in order to break
43:transactional memory
2618:Concurrency control
129:TSX/TSX-NI enables
2603:Parallel computing
1521:similar bug report
1498:, Chapter 12 (PDF)
685:supercomputing.org
661:software.intel.com
625:intel-research.net
2580:
2579:
2130:
2129:
2004:Intel Turbo Boost
1963:Intel Inboard 386
1823:
1822:
1661:
1660:
437:
436:
2630:
2598:X86 instructions
2401:Bit manipulation
2157:
2150:
2143:
2134:
2133:
2046:Hub Architecture
2014:Intel Secure Key
1850:
1843:
1836:
1827:
1826:
1612:
1611:
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1550:
1543:
1534:
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714:sisoftware.co.uk
706:
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677:
671:
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667:
658:
649:
643:
642:
640:
639:
633:
627:. Archived from
622:
613:
565:
518:History and bugs
470:
466:
450:
442:
432:
373:
354:
353:
350:
346:
342:
338:
334:
330:
326:
322:
306:
302:
294:
290:
286:
280:prefix as well.
279:
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157:of the existing
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2510:
2448:
2420:
2395:
2279:
2169:
2164:Instruction set
2161:
2131:
2126:
2110:
2071:Hyper-threading
1982:
1936:
1860:
1854:
1824:
1819:
1729:
1657:
1631:
1603:
1589:Radeon Software
1567:
1561:
1527:Intel microcode
1470:
1451:
1427:
1425:Further reading
1422:
1413:
1411:
1407:
1403:
1402:
1398:
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59:microprocessors
26:), also called
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1468:External links
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295:instructions.
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1428:
1410:. Intel. 2020
1406:
1400:
1386:. Intel. 2020
1385:
1379:
1365:. Intel. 2020
1364:
1358:
1344:. Intel. 2020
1343:
1337:
1323:. Intel. 2020
1322:
1316:
1302:. Intel. 2020
1301:
1295:
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1243:
1242:"HiPEAC info"
1237:
1230:
1218:
1211:
1205:
1191:
1187:
1180:
1165:
1158:
1151:
1139:
1132:
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1115:. Intel. 2013
1114:
1108:
1090:
1084:
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1080:
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1013:on 2013-10-29
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691:on 2013-10-29
690:
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634:on 2016-10-24
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374:instruction.
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98:
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90:
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85:timing attack
83:
78:
76:
72:
68:
64:
61:based on the
60:
56:
51:
49:
44:
40:
37:
33:
29:
25:
21:
2572:
2523:
2455:cryptography
2342:
2029:AMT versions
1941:Discontinued
1734:Instructions
1673:Cool'n'Quiet
1432:
1412:. Retrieved
1399:
1388:. Retrieved
1378:
1367:. Retrieved
1357:
1346:. Retrieved
1336:
1325:. Retrieved
1315:
1304:. Retrieved
1294:
1280:
1272:
1260:
1249:the original
1236:
1227:
1221:. Retrieved
1204:
1193:. Retrieved
1179:
1168:. Retrieved
1157:
1149:
1142:. Retrieved
1131:
1123:
1117:. Retrieved
1107:
1096:. Retrieved
1067:. Retrieved
1040:. Retrieved
1015:. Retrieved
1011:the original
1001:
990:. Retrieved
962:. Retrieved
958:
945:
934:. Retrieved
920:
909:. Retrieved
906:The Register
895:
878:
870:
864:. Retrieved
833:. Retrieved
829:
805:. Retrieved
795:
784:. Retrieved
774:
763:. Retrieved
761:. 2012-02-08
759:Ars Technica
758:
749:
738:. Retrieved
728:
717:. Retrieved
713:
704:
693:. Retrieved
689:the original
684:
675:
664:. Retrieved
660:
647:
636:. Retrieved
629:the original
624:
611:
582:
570:
558:Whiskey Lake
547:
532:
525:
521:
507:
500:
492:
484:
462:
458:
446:
359:bit position
357:EAX register
318:
314:
297:
293:MOV mem, imm
289:MOV mem, reg
282:
191:
144:
136:
128:
123:
119:
117:
105:
82:side-channel
79:
52:
31:
27:
23:
19:
18:
2439:MIPS16e ASE
2101:Thunderbolt
1144:23 December
1140:. AnandTech
803:. intel.com
554:Coffee Lake
443:instruction
101:Coffee Lake
89:page faults
80:In 2016, a
2587:Categories
2167:extensions
1968:Intel Play
1907:Skulltrail
1877:Centrino 2
1859:technology
1761:CVT16/F16C
1708:AMD Wraith
1698:Turbo Core
1666:Technology
1599:Xilinx ISE
1566:technology
1414:2020-10-21
1390:2020-10-10
1369:2020-10-10
1348:2020-10-10
1327:2020-10-10
1306:2020-10-10
1223:2014-12-28
1195:2014-08-30
1170:2013-11-14
1119:2013-11-14
1098:2013-11-19
1069:2013-11-19
1042:2013-11-19
1017:2013-10-27
992:2013-10-20
964:2013-11-12
936:2013-11-12
911:2012-10-17
866:2014-08-13
835:2014-08-12
807:2014-02-11
786:2012-06-03
765:2012-02-09
740:2012-02-07
719:2013-11-14
695:2013-11-14
666:2014-03-03
638:2013-11-14
604:References
574:Comet Lake
490:protocol.
479:See also:
422:Reserved.
351:register.
165:prefixes (
2256:Power ISA
2237:MIPS SIMD
2076:Omni-Path
2056:SpeedStep
1902:Ultrabook
1865:Platforms
1693:PowerTune
1688:PowerPlay
1683:PowerNow!
1608:Platforms
1190:AnandTech
987:AnandTech
469:XRESLDTRK
465:XSUSLDTRK
230:CMPXCHG8B
75:microcode
71:Broadwell
2562:(AMD-Vi)
2115:Upcoming
1872:Centrino
1723:Ryzen AI
1636:Obsolete
1572:Software
1459:16645370
591:See also
578:Ice Lake
552:through
362:Meaning
305:XACQUIRE
301:XACQUIRE
285:XRELEASE
200:prefix:
194:XACQUIRE
187:XRELEASE
183:XACQUIRE
151:XRELEASE
147:XACQUIRE
114:Features
77:update.
2463:PadLock
2378:AVX-512
2244:PA-RISC
2227:MIPS-3D
1987:Current
1917:Galileo
1627:GPUOpen
1615:Current
1490:LWN.net
959:mit.edu
889:. 2016.
550:Skylake
535:Skylake
504:Skylake
226:CMPXCHG
155:opcodes
97:Skylake
63:Haswell
50:(TPS).
2556:(2006)
2550:(2005)
2526:(2013)
2507:(2021)
2501:(2015)
2495:(2015)
2489:(2013)
2483:(2012)
2481:RDRAND
2477:(2010)
2469:AES-NI
2465:(2003)
2417:(2014)
2392:(2023)
2386:(2022)
2380:(2015)
2374:(2013)
2362:(2009)
2356:(2009)
2350:(2008)
2343:(2007)
2336:(2006)
2330:(2006)
2324:(2004)
2318:(2001)
2312:(1999)
2306:(1998)
2304:3DNow!
2300:(1996)
1922:Edison
1892:Tablet
1746:3DNow!
1741:X86-64
1713:Virtex
1648:Dragon
1643:Spider
1594:Vivado
1584:AMDGPU
1457:
1447:
431:XABORT
372:XABORT
345:XBEGIN
341:XABORT
333:XBEGIN
331:. The
329:XABORT
321:XBEGIN
272:. The
268:, and
110:fork.
32:TSX-NI
2554:AMD-V
2475:CLMUL
2434:Thumb
2390:AVX10
2328:SSSE3
2268:SPARC
2188:Alpha
1978:MMC-2
1973:MMC-1
1927:Curie
1857:Intel
1653:Horus
1579:AGESA
1476:(PDF)
1455:S2CID
1408:(PDF)
1269:(PDF)
1252:(PDF)
1245:(PDF)
1229:SKUs.
1217:Intel
1213:(PDF)
1092:(PDF)
1063:(PDF)
955:(PDF)
931:Intel
887:(PDF)
860:Intel
856:(PDF)
657:(PDF)
632:(PDF)
621:(PDF)
564:CPUID
449:XTEST
441:XTEST
427:31:24
175:REPNE
159:REPNE
55:Intel
2560:VT-d
2548:VT-x
2372:AVX2
2354:F16C
2340:SSE5
2334:SSE4
2322:SSE3
2316:SSE2
2285:SIMD
2222:MDMX
2217:MIPS
2205:NEON
2179:RISC
2175:SIMD
2009:vPro
1999:CNVi
1897:CULV
1882:Viiv
1805:SSE5
1793:BMI1
1776:FMA3
1771:FMA4
1718:XDNA
1703:ASTC
1622:ROCm
1517:LKML
1445:ISBN
1146:2013
576:and
556:and
467:and
419:23:6
337:XEND
335:and
327:and
325:XEND
291:and
283:The
278:LOCK
274:XCHG
270:XCHG
266:XADD
198:LOCK
192:The
179:REPE
163:REPE
149:and
108:QEMU
67:SKUs
2530:ASF
2524:TSX
2505:TDX
2499:SGX
2493:MPX
2487:SHA
2444:RVC
2415:ADX
2409:BMI
2384:AMX
2366:FMA
2360:XOP
2348:AVX
2310:SSE
2298:MMX
2289:x86
2273:VIS
2261:VMX
2249:MAX
2232:MXU
2210:SVE
2200:ARM
2193:MVI
1932:Evo
1912:NUC
1887:MID
1815:AES
1810:ASF
1798:TBM
1788:ABM
1783:BMI
1766:FMA
1756:XOP
1751:AVX
1564:AMD
1437:doi
543:SMM
539:SGX
349:EAX
262:XOR
258:SUB
254:SBB
246:NOT
242:NEG
238:INC
234:DEC
222:BTS
218:BTR
214:BTC
210:AND
206:ADC
202:ADD
171:F3H
167:F2H
99:to
36:x86
24:TSX
2589::
1515:,
1488:,
1453:.
1443:.
1226:.
1215:.
1188:.
1148:.
1122:.
1078:^
1051:^
1026:^
985:.
973:^
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