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The ULLtraDIMM supports support both 1.35 V and 1.5 V operation from 800–1333 MHz, and 1.5 V @ 1600 MHz DDR3 transfer rates. DDR3 ECC bits are used to verify the integrity of the data being sent across
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is received and, if there are errors, the device driver will re-run the transfer. The CPU treats the ECC from the ULLtraDIMM in the same manner as ECC from a memory
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This design and connection location provides deterministic (consistent) known latency to enable applications to be streamlined for improved performance.
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ECC bits are not stored in the flash array. A separate ECC scheme is used for protecting data in the flash array. Memory interleaving of standard
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166:"MO-269J Registration - 240 Pin DDR3 DIMM (Dual Inline Memory Module) Family with 1.00 mm pitch. DIM"
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updates are required to properly recognize an ULLtraDIMM in the system as a block device and not halt the
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Flash
Storage devices, the ULLtraDIMM is plugged directly into an industry standard
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142:"Bringing SSD Performance to the DIMM form factor"
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111:is not affected by the presence of ULLtraDIMMs.
103:, single symbol errors are corrected. The
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18:
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76:The ULLtraDIMM is compatible with the
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217:Solid-state computer storage media
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55:memory bus. Unlike traditional
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212:Solid-state computer storage
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16:Solid state storage device
197:Computer storage devices
202:File system management
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192:Computer peripherals
207:Non-volatile memory
41:solid state storage
123:bootstrap sequence
51:directly onto the
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23:ULLtraDIMM Front
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87:specification.
31:ULLtraDIMM Back
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47:that connects
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49:flash storage
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170:. Retrieved
168:. April 2014
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149:. Retrieved
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43:device from
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146:SanDisk.com
186:Categories
172:2013-07-01
151:2013-07-01
129:References
93:memory bus
66:slot in a
64:memory bus
37:ULLtraDIMM
80:MO-269
45:SanDisk
68:server
85:RDIMM
78:JEDEC
61:RDIMM
39:is a
119:BIOS
115:UEFI
105:DDR3
101:DIMM
82:DDR3
57:PCIe
53:DDR3
35:The
109:RAM
97:ECC
188::
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125:.
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117:/
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