1299:
66:
219:
127:
for maximum performance. Wishbone permits addition of a "tag bus" to describe the data. But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags.
103:
Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels.
179:
203:
191:
150:
that describes what it does, bus width, utilization, etc. Promoting reuse of a design requires the data sheet. Making a design reusable in turn makes it easier to share with others.
123:
designs (called "cores"). Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated
165:
Wishbone adapts well to common topologies such as point-to-point, many-to-many (i.e. the classic bus system), hierarchical, or even switched fabrics such as
377:
indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.
1294:
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
739:
1326:
1267:
291:
896:
240:
89:
263:
759:
566:
169:. In the more exotic topologies, Wishbone requires a bus controller or arbiter, but devices still maintain the same interface.
270:
947:
618:
653:
1000:
839:
769:
277:
829:
310:
135:. To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples of
248:
927:
259:
719:
244:
1271:
922:
891:
477:
544:
869:
116:
1195:
1134:
989:
794:
559:
1164:
849:
472:
107:
This ambiguity is intentional. Wishbone is made to let designers combine several designs written in
284:
229:
1321:
1302:
1169:
824:
233:
154:
859:
41:
1123:
1076:
932:
704:
552:
529:
1119:
972:
854:
132:
78:
8:
1031:
586:
124:
575:
85:
1021:
643:
579:
523:
517:
511:
754:
884:
734:
714:
589:
323:
Wishbone control signals compared to other system on a chip (SoC) bus standards:
166:
1185:
879:
804:
729:
633:
608:
120:
1315:
1257:
1144:
1036:
984:
967:
749:
648:
638:
613:
574:
88:
communicate with each other. The aim is to allow the connection of differing
994:
937:
789:
694:
81:
1262:
1241:
1159:
1004:
942:
917:
844:
628:
623:
1081:
1115:
814:
603:
539:
534:
119:(EDA). Wishbone provides a standard way for designers to combine these
178:
1139:
1129:
1096:
1091:
1026:
901:
689:
674:
669:
202:
136:
97:
65:
218:
190:
1149:
1086:
819:
679:
1282:
1236:
1220:
1046:
864:
809:
744:
699:
390:
indicates the termination of a normal bus cycle by slave device.
108:
1215:
1106:
1071:
1066:
1061:
1056:
874:
764:
724:
684:
1200:
1111:
1210:
1101:
1041:
979:
952:
834:
784:
709:
1205:
1190:
1051:
962:
957:
799:
112:
496:
447:
indicated that master requests to read from slave device.
1154:
779:
774:
434:
indicated that master requests to write to slave device.
526:- Combining WISHBONE interface signals application note
157:
is a simplified version of the
Wishbone specification.
146:to the Wishbone specification unless it includes a
139:, to prove its concepts are in the public domain.
520:- PDF specification of latest version of Wishbone
1313:
460:indicates that slave requests that master wait.
351:indicates that a valid bus cycle is in progress
897:Coherent Accelerator Processor Interface (CAPI)
560:
115:or some other logic-description language for
247:. Unsourced material may be challenged and
567:
553:
421:indicates that slave device is selected.
311:Learn how and when to remove this message
64:
69:Master and Slave Wishbone's interfaces.
1314:
364:indicates a valid data transfer cycle
160:
548:
245:adding citations to reliable sources
212:
92:to each other inside of a chip. The
13:
196:
14:
1338:
505:
1327:Open hardware electronic devices
1298:
1297:
217:
201:
189:
177:
84:intended to let the parts of an
96:is used by many designs in the
490:
208:
1:
892:Intel Ultra Path Interconnect
530:Comparison to other SoC buses
483:
478:Advanced eXtensible Interface
172:
870:Intel QuickPath Interconnect
860:Direct Media Interface (DMI)
260:"Wishbone" computer bus
184:
117:electronic design automation
7:
466:
10:
1343:
855:Compute Express Link (CXL)
1291:
1250:
1229:
1178:
1092:IEEE-1284 (parallel port)
1014:
1007:logical device interface)
910:
662:
596:
473:Master/slave (technology)
55:
47:
37:
29:
21:
540:Wishbone@FPGA-Cores.com
514:- The PDF specification
155:Simple Bus Architecture
654:List of bus bandwidths
444:= !(cyc and !we)
431:= !(cyc and we)
397:Avalon => Wishbone
374:= !write_n and read_n
348:= !write_n or !read_n
327:Wishbone => Avalon
70:
68:
48:Hotplugging interface
1097:IEEE-1394 (FireWire)
835:PCI Extended (PCI-X)
241:improve this section
79:open source hardware
25:Silicore Corporation
938:Parallel ATA (PATA)
518:Wishbone Version B4
512:Wishbone Version B3
398:
328:
161:Wishbone topologies
18:
845:PCI Express (PCIe)
535:Wishbone@OpenCores
396:
326:
142:A device does not
86:integrated circuit
71:
56:External interface
16:
1309:
1308:
1295:
1022:Apple Desktop Bus
999:PCI Express (via
958:Serial ATA (SATA)
644:Network on a chip
464:
463:
394:
393:
321:
320:
313:
295:
167:crossbar switches
63:
62:
1334:
1301:
1300:
1293:
755:HP Precision Bus
569:
562:
555:
546:
545:
499:
494:
399:
395:
329:
325:
316:
309:
305:
302:
296:
294:
253:
221:
213:
205:
193:
181:
51:No (On chip bus)
19:
15:
1342:
1341:
1337:
1336:
1335:
1333:
1332:
1331:
1312:
1311:
1310:
1305:
1296:
1287:
1246:
1225:
1174:
1087:IEEE-488 (GPIB)
1010:
906:
885:Infinity Fabric
715:Europe Card Bus
658:
592:
573:
508:
503:
502:
495:
491:
486:
469:
387:= !waitrequest
317:
306:
300:
297:
254:
252:
238:
222:
211:
199:
197:Crossbar switch
187:
175:
163:
125:combinatorially
12:
11:
5:
1340:
1330:
1329:
1324:
1322:Computer buses
1307:
1306:
1292:
1289:
1288:
1286:
1285:
1280:
1275:
1265:
1260:
1254:
1252:
1248:
1247:
1245:
1244:
1239:
1233:
1231:
1227:
1226:
1224:
1223:
1218:
1213:
1208:
1203:
1198:
1196:Intel HD Audio
1193:
1188:
1186:ADAT Lightpipe
1182:
1180:
1176:
1175:
1173:
1172:
1167:
1162:
1157:
1152:
1147:
1142:
1137:
1132:
1127:
1109:
1104:
1099:
1094:
1089:
1084:
1079:
1074:
1069:
1064:
1059:
1054:
1049:
1044:
1039:
1034:
1029:
1024:
1018:
1016:
1012:
1011:
1009:
1008:
997:
992:
987:
982:
977:
976:
975:
970:
960:
955:
950:
945:
940:
935:
930:
925:
920:
914:
912:
908:
907:
905:
904:
899:
894:
889:
888:
887:
880:HyperTransport
877:
872:
867:
862:
857:
852:
847:
842:
837:
832:
827:
822:
817:
812:
807:
802:
797:
792:
787:
782:
777:
772:
767:
762:
757:
752:
747:
742:
737:
732:
727:
722:
717:
712:
707:
702:
697:
692:
687:
682:
677:
672:
666:
664:
660:
659:
657:
656:
651:
646:
641:
636:
634:Bus contention
631:
626:
621:
616:
611:
609:Front-side bus
606:
600:
598:
594:
593:
590:computer buses
572:
571:
564:
557:
549:
543:
542:
537:
532:
527:
521:
515:
507:
506:External links
504:
501:
500:
488:
487:
485:
482:
481:
480:
475:
468:
465:
462:
461:
458:
455:
449:
448:
445:
442:
436:
435:
432:
429:
423:
422:
419:
416:
410:
409:
406:
403:
392:
391:
388:
385:
379:
378:
375:
372:
366:
365:
362:
359:
353:
352:
349:
346:
340:
339:
336:
333:
319:
318:
301:September 2017
225:
223:
216:
210:
207:
198:
195:
186:
183:
174:
171:
162:
159:
121:hardware logic
61:
60:
57:
53:
52:
49:
45:
44:
39:
35:
34:
31:
27:
26:
23:
9:
6:
4:
3:
2:
1339:
1328:
1325:
1323:
1320:
1319:
1317:
1304:
1290:
1284:
1281:
1279:
1276:
1273:
1269:
1266:
1264:
1261:
1259:
1258:Multidrop bus
1256:
1255:
1253:
1249:
1243:
1240:
1238:
1235:
1234:
1232:
1228:
1222:
1219:
1217:
1214:
1212:
1209:
1207:
1204:
1202:
1199:
1197:
1194:
1192:
1189:
1187:
1184:
1183:
1181:
1177:
1171:
1168:
1166:
1165:External PCIe
1163:
1161:
1158:
1156:
1153:
1151:
1148:
1146:
1145:Parallel SCSI
1143:
1141:
1138:
1136:
1133:
1131:
1128:
1125:
1121:
1117:
1113:
1110:
1108:
1105:
1103:
1100:
1098:
1095:
1093:
1090:
1088:
1085:
1083:
1080:
1078:
1075:
1073:
1070:
1068:
1065:
1063:
1060:
1058:
1055:
1053:
1050:
1048:
1045:
1043:
1040:
1038:
1037:Commodore bus
1035:
1033:
1030:
1028:
1025:
1023:
1020:
1019:
1017:
1013:
1006:
1002:
998:
996:
993:
991:
988:
986:
985:Fibre Channel
983:
981:
978:
974:
971:
969:
966:
965:
964:
961:
959:
956:
954:
951:
949:
946:
944:
941:
939:
936:
934:
931:
929:
926:
924:
921:
919:
916:
915:
913:
909:
903:
900:
898:
895:
893:
890:
886:
883:
882:
881:
878:
876:
873:
871:
868:
866:
863:
861:
858:
856:
853:
851:
848:
846:
843:
841:
838:
836:
833:
831:
828:
826:
823:
821:
818:
816:
813:
811:
808:
806:
803:
801:
798:
796:
793:
791:
788:
786:
783:
781:
778:
776:
773:
771:
768:
766:
763:
761:
758:
756:
753:
751:
748:
746:
743:
741:
738:
736:
733:
731:
728:
726:
723:
721:
718:
716:
713:
711:
708:
706:
703:
701:
698:
696:
693:
691:
688:
686:
683:
681:
678:
676:
673:
671:
668:
667:
665:
661:
655:
652:
650:
649:Plug and play
647:
645:
642:
640:
639:Bus mastering
637:
635:
632:
630:
627:
625:
622:
620:
617:
615:
614:Back-side bus
612:
610:
607:
605:
602:
601:
599:
595:
591:
588:
584:
582:
577:
570:
565:
563:
558:
556:
551:
550:
547:
541:
538:
536:
533:
531:
528:
525:
522:
519:
516:
513:
510:
509:
498:
493:
489:
479:
476:
474:
471:
470:
459:
456:
454:
451:
450:
446:
443:
441:
438:
437:
433:
430:
428:
425:
424:
420:
417:
415:
412:
411:
407:
404:
401:
400:
389:
386:
384:
381:
380:
376:
373:
371:
368:
367:
363:
361:= chipselect
360:
358:
355:
354:
350:
347:
345:
342:
341:
337:
334:
331:
330:
324:
315:
312:
304:
293:
290:
286:
283:
279:
276:
272:
269:
265:
262: –
261:
257:
256:Find sources:
250:
246:
242:
236:
235:
231:
226:This section
224:
220:
215:
214:
206:
204:
194:
192:
182:
180:
170:
168:
158:
156:
151:
149:
145:
140:
138:
134:
129:
126:
122:
118:
114:
110:
105:
101:
99:
95:
91:
87:
83:
80:
76:
67:
58:
54:
50:
46:
43:
40:
36:
33:8, 16, 32, 64
32:
30:Width in bits
28:
24:
20:
1277:
790:TURBOchannel
580:
492:
452:
439:
426:
413:
408:Description
382:
369:
356:
343:
338:Description
322:
307:
298:
288:
281:
274:
267:
255:
239:Please help
227:
200:
188:
176:
164:
152:
147:
143:
141:
131:Wishbone is
130:
106:
102:
94:Wishbone Bus
93:
82:computer bus
75:Wishbone Bus
74:
72:
1263:CoreConnect
1242:ExpressCard
1170:Thunderbolt
1160:Camera Link
943:Bus and Tag
629:Address bus
624:Control bus
619:Daisy chain
497:"About SBA"
453:waitrequest
402:Avalon Bus
335:Avalon Bus
209:Comparisons
133:open source
1316:Categories
1116:ACCESS.bus
1015:Peripheral
815:InfiniBand
810:HP GSC bus
604:System bus
524:appnote_01
484:References
414:chipselect
271:newspapers
173:Shared bus
148:data sheet
22:Created by
1077:Lightning
1027:Atari SIO
902:SpaceWire
735:Zorro III
675:S-100 bus
670:SS-50 bus
663:Standards
583:standards
576:Technical
405:Wishbone
332:Wishbone
228:does not
185:Data flow
137:prior art
100:project.
98:OpenCores
1303:Category
1278:Wishbone
1251:Embedded
1230:Portable
1150:Profibus
1082:DMX512-A
968:Parallel
820:Ethernet
730:Zorro II
680:Multibus
581:de facto
467:See also
42:Parallel
17:Wishbone
1283:SLIMbus
1237:PC Card
1221:TOSLINK
911:Storage
865:RapidIO
745:FASTBUS
700:STD Bus
597:General
457:= !ack
427:write_n
285:scholar
249:removed
234:sources
144:conform
109:Verilog
1216:S/PDIF
1107:1-Wire
1072:RS-485
1067:RS-423
1062:RS-422
1057:RS-232
918:ST-506
875:NVLink
725:STEbus
685:Unibus
440:read_n
418:= stb
287:
280:
273:
266:
258:
77:is an
1211:McASP
1179:Audio
1124:SMBus
1120:PMBus
1102:UNI/O
1042:HP-IL
995:SATAe
980:ESCON
953:HIPPI
785:NuBus
740:CAMAC
710:Q-Bus
705:SMBus
690:VAXBI
587:wired
292:JSTOR
278:books
90:cores
38:Style
1268:AMBA
1206:MADI
1191:AES3
1052:MIDI
1005:NVMe
1001:AHCI
963:SCSI
948:DSSI
923:ESDI
800:SBus
760:EISA
695:MBus
585:for
578:and
264:news
232:any
230:cite
153:The
113:VHDL
73:The
1272:AXI
1201:I²S
1155:USB
1140:D²B
1135:SPI
1130:I3C
1112:I²C
1047:HIL
1032:DCB
1003:or
990:SSA
973:SAS
933:SMD
928:IPI
850:AGP
840:PXI
830:PCI
825:UPA
805:VLB
795:MCA
780:VPX
775:VXS
770:VXI
765:VME
750:LPC
720:ISA
383:ack
357:stb
344:cyc
243:by
1318::
1122:,
1118:,
370:we
111:,
59:No
1274:)
1270:(
1126:)
1114:(
568:e
561:t
554:v
314:)
308:(
303:)
299:(
289:·
282:·
275:·
268:·
251:.
237:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
