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999:(MPW) as a method of obtaining low cost prototypes. Often called shuttles, these MPWs, containing several designs, run at regular, scheduled intervals on a "cut and go" basis, usually with limited liability on the part of the manufacturer. The contract involves delivery of bare dies or the assembly and packaging of a handful of devices. The service usually involves the supply of a physical design database (i.e. masking information or pattern generation (PG) tape). The manufacturer is often referred to as a "silicon foundry" due to the low involvement it has in the process.
32:
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899:") is a relatively new trend in the semiconductor industry, resulting in some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC, by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of what is on the silicon (thus reducing design cycle time).
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tools used for structured ASIC can be substantially lower cost and easier (faster) to use than cell-based tools, because they do not have to perform all the functions that cell-based tools do. In some cases, the structured ASIC vendor requires customized tools for their device (e.g., custom physical synthesis) be used, also allowing for the design to be brought into manufacturing more quickly.
907:"Structured ASIC" technology is seen as bridging the gap between field-programmable gate arrays and "standard-cell" ASIC designs. Because only a small number of chip layers must be custom-produced, "structured ASIC" designs have much smaller non-recurring expenditures (NRE) than "standard-cell" or "full-custom" chips, which require that a full mask set be produced for every design.
952:(often termed a "soft macro"), or as a fully routed design that could be printed directly onto an ASIC's mask (often termed a "hard macro"). Many organizations now sell such pre-designed cores – CPUs, Ethernet, USB or telephone interfaces – and larger organizations may have an entire department or division to produce cores for the rest of the organization. The company
236:, meaning that they are not made to be application-specific as opposed to ASICs. Programmable logic blocks and programmable interconnects allow the same FPGA to be used in many different applications. For smaller designs or lower production volumes, FPGAs may be more cost-effective than an ASIC design, even in production. The
643:, are also common to standard product design. The significant difference is that standard-cell design uses the manufacturer's cell libraries that have been used in potentially hundreds of other design implementations and therefore are of much lower risk than a full custom design. Standard cells produce a
917:
This is effectively the same definition as a gate array. What distinguishes a structured ASIC from a gate array is that in a gate array, the predefined metal layers serve to make manufacturing turnaround faster. In a structured ASIC, the use of predefined metallization is primarily to reduce cost of
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In a "structured ASIC" design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Design differentiation and customization is achieved by creating custom metal layers that create custom connections between predefined lower-layer logic elements.
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For example, in a cell-based or gate-array design the user must often design power, clock, and test structures themselves. By contrast, these are predefined in most structured ASICs and therefore can save time and expense for the designer compared to gate-array based designs. Likewise, the design
376:
and actual semiconductor process performance characteristics of the various ASIC manufacturers. Most designers used factory-specific tools to complete the implementation of their designs. A solution to this problem, which also yielded a much higher density device, was the implementation of
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process defines the interconnections of these layers for the final device. For most ASIC manufacturers, this consists of between two and nine metal layers with each layer running perpendicular to the one below it. Non-recurring engineering costs are much lower than full custom designs, as
870:
For digital-only designs, however, "standard-cell" cell libraries, together with modern CAD systems, can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to "hand-tweak" or manually optimize any
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Soft macros are often process-independent (i.e. they can be fabricated on a wide range of manufacturing processes and different manufacturers). Hard macros are process-limited and usually further design effort must be invested to migrate (port) to a different process or manufacturer.
371:
In the mid-1980s, a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third-party design tools were available, there was not an effective link from the third-party design tools to the
385:, capacitance and inductance, that could also be represented in third-party tools. Standard-cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard-cell design is intermediate between
1053:. Both of these examples are specific to an application (which is typical of an ASIC) but are sold to many different system vendors (which is typical of standard parts). ASICs such as these are sometimes called application-specific standard products (ASSPs).
520:
performing specific functions. The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells and the needed electrical connections between them is called a gate-level
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Indeed, the wide range of functions now available in structured ASIC design is a result of the phenomenal improvement in electronics in the late 1990s and early 2000s; as a core takes a lot of time and investment to create, its
635:
These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.
290:(CMOS) technology opened the door to the broad commercialization of gate arrays. The first CMOS gate arrays were developed by Robert Lipp, in 1974 for International Microcircuits, Inc. (IMI).
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of logical primitives are usually provided by the device manufacturer as part of the service. Although they will incur no additional cost, their release will be covered by the terms of a
737:(FPGAs) which can be programmed by the user and thus offer minimal tooling charges, non-recurring engineering, only marginally increased piece part cost, and comparable performance.
833:
By contrast, full-custom ASIC design defines all the photolithographic layers of the device. Full-custom design is used for both ASIC design and for standard product design.
667:
Microscope photograph of a gate-array ASIC showing the predefined logic cells and custom interconnections. This particular design uses less than 20% of available logic gates.
937:(NDA) and they will be regarded as intellectual property by the manufacturer. Usually, their physical design will be pre-defined so they could be termed "hard macros".
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the interconnect require migration onto a larger array device with a consequent increase in the piece part price. These difficulties are often a result of the layout
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The disadvantages of full-custom design can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the
1038:, ASSPs are available as off-the-shelf components. ASSPs are used in all industries, from automotive to communications. As a general rule, if you can find a
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are intended to ensure that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the
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masks are required only for the metal layers. Production cycles are much shorter, as metallization is a comparatively quick process; thereby accelerating
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486:. Each verification technique has advantages and disadvantages, and most often several methods are used together for ASIC verification. Unlike most
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transforms the RTL design into a large collection called of lower-level constructs called standard cells. These constructs are taken from a
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Customization occurred by varying a metal interconnect mask. Gate arrays had complexities of up to a few thousand gates; this is now called
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in terms of its non-recurring engineering and recurring component costs as well as performance and speed of development (including
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Pure, logic-only gate-array design is rarely implemented by circuit designers today, having been almost entirely replaced by
143:(IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a
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that appeals to a wide market. As opposed to ASICs that combine a collection of functions and are designed by or for one
304:, under the trade names Micromosaic and Polycell, in the 1970s. This technology was later successfully commercialized by
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In their frequent usages in the field, the terms "gate array" and "semi-custom" are synonymous when referring to ASICs.
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more commonly use the term "semi-custom", while "gate-array" is more commonly used by logic (or gate-level) designers.
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240:(NRE) cost of an ASIC can run into the millions of dollars. Therefore, device manufacturers typically prefer FPGAs
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improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000
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Microscope photograph of custom ASIC (486 chipset) showing gate-based design on top and custom circuitry on bottom
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For example, two ICs that might or might not be considered ASICs are a controller chip for a PC and a chip for a
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and therefore ASIC designs that are not completely correct are much more costly, increasing the need for full
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and further development cuts product cycle times dramatically and creates better products. Additionally,
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381:. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as
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462:: Suitability for purpose is verified by functional verification. This may include such techniques as
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1362:. Studies in Systems, Decision and Control. Vol. 195. Cham: Springer International Publishing.
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The benefits of full-custom design include reduced area (and therefore recurring component cost),
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ASIC Design in the
Silicon Sandbox: A Complete Guide to Building Mixed-Signal Integrated Circuits
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ASIC Design in the
Silicon Sandbox: A Complete Guide to Building Mixed-signal Integrated Circuits
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Examples of ASSPs are encoding/decoding chip, Ethernet network interface controller chip, etc.
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tool takes the physical placement of the standard cells and uses the netlist to create the
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A successful commercial application of gate array circuitry was found in the low-end 8-bit
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as mapping a given design onto what a manufacturer held as a stock wafer never gives 100%
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This is designed by using basic logic gates, circuits or layout specially for a design.
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chips are intermediate between ASICs and industry standard integrated circuits like the
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446:: The design team constructs a description of an ASIC to achieve these goals using a
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placement of the standard cells, subject to a variety of specified constraints.
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design is a manufacturing method in which diffused layers, each consisting of
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1178:"1967: Application Specific Integrated Circuits employ Computer-Aided Design"
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the mask sets as well as making the design cycle time significantly shorter.
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systems, and a much higher skill requirement on the part of the design team.
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581:. Placement and routing are closely interrelated and are collectively called
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429:: A team of design engineers starts with a non-formal understanding of the
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Barkalov, Alexander; Titarenko, Larysa; Mazurkiewicz, Małgorzata (2019).
820:
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containing such devices are "held in stock" or unconnected prior to the
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565:" solution. The output is a file which can be used to create a set of
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Physical design essentials: an ASIC design implementation perspective
1448:"Xilinx intros next-gen EasyPath FPGAs priced below structured ASICs"
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representing the final ASIC. The placement tool attempts to find an
416:(ICs) are designed in the following conceptual stages referred to as
309:
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and other large building blocks. Such an ASIC is often termed a SoC (
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1046:, then it is probably not an ASIC, but there are some exceptions.
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Gate-array ASICs are always a compromise between rapid design and
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2014:
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from which the circuit performance can be estimated, usually by
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is large, this process will produce a "sufficient" rather than "
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2029:
1994:
1959:
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450:. This process is similar to writing a computer program in a
94:
A tray of application-specific integrated circuit (ASIC) chips
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2019:
1989:
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Definition from
Foundations of Embedded Systems states that:
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2009:
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420:, although these stages overlap significantly in practice:
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tool which places the standard cells onto a region of an
345:. Later versions became more generalized, with different
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for an overview of computing based primarily in hardware
1002:
186:
to over 100 million. Modern ASICs often include entire
386:
1172:
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1168:
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926:
Cell libraries, IP-based design, hard and soft macros
244:
and devices with low production volume and ASICs for
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125:
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that is cost-effective, and they can also integrate
232:(FPGA) are the modern-day technology improvement on
119:
1163:
1134:
404:tools became available. Such tools could compile
326:, introduced in 1981 and 1982. These were used by
102:A packet processing ASIC inside an Ethernet switch
16:Integrated circuit customized for a specific task
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840:improvements, and also the ability to integrate
733:devices. The most prominent of such devices are
531:: The gate-level netlist is next processed by a
478:, or creating and evaluating an equivalent pure
1421:
995:Some manufacturers and IC design houses offer
516:consisting of pre-characterized collections of
1067:Application-specific instruction set processor
979:are collecting free IP cores, paralleling the
4460:
4013:
3455:
1512:
848:—and thus fully verified—components, such as
276:introduced the Micromatrix family of bipolar
2517:Computer performance by orders of magnitude
1424:"Xilinx looks to ease path to custom FPGAs"
1402:
1325:Hurley, Jaden Mclean & Carmen. (2019).
1232:. Computer History Museum. 14 February 2017
871:performance-limiting aspect of the design.
726:software used to develop the interconnect.
300:technology was introduced by Fairchild and
19:"ASIC" redirects here. For other uses, see
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4453:
4020:
4006:
3462:
3448:
1526:
1519:
1505:
1454:. Millin Publishing, Inc. 18 October 2004.
573:, commonly called a 'fab' or 'foundry' to
226:, to describe the functionality of ASICs.
214:). Designers of digital ASICs often use a
4474:
1205:
268:and Interdesign were manufacturing early
76:Learn how and when to remove this message
4773:Application-specific integrated circuits
1491:Application-specific integrated circuits
1302:Application-Specific Integrated Circuits
1006:
824:
800:, and other components rather than only
662:
655:(SRAM) effectively, unlike gate arrays.
603:, this will then be further mapped into
387:§ Gate-array and semi-custom design
360:
97:
89:
39:This article includes a list of general
4192:Application-specific integrated circuit
4027:
1458:
990:
611:. This, and other final tests such as
390:
288:Complementary metal–oxide–semiconductor
108:application-specific integrated circuit
4765:
3469:
1300:Smith, Michael John Sebastian (1997).
1014:M66591GP: USB2.0 Peripheral Controller
597:parasitic resistances and capacitances
4448:
4001:
3443:
1500:
1206:Kriegbaum, Jeff (13 September 2004).
1020:application-specific standard product
1003:Application-specific standard product
814:
740:Today, gate arrays are evolving into
433:for a new ASIC, usually derived from
153:Application-specific standard product
4127:Three-dimensional integrated circuit
2488:Floating-point operations per second
1132:
1128:
1126:
877:
353:layers. Some base dies also include
25:
940:What most engineers understand as "
13:
4139:Erasable programmable logic device
571:semiconductor fabrication facility
45:it lacks sufficient corresponding
14:
4799:
4545:Hardware random number generation
4174:Complex programmable logic device
1478:
1422:Anthony Cataldo (26 March 2002).
1123:
1073:Complex programmable logic device
659:Gate-array and semi-custom design
178:As feature sizes have shrunk and
3414:Semiconductor device fabrication
1484:
1430:. CMP Media, LLC. Archived from
115:
30:
4186:Field-programmable object array
4122:Mixed-signal integrated circuit
3389:History of general-purpose CPUs
1616:Nondeterministic Turing machine
1360:Foundations of Embedded Systems
1304:. Addison-Wesley Professional.
912:Foundations of Embedded Systems
408:descriptions into a gate-level
334:solution aimed at handling the
330:(UK) essentially as a low-cost
1569:Deterministic finite automaton
1351:
1318:
1264:
1220:
1199:
735:field-programmable gate arrays
230:Field-programmable gate arrays
1:
4312:Hardware description language
4180:Field-programmable gate array
2360:Simultaneous and heterogenous
1116:
1085:Field-programmable gate array
983:movement in hardware design.
950:hardware description language
639:The design steps also called
448:hardware description language
349:customized by both metal and
246:very large production volumes
216:hardware description language
3044:Integrated memory controller
3026:Translation lookaside buffer
2225:Memory dependence prediction
1668:Random-access stored program
1621:Probabilistic Turing machine
1407:. McGraw Hill Professional.
1097:Very Large Scale Integration
1079:Electronic design automation
959:sells IP cores, making it a
865:electronic design automation
627:information is released for
7:
4324:Formal equivalence checking
2500:Synaptic updates per second
1059:
1030:that implements a specific
997:multi-project wafer service
804:and basic interconnection.
653:static random-access memory
282:transistor–transistor logic
163:. ASIC chips are typically
10:
4804:
4344:Hierarchical state machine
4302:Transaction-level modeling
2904:Heterogeneous architecture
1826:Orthogonal instruction set
1596:Alternating Turing machine
1584:Quantum cellular automaton
1396:
881:
818:
591:: Given the final layout,
364:
255:
18:
4700:
4647:
4597:
4540:Digital signal processing
4510:
4482:
4421:
4354:
4270:
4245:Digital signal processing
4230:Logic in computer science
4207:
4156:Programmable logic device
4116:Hybrid integrated circuit
4035:
3920:
3867:
3856:
3815:
3789:
3782:
3701:
3572:
3477:
3394:Microprocessor chronology
3381:
3357:Dynamic frequency scaling
3330:
3266:
3204:
3158:
3110:
3065:
2985:
2912:
2881:
2786:
2707:
2671:
2625:
2525:
2512:Cache performance metrics
2451:
2385:
2335:
2246:
2237:
2210:
2165:
2132:
2104:
2095:
1915:
1818:
1807:
1678:
1534:
1368:10.1007/978-3-030-11961-4
1278:. Computer History Museum
1141:. New York: McGraw-Hill.
790:communications subsystems
718:. Often difficulties in
557:between them. Since the
391:§ Full-custom design
294:Metal–oxide–semiconductor
238:non-recurring engineering
169:metal–oxide–semiconductor
4492:Universal Turing machine
4257:Switching circuit theory
4162:Programmable Array Logic
4150:Programmable logic array
3554:Circuit underutilization
3537:Reconfigurable computing
3409:Hardware security module
2752:Digital signal processor
2729:Graphics processing unit
2541:Graphics processing unit
935:non-disclosure agreement
884:Structured ASIC platform
754:digital signal processor
744:that consist of a large
426:Requirements engineering
4550:Artificial intelligence
4307:Register-transfer level
3362:Dynamic voltage scaling
3145:Memory address register
3039:Branch target predictor
3003:Address generation unit
2746:Physics processing unit
2535:Central processing unit
2494:Transactions per second
2482:Instructions per second
2405:Array processing (SIMT)
1549:Stored-program computer
1452:EDP Weekly's IT Monitor
1186:Computer History Museum
459:Functional verification
442:Register-transfer level
418:electronics design flow
274:Fairchild Semiconductor
248:where NRE costs can be
60:more precise citations.
4572:Custom hardware attack
4198:Tensor Processing Unit
3168:Hardwired control unit
3050:Memory management unit
3015:Memory management unit
2764:Secure cryptoprocessor
2758:Tensor Processing Unit
2740:Vision processing unit
2474:Cycles per instruction
2468:Instructions per cycle
2415:Associative processing
2106:Instruction pipelining
1528:Processor technologies
1463:. New York: Springer.
1229:Lipp, Bob oral history
1015:
975:organizations such as
915:
895:(also referred to as "
893:Structured ASIC design
830:
668:
609:static timing analysis
585:in electronics design.
555:electrical connections
537:integrated circuit die
278:diode–transistor logic
272:gate arrays. In 1967,
173:MOS integrated circuit
145:digital voice recorder
103:
95:
4788:Hardware acceleration
4502:Distributed computing
4476:Hardware acceleration
4413:Electronic literature
4367:Hardware acceleration
4235:Computer architecture
4133:Emitter-coupled logic
4070:Printed circuit board
3564:Hardware acceleration
3251:Sum-addressed decoder
2997:Arithmetic logic unit
2124:Classic RISC pipeline
2078:Epiphany architecture
1925:Motorola 68000 series
1109:Hardware acceleration
1010:
942:intellectual property
904:
888:Platform-based design
861:computer-aided design
844:components and other
828:
682:, are predefined and
666:
514:standard-cell library
435:requirements analysis
361:Standard-cell designs
343:mid-scale integration
264:technology. By 1967,
252:across many devices.
171:(MOS) technology, as
147:or a high-efficiency
101:
93:
21:ASIC (disambiguation)
4605:High-level synthesis
4339:Finite-state machine
4317:High-level synthesis
4252:Circuit minimization
3754:Microchip Technology
3559:High-level synthesis
3372:Performance per watt
2950:replacement policies
2616:Package on a package
2506:Performance per watt
2410:Pipelined processing
2180:Tomasulo's algorithm
1985:Clipper architecture
1841:Application-specific
1554:Finite-state machine
1493:at Wikimedia Commons
1459:Golshan, K. (2007).
1434:on 29 September 2007
1403:Barr, Keith (2007).
1133:Barr, Keith (2007).
991:Multi-project wafers
981:open-source software
973:open-source hardware
961:fabless manufacturer
897:platform ASIC design
619:collectively called
613:design rule checking
599:. In the case of a
355:random-access memory
4783:Integrated circuits
4730:Digital electronics
4682:In-memory computing
4662:Transport triggered
4386:Digital photography
4168:Generic Array Logic
4090:Combinational logic
4065:Printed electronics
4029:Digital electronics
3823:Intel Quartus Prime
3549:Soft microprocessor
3404:Digital electronics
3057:Instruction decoder
3009:Floating-point unit
2663:Soft microprocessor
2610:System in a package
2185:Reservation station
1715:Transport-triggered
1208:"FPGA's vs. ASIC's"
852:cores, that form a
780:functionality, and
716:circuit utilization
692:fabrication process
579:integrated circuits
472:formal verification
452:high-level language
414:integrated circuits
400:By the late 1990s,
336:computer's graphics
308:(founded 1979) and
4740:Hardware emulation
4708:Programmable logic
4497:Parallel computing
4334:Asynchronous logic
4110:Integrated circuit
4075:Electronic circuit
3471:Programmable logic
3276:Integrated circuit
3120:Processor register
2774:Baseband processor
2119:Operand forwarding
1579:Cellular automaton
1276:The Silicon Engine
1182:The Silicon Engine
1091:Multi-project chip
1028:integrated circuit
1016:
831:
815:Full-custom design
731:field-programmable
684:electronics wafers
669:
593:circuit extraction
490:, ASICs cannot be
431:required functions
324:personal computers
141:integrated circuit
104:
96:
4760:
4759:
4637:Network on a chip
4442:
4441:
4391:Digital telephone
4362:Computer hardware
4329:Synchronous logic
3995:
3994:
3991:
3990:
3987:
3986:
3774:Texas Instruments
3437:
3436:
3326:
3325:
2945:Instruction cache
2935:Scratchpad memory
2782:
2781:
2769:Network processor
2698:Network on a chip
2653:Ultra-low-voltage
2604:Multi-chip module
2447:
2446:
2233:
2232:
2220:Branch prediction
2197:Register renaming
2091:
2090:
2073:VISC architecture
1895:Quantum computing
1890:VISC architecture
1772:Secondary storage
1688:Microarchitecture
1648:Register machines
1489:Media related to
1470:978-0-387-36642-5
1414:978-0-07-148161-8
1336:978-1-83947-319-7
1311:978-0-201-50022-6
1148:978-0-07-148161-8
878:Structured design
809:Process engineers
782:systems on a chip
772:, and a block of
701:photolithographic
605:delay information
549:: An electronics
412:. Standard-cell
383:propagation delay
328:Sinclair Research
260:Early ASICs used
194:blocks including
180:chip design tools
86:
85:
78:
4795:
4752:Embedded systems
4632:System on a chip
4469:
4462:
4455:
4446:
4445:
4095:Sequential logic
4022:
4015:
4008:
3999:
3998:
3865:
3864:
3787:
3786:
3464:
3457:
3450:
3441:
3440:
3399:Processor design
3291:Power management
3173:Instruction unit
3034:Branch predictor
2983:
2982:
2681:System on a chip
2623:
2622:
2463:Transistor count
2387:Flynn's taxonomy
2244:
2243:
2102:
2101:
1905:Addressing modes
1816:
1815:
1762:Memory hierarchy
1626:Hypercomputation
1544:Abstract machine
1521:
1514:
1507:
1498:
1497:
1488:
1474:
1455:
1443:
1441:
1439:
1418:
1390:
1389:
1355:
1349:
1348:
1322:
1316:
1315:
1297:
1288:
1287:
1285:
1283:
1268:
1262:
1261:
1255:
1251:
1249:
1241:
1239:
1237:
1224:
1218:
1217:
1203:
1197:
1196:
1194:
1192:
1174:
1161:
1160:
1140:
1130:
1103:System on a chip
913:
854:system on a chip
802:functional units
794:networks on chip
742:structured ASICs
629:chip fabrication
563:globally optimal
464:logic simulation
357:(RAM) elements.
138:
137:
134:
133:
130:
127:
124:
121:
81:
74:
70:
67:
61:
56:this article by
47:inline citations
34:
33:
26:
4803:
4802:
4798:
4797:
4796:
4794:
4793:
4792:
4763:
4762:
4761:
4756:
4747:Logic synthesis
4696:
4643:
4598:Implementations
4593:
4506:
4478:
4473:
4443:
4438:
4417:
4350:
4285:Place and route
4280:Logic synthesis
4266:
4262:Gate equivalent
4225:Logic synthesis
4220:Boolean algebra
4203:
4145:Macrocell array
4105:Boolean circuit
4031:
4026:
3996:
3983:
3916:
3859:
3852:
3811:
3778:
3697:
3568:
3473:
3468:
3438:
3433:
3419:Tick–tock model
3377:
3333:
3322:
3262:
3246:Address decoder
3200:
3154:
3150:Program counter
3125:Status register
3106:
3061:
3021:Load–store unit
2988:
2981:
2908:
2877:
2778:
2735:Image processor
2710:
2703:
2673:
2667:
2643:Microcontroller
2633:Embedded system
2621:
2521:
2454:
2443:
2381:
2331:
2229:
2206:
2190:Re-order buffer
2161:
2142:Data dependency
2128:
2087:
1917:
1911:
1810:
1809:Instruction set
1803:
1789:Multiprocessing
1757:Cache hierarchy
1750:Register/memory
1674:
1574:Queue automaton
1530:
1525:
1481:
1471:
1446:
1437:
1435:
1415:
1399:
1394:
1393:
1378:
1356:
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1200:
1190:
1188:
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1149:
1131:
1124:
1119:
1114:
1062:
1005:
993:
928:
914:
911:
890:
882:Main articles:
880:
823:
817:
784:(SoCs) require
696:physical design
661:
601:digital circuit
583:place and route
510:Logic synthesis
506:Logic synthesis
402:logic synthesis
369:
363:
306:VLSI Technology
258:
242:for prototyping
218:(HDL), such as
188:microprocessors
118:
114:
82:
71:
65:
62:
52:Please help to
51:
35:
31:
24:
17:
12:
11:
5:
4801:
4791:
4790:
4785:
4780:
4775:
4758:
4757:
4755:
4754:
4749:
4744:
4743:
4742:
4735:Virtualization
4732:
4727:
4726:
4725:
4720:
4710:
4704:
4702:
4698:
4697:
4695:
4694:
4689:
4687:Systolic array
4684:
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4674:
4669:
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4595:
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4586:
4581:
4580:
4579:
4569:
4567:Machine vision
4564:
4563:
4562:
4552:
4547:
4542:
4537:
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4514:
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4457:
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4431:
4425:
4423:
4419:
4418:
4416:
4415:
4410:
4409:
4408:
4403:
4401:cinematography
4393:
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4371:
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4282:
4276:
4274:
4268:
4267:
4265:
4264:
4259:
4254:
4249:
4248:
4247:
4240:Digital signal
4237:
4232:
4227:
4222:
4217:
4215:Digital signal
4211:
4209:
4205:
4204:
4202:
4201:
4195:
4189:
4183:
4177:
4171:
4165:
4159:
4153:
4147:
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4113:
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4097:
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3474:
3467:
3466:
3459:
3452:
3444:
3435:
3434:
3432:
3431:
3426:
3424:Pin grid array
3421:
3416:
3411:
3406:
3401:
3396:
3391:
3385:
3383:
3379:
3378:
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3305:
3300:
3295:
3294:
3293:
3288:
3283:
3272:
3270:
3264:
3263:
3261:
3260:
3258:Barrel shifter
3255:
3254:
3253:
3248:
3241:Binary decoder
3238:
3237:
3236:
3226:
3221:
3216:
3210:
3208:
3202:
3201:
3199:
3198:
3193:
3185:
3180:
3175:
3170:
3164:
3162:
3156:
3155:
3153:
3152:
3147:
3142:
3137:
3132:
3130:Stack register
3127:
3122:
3116:
3114:
3108:
3107:
3105:
3104:
3103:
3102:
3097:
3087:
3082:
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2776:
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2755:
2749:
2743:
2737:
2732:
2726:
2724:AI accelerator
2721:
2715:
2713:
2705:
2704:
2702:
2701:
2695:
2690:
2687:Multiprocessor
2684:
2677:
2675:
2669:
2668:
2666:
2665:
2660:
2655:
2650:
2645:
2640:
2638:Microprocessor
2635:
2629:
2627:
2626:By application
2620:
2619:
2613:
2607:
2601:
2596:
2591:
2586:
2581:
2576:
2571:
2569:Tile processor
2566:
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2556:
2551:
2550:
2549:
2538:
2531:
2529:
2523:
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2520:
2519:
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2389:
2383:
2382:
2380:
2379:
2374:
2369:
2364:
2363:
2362:
2357:
2355:Hyperthreading
2347:
2341:
2339:
2337:Multithreading
2333:
2332:
2330:
2329:
2324:
2319:
2318:
2317:
2307:
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2300:
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2250:
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2116:
2114:Pipeline stall
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2063:z/Architecture
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1767:Virtual memory
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1628:
1623:
1618:
1613:
1608:
1603:
1598:
1591:Turing machine
1588:
1587:
1586:
1581:
1576:
1571:
1566:
1561:
1551:
1546:
1540:
1538:
1532:
1531:
1524:
1523:
1516:
1509:
1501:
1495:
1494:
1480:
1479:External links
1477:
1476:
1475:
1469:
1456:
1444:
1419:
1413:
1398:
1395:
1392:
1391:
1376:
1350:
1335:
1317:
1310:
1289:
1263:
1254:|website=
1219:
1198:
1162:
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1121:
1120:
1118:
1115:
1113:
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1106:
1100:
1094:
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1004:
1001:
992:
989:
931:Cell libraries
927:
924:
909:
879:
876:
850:microprocessor
819:Main article:
816:
813:
774:reconfigurable
705:time to market
680:active devices
660:
657:
645:design density
633:
632:
617:power analysis
586:
544:
526:
503:
455:
438:
395:time to market
379:standard cells
365:Main article:
362:
359:
284:(TTL) arrays.
257:
254:
212:system-on-chip
84:
83:
38:
36:
29:
15:
9:
6:
4:
3:
2:
4800:
4789:
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4779:
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4753:
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4724:
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4709:
4706:
4705:
4703:
4699:
4693:
4690:
4688:
4685:
4683:
4680:
4678:
4677:Heterogeneous
4675:
4673:
4670:
4668:
4665:
4663:
4660:
4658:
4655:
4654:
4652:
4650:
4649:Architectures
4646:
4638:
4635:
4634:
4633:
4630:
4628:
4625:
4623:
4620:
4618:
4615:
4611:
4608:
4607:
4606:
4603:
4602:
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4509:
4503:
4500:
4498:
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4485:
4481:
4477:
4470:
4465:
4463:
4458:
4456:
4451:
4450:
4447:
4435:
4432:
4430:
4429:Metastability
4427:
4426:
4424:
4422:Design issues
4420:
4414:
4411:
4407:
4404:
4402:
4399:
4398:
4397:
4396:Digital video
4394:
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4389:
4387:
4384:
4380:
4377:
4376:
4375:
4374:Digital audio
4372:
4368:
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4364:
4363:
4360:
4359:
4357:
4353:
4345:
4342:
4341:
4340:
4337:
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4327:
4325:
4322:
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4315:
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4310:
4309:
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4300:
4296:
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4288:
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4286:
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4260:
4258:
4255:
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4238:
4236:
4233:
4231:
4228:
4226:
4223:
4221:
4218:
4216:
4213:
4212:
4210:
4206:
4199:
4196:
4193:
4190:
4187:
4184:
4181:
4178:
4175:
4172:
4169:
4166:
4163:
4160:
4157:
4154:
4151:
4148:
4146:
4143:
4140:
4137:
4134:
4131:
4128:
4125:
4123:
4120:
4117:
4114:
4111:
4108:
4106:
4103:
4101:
4098:
4096:
4093:
4091:
4088:
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4073:
4071:
4068:
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4061:
4058:
4056:
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4042:
4040:
4038:
4034:
4030:
4023:
4018:
4016:
4011:
4009:
4004:
4003:
4000:
3980:
3977:
3975:
3972:
3968:
3965:
3963:
3960:
3959:
3958:
3955:
3951:
3948:
3947:
3946:
3943:
3941:
3938:
3936:
3935:LatticeMico32
3933:
3931:
3928:
3927:
3925:
3923:
3919:
3913:
3910:
3908:
3905:
3903:
3900:
3898:
3895:
3893:
3890:
3888:
3885:
3883:
3880:
3878:
3875:
3874:
3872:
3870:
3866:
3863:
3861:
3855:
3849:
3846:
3844:
3841:
3839:
3836:
3834:
3831:
3829:
3826:
3824:
3821:
3820:
3818:
3814:
3808:
3805:
3803:
3800:
3798:
3795:
3794:
3792:
3788:
3785:
3781:
3775:
3772:
3770:
3767:
3765:
3762:
3760:
3757:
3755:
3752:
3750:
3747:
3745:
3742:
3740:
3737:
3735:
3732:
3730:
3727:
3725:
3722:
3720:
3717:
3715:
3712:
3710:
3707:
3706:
3704:
3700:
3694:
3691:
3689:
3686:
3684:
3681:
3679:
3676:
3674:
3671:
3669:
3666:
3664:
3661:
3659:
3656:
3654:
3651:
3649:
3646:
3644:
3641:
3639:
3636:
3634:
3631:
3629:
3626:
3622:
3619:
3618:
3617:
3616:SystemVerilog
3614:
3610:
3607:
3605:
3602:
3601:
3600:
3597:
3593:
3590:
3588:
3585:
3584:
3583:
3580:
3579:
3577:
3575:
3571:
3565:
3562:
3560:
3557:
3555:
3552:
3550:
3547:
3543:
3540:
3539:
3538:
3535:
3533:
3530:
3528:
3525:
3523:
3520:
3518:
3515:
3513:
3510:
3508:
3505:
3501:
3498:
3497:
3496:
3493:
3491:
3488:
3486:
3483:
3482:
3480:
3476:
3472:
3465:
3460:
3458:
3453:
3451:
3446:
3445:
3442:
3430:
3427:
3425:
3422:
3420:
3417:
3415:
3412:
3410:
3407:
3405:
3402:
3400:
3397:
3395:
3392:
3390:
3387:
3386:
3384:
3380:
3373:
3370:
3368:
3365:
3363:
3360:
3358:
3355:
3353:
3350:
3348:
3345:
3343:
3340:
3339:
3337:
3335:
3329:
3319:
3316:
3314:
3311:
3309:
3306:
3304:
3301:
3299:
3296:
3292:
3289:
3287:
3284:
3282:
3279:
3278:
3277:
3274:
3273:
3271:
3269:
3265:
3259:
3256:
3252:
3249:
3247:
3244:
3243:
3242:
3239:
3235:
3232:
3231:
3230:
3227:
3225:
3222:
3220:
3219:Demultiplexer
3217:
3215:
3212:
3211:
3209:
3207:
3203:
3197:
3194:
3192:
3189:
3186:
3184:
3181:
3179:
3176:
3174:
3171:
3169:
3166:
3165:
3163:
3161:
3157:
3151:
3148:
3146:
3143:
3141:
3140:Memory buffer
3138:
3136:
3135:Register file
3133:
3131:
3128:
3126:
3123:
3121:
3118:
3117:
3115:
3113:
3109:
3101:
3098:
3096:
3093:
3092:
3091:
3088:
3086:
3083:
3081:
3078:
3076:
3075:Combinational
3073:
3072:
3070:
3068:
3064:
3058:
3055:
3051:
3048:
3047:
3045:
3042:
3040:
3037:
3035:
3032:
3027:
3024:
3022:
3019:
3018:
3016:
3013:
3010:
3007:
3004:
3001:
2998:
2995:
2994:
2992:
2990:
2984:
2978:
2975:
2973:
2970:
2968:
2965:
2963:
2960:
2956:
2953:
2951:
2948:
2946:
2943:
2941:
2938:
2936:
2933:
2931:
2928:
2927:
2926:
2923:
2921:
2918:
2917:
2915:
2911:
2905:
2902:
2900:
2897:
2895:
2892:
2890:
2887:
2886:
2884:
2880:
2872:
2869:
2868:
2867:
2864:
2862:
2859:
2857:
2854:
2852:
2849:
2847:
2844:
2842:
2839:
2837:
2834:
2832:
2829:
2827:
2824:
2822:
2819:
2817:
2814:
2812:
2809:
2807:
2804:
2802:
2799:
2797:
2794:
2793:
2791:
2789:
2785:
2775:
2772:
2770:
2767:
2765:
2762:
2759:
2756:
2753:
2750:
2747:
2744:
2741:
2738:
2736:
2733:
2730:
2727:
2725:
2722:
2720:
2717:
2716:
2714:
2712:
2706:
2699:
2696:
2694:
2691:
2688:
2685:
2682:
2679:
2678:
2676:
2670:
2664:
2661:
2659:
2656:
2654:
2651:
2649:
2646:
2644:
2641:
2639:
2636:
2634:
2631:
2630:
2628:
2624:
2617:
2614:
2611:
2608:
2605:
2602:
2600:
2597:
2595:
2592:
2590:
2587:
2585:
2582:
2580:
2577:
2575:
2572:
2570:
2567:
2565:
2562:
2560:
2557:
2555:
2552:
2548:
2545:
2544:
2542:
2539:
2536:
2533:
2532:
2530:
2528:
2524:
2518:
2515:
2513:
2510:
2507:
2504:
2501:
2498:
2495:
2492:
2489:
2486:
2483:
2480:
2475:
2472:
2471:
2469:
2466:
2464:
2461:
2460:
2458:
2456:
2450:
2438:
2435:
2434:
2433:
2430:
2428:
2425:
2421:
2418:
2416:
2413:
2411:
2408:
2406:
2403:
2402:
2401:
2398:
2396:
2393:
2392:
2390:
2388:
2384:
2378:
2375:
2373:
2370:
2368:
2365:
2361:
2358:
2356:
2353:
2352:
2351:
2348:
2346:
2343:
2342:
2340:
2338:
2334:
2328:
2325:
2323:
2320:
2316:
2313:
2312:
2311:
2308:
2304:
2301:
2299:
2296:
2295:
2294:
2291:
2287:
2284:
2282:
2279:
2278:
2277:
2274:
2272:
2269:
2265:
2262:
2260:
2257:
2256:
2255:
2252:
2251:
2249:
2245:
2242:
2240:
2236:
2226:
2223:
2221:
2218:
2217:
2215:
2213:
2209:
2203:
2200:
2198:
2195:
2191:
2188:
2186:
2183:
2182:
2181:
2178:
2176:
2175:Scoreboarding
2173:
2172:
2170:
2168:
2164:
2158:
2157:False sharing
2155:
2153:
2150:
2148:
2145:
2143:
2140:
2139:
2137:
2135:
2131:
2125:
2122:
2120:
2117:
2115:
2112:
2111:
2109:
2107:
2103:
2100:
2098:
2094:
2084:
2081:
2079:
2076:
2074:
2071:
2068:
2064:
2061:
2059:
2056:
2054:
2051:
2049:
2046:
2045:
2043:
2041:
2038:
2036:
2033:
2031:
2028:
2026:
2023:
2021:
2018:
2016:
2013:
2011:
2008:
2006:
2003:
2001:
1998:
1996:
1993:
1991:
1988:
1986:
1983:
1979:
1976:
1974:
1971:
1969:
1966:
1965:
1963:
1961:
1958:
1956:
1953:
1951:
1950:Stanford MIPS
1948:
1946:
1943:
1941:
1938:
1936:
1933:
1931:
1928:
1926:
1923:
1922:
1920:
1914:
1906:
1903:
1902:
1901:
1898:
1896:
1893:
1891:
1888:
1886:
1883:
1881:
1878:
1876:
1873:
1871:
1868:
1864:
1861:
1860:
1859:
1856:
1852:
1849:
1848:
1847:
1844:
1842:
1839:
1837:
1834:
1832:
1829:
1827:
1824:
1823:
1821:
1817:
1814:
1812:
1811:architectures
1806:
1800:
1797:
1795:
1792:
1790:
1787:
1785:
1782:
1780:
1779:Heterogeneous
1777:
1773:
1770:
1768:
1765:
1764:
1763:
1760:
1758:
1755:
1751:
1748:
1746:
1743:
1741:
1738:
1736:
1733:
1732:
1731:
1730:Memory access
1728:
1726:
1723:
1721:
1718:
1716:
1713:
1711:
1708:
1704:
1701:
1700:
1699:
1696:
1694:
1691:
1689:
1686:
1685:
1683:
1681:
1677:
1669:
1666:
1664:
1663:Random-access
1661:
1659:
1656:
1654:
1651:
1650:
1649:
1646:
1644:
1643:Stack machine
1641:
1639:
1636:
1632:
1629:
1627:
1624:
1622:
1619:
1617:
1614:
1612:
1609:
1607:
1604:
1602:
1599:
1597:
1594:
1593:
1592:
1589:
1585:
1582:
1580:
1577:
1575:
1572:
1570:
1567:
1565:
1562:
1560:
1559:with datapath
1557:
1556:
1555:
1552:
1550:
1547:
1545:
1542:
1541:
1539:
1537:
1533:
1529:
1522:
1517:
1515:
1510:
1508:
1503:
1502:
1499:
1492:
1487:
1483:
1482:
1472:
1466:
1462:
1457:
1453:
1449:
1445:
1433:
1429:
1425:
1420:
1416:
1410:
1406:
1401:
1400:
1387:
1383:
1379:
1377:9783030119607
1373:
1369:
1365:
1361:
1354:
1346:
1342:
1338:
1332:
1328:
1321:
1313:
1307:
1303:
1296:
1294:
1277:
1273:
1267:
1259:
1247:
1231:
1230:
1223:
1215:
1214:
1209:
1202:
1187:
1183:
1179:
1173:
1171:
1169:
1167:
1158:
1154:
1150:
1144:
1139:
1138:
1129:
1127:
1122:
1110:
1107:
1104:
1101:
1098:
1095:
1092:
1089:
1086:
1083:
1081:(EDA or ECAD)
1080:
1077:
1074:
1071:
1068:
1065:
1064:
1057:
1054:
1052:
1047:
1045:
1041:
1037:
1033:
1029:
1025:
1021:
1013:
1009:
1000:
998:
988:
984:
982:
978:
974:
970:
964:
962:
958:
955:
951:
947:
943:
938:
936:
932:
923:
919:
908:
903:
900:
898:
894:
889:
885:
875:
872:
868:
866:
862:
857:
855:
851:
847:
843:
839:
834:
827:
822:
812:
810:
805:
803:
799:
795:
791:
787:
783:
779:
775:
771:
767:
764:, integrated
763:
759:
755:
751:
747:
743:
738:
736:
732:
727:
725:
721:
717:
713:
708:
706:
702:
697:
693:
690:stage of the
689:
688:metallization
685:
681:
677:
673:
665:
656:
654:
650:
646:
642:
637:
630:
626:
622:
618:
614:
610:
606:
602:
598:
595:computes the
594:
590:
587:
584:
580:
576:
572:
568:
564:
560:
556:
552:
548:
545:
542:
538:
534:
530:
527:
524:
519:
515:
511:
507:
504:
501:
500:test coverage
497:
493:
489:
485:
482:model, as in
481:
477:
473:
469:
465:
461:
460:
456:
453:
449:
445:
443:
439:
436:
432:
428:
427:
423:
422:
421:
419:
415:
411:
407:
403:
398:
396:
392:
388:
384:
380:
375:
368:
367:Standard cell
358:
356:
352:
348:
344:
339:
337:
333:
329:
325:
322:
318:
313:
311:
307:
303:
299:
298:standard-cell
295:
291:
289:
285:
283:
279:
275:
271:
267:
263:
253:
251:
247:
243:
239:
235:
231:
227:
225:
221:
217:
213:
209:
205:
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197:
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176:
174:
170:
166:
162:
158:
154:
150:
146:
142:
136:
113:
109:
100:
92:
88:
80:
77:
69:
59:
55:
49:
48:
42:
37:
28:
27:
22:
4692:Neuromorphic
4621:
4555:Cryptography
4511:Applications
4355:Applications
4191:
3892:LatticeMico8
3882:ARM Cortex-M
3858:Intellectual
3484:
3429:Chip carrier
3367:Clock gating
3286:Mixed-signal
3183:Write buffer
3160:Control unit
2972:Clock signal
2711:accelerators
2693:Cypress PSoC
2583:
2350:Simultaneous
2167:Out-of-order
1799:Neuromorphic
1680:Architecture
1638:Belt machine
1631:Zeno machine
1564:Hierarchical
1460:
1451:
1436:. Retrieved
1432:the original
1427:
1404:
1359:
1353:
1327:Logic Design
1326:
1320:
1301:
1280:. Retrieved
1275:
1266:
1234:. Retrieved
1228:
1222:
1211:
1201:
1189:. Retrieved
1181:
1136:
1055:
1048:
1023:
1019:
1017:
994:
985:
965:
956:
939:
929:
920:
916:
905:
901:
896:
892:
891:
873:
869:
858:
846:pre-designed
835:
832:
806:
739:
728:
709:
670:
638:
634:
588:
559:search space
546:
528:
505:
492:reprogrammed
468:test benches
457:
444:(RTL) design
440:
424:
399:
370:
340:
314:
292:
286:
259:
228:
208:flash memory
177:
111:
107:
105:
87:
72:
66:October 2015
63:
44:
4778:Gate arrays
4085:Memory cell
3922:Open-source
3869:Proprietary
3678:Flow to HDL
3500:Logic block
3214:Multiplexer
3178:Data buffer
2889:Single-core
2861:bit slicing
2719:Coprocessor
2574:Coprocessor
2455:performance
2377:Cooperative
2367:Speculative
2327:Distributed
2286:Superscalar
2271:Instruction
2239:Parallelism
2212:Speculative
2044:System/3x0
1916:Instruction
1693:Von Neumann
1606:Post–Turing
1438:14 December
838:performance
821:Full custom
798:peripherals
760:, standard
758:peripherals
712:performance
676:transistors
641:design flow
575:manufacture
569:enabling a
518:logic gates
351:polysilicon
321:ZX Spectrum
234:breadboards
184:logic gates
161:4000 series
157:7400 series
149:video codec
58:introducing
4767:Categories
4723:chronology
4584:Networking
4434:Runt pulse
4406:television
4100:Logic gate
4045:Transistor
4037:Components
3897:MicroBlaze
3848:Simulators
3828:Xilinx ISE
3334:management
3229:Multiplier
3090:Logic gate
3080:Sequential
2987:Functional
2967:Clock rate
2940:Data cache
2913:Components
2894:Multi-core
2882:Core count
2372:Preemptive
2276:Pipelining
2259:Bit-serial
2202:Wide-issue
2147:Structural
2069:Tilera ISA
2035:MicroBlaze
2005:ETRAX CRIS
1900:Comparison
1745:Load–store
1725:Endianness
1345:1132366891
1329:. EDTECH.
1282:28 January
1236:28 January
1191:9 November
1117:References
1042:in a data
863:(CAD) and
786:glue logic
762:interfaces
678:and other
672:Gate array
567:photomasks
496:fabricated
280:(DTL) and
262:gate array
165:fabricated
41:references
4713:Processor
4667:Multicore
4290:Placement
4080:Flip-flop
4060:Capacitor
3967:Microwatt
3962:Libre-SOC
3957:Power ISA
3940:OpenCores
3902:PicoBlaze
3709:Accellera
3702:Companies
3574:Languages
3268:Circuitry
3188:Microcode
3112:Registers
2955:coherence
2930:CPU cache
2788:Word size
2453:Processor
2097:Execution
2000:DEC Alpha
1978:Power ISA
1794:Cognitive
1601:Universal
1256:ignored (
1246:cite book
977:OpenCores
792:(such as
625:photomask
577:physical
541:optimized
533:placement
529:Placement
476:emulation
347:base dies
310:LSI Logic
250:amortized
4672:Manycore
4657:Dataflow
4610:C to HDL
4055:Inductor
4050:Resistor
3945:OpenRISC
3860:property
3838:ModelSim
3816:Software
3790:Hardware
3783:Products
3769:Synopsys
3739:Infineon
3714:Achronix
3673:C to HDL
3638:Handel-C
3478:Concepts
3206:Datapath
2899:Manycore
2871:variable
2709:Hardware
2345:Temporal
2025:OpenRISC
1720:Cellular
1710:Dataflow
1703:modified
1428:EE Times
1386:86596100
1272:"People"
1213:EE Times
1157:76935560
1060:See also
1036:customer
1032:function
946:IP cores
910:—
766:memories
649:IP cores
589:Sign-off
480:software
466:through
312:(1981).
302:Motorola
266:Ferranti
139:) is an
4701:Related
4528:DirectX
4295:Routing
4129:(3D IC)
3912:Nios II
3802:Stratix
3764:Siemens
3749:Lattice
3734:Cadence
3628:SystemC
3582:Verilog
3382:Related
3313:Quantum
3303:Digital
3298:Boolean
3196:Counter
3095:Quantum
2856:512-bit
2851:256-bit
2846:128-bit
2689:(MPSoC)
2674:on chip
2672:Systems
2490:(FLOPS)
2303:Process
2152:Control
2134:Hazards
2020:Itanium
2015:Unicore
1973:PowerPC
1698:Harvard
1658:Pointer
1653:Counter
1611:Quantum
1397:Sources
1012:Renesas
756:units,
748:like a
746:IP core
720:routing
694:. The
621:signoff
551:routing
547:Routing
523:netlist
410:netlist
270:bipolar
256:History
220:Verilog
175:chips.
159:or the
54:improve
4718:design
4577:scrypt
4484:Theory
4272:Design
4208:Theory
4194:(ASIC)
4188:(FPOA)
4182:(FPGA)
4176:(CPLD)
4141:(EPLD)
3974:RISC-V
3833:Vivado
3807:Virtex
3693:Chisel
3658:PALASM
3542:Xputer
3318:Switch
3308:Analog
3046:(IMC)
3017:(MMU)
2866:others
2841:64-bit
2836:48-bit
2831:32-bit
2826:24-bit
2821:16-bit
2816:15-bit
2811:12-bit
2648:Mobile
2564:Stream
2559:Barrel
2554:Vector
2543:(GPU)
2502:(SUPS)
2470:(IPC)
2322:Memory
2315:Vector
2298:Thread
2281:Scalar
2083:Others
2030:RISC-V
1995:SuperH
1964:Power
1960:MIPS-X
1935:PDP-11
1784:Fabric
1536:Models
1467:
1411:
1384:
1374:
1343:
1333:
1308:
1155:
1145:
1099:(VLSI)
1087:(FPGA)
1075:(CPLD)
1069:(ASIP)
1040:design
1026:is an
969:re-use
944:" are
842:analog
778:system
484:Simics
374:layout
296:(MOS)
204:EEPROM
192:memory
167:using
43:, but
4535:Audio
4523:GPGPU
4379:radio
4200:(TPU)
4170:(GAL)
4164:(PAL)
4158:(PLD)
4152:(PLA)
4135:(ECL)
4118:(HIC)
3744:Intel
3724:Aldec
3683:MyHDL
3609:VITAL
3374:(PPW)
3332:Power
3224:Adder
3100:Array
3067:Logic
3028:(TLB)
3011:(FPU)
3005:(AGU)
2999:(ALU)
2989:units
2925:Cache
2806:8-bit
2801:4-bit
2796:1-bit
2760:(TPU)
2754:(DSP)
2748:(PPU)
2742:(VPU)
2731:(GPU)
2700:(NoC)
2683:(SoC)
2618:(PoP)
2612:(SiP)
2606:(MCM)
2547:GPGPU
2537:(CPU)
2527:Types
2508:(PPW)
2496:(TPS)
2484:(IPS)
2476:(CPI)
2247:Level
2058:S/390
2053:S/370
2048:S/360
1990:SPARC
1968:POWER
1851:TRIPS
1819:Types
1382:S2CID
1105:(SoC)
1093:(MPC)
1051:modem
494:once
488:FPGAs
4627:CPLD
4622:ASIC
4617:FPGA
4589:Data
4112:(IC)
3950:1200
3907:Nios
3887:LEON
3688:ELLA
3668:CUPL
3663:ABEL
3643:Lola
3633:AHDL
3599:VHDL
3532:PSoC
3512:EPLD
3507:CPLD
3495:FPGA
3485:ASIC
3352:ACPI
3085:Glue
2977:FIFO
2920:Core
2658:ASIP
2599:CPLD
2594:FPOA
2589:FPGA
2584:ASIC
2437:SPMD
2432:MIMD
2427:MISD
2420:SWAR
2400:SIMD
2395:SISD
2310:Data
2293:Task
2264:Word
2010:M32R
1955:MIPS
1918:sets
1885:ZISC
1880:NISC
1875:OISC
1870:MISC
1863:EPIC
1858:VLIW
1846:EDGE
1836:RISC
1831:CISC
1740:HUMA
1735:NUMA
1465:ISBN
1440:2006
1409:ISBN
1372:ISBN
1341:OCLC
1331:ISBN
1306:ISBN
1284:2018
1258:help
1238:2018
1193:2019
1153:OCLC
1143:ISBN
1044:book
1024:ASSP
957:only
886:and
770:SRAM
651:and
615:and
389:and
319:and
317:ZX81
224:VHDL
112:ASIC
4560:TLS
4518:GPU
3979:Zet
3930:JOP
3877:ARC
3843:VTR
3797:iCE
3759:NXP
3729:Arm
3719:AMD
3653:UPF
3648:PSL
3621:DPI
3604:AMS
3592:AMS
3527:GAL
3522:PAL
3517:PLA
3490:SoC
3347:APM
3342:PMU
3234:CPU
3191:ROM
2962:Bus
2579:PAL
2254:Bit
2040:LMC
1945:ARM
1940:x86
1930:VAX
1364:doi
1022:or
1018:An
954:ARM
796:),
750:CPU
724:EDA
406:HDL
397:).
332:I/O
222:or
200:RAM
196:ROM
106:An
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