2305:
27:
571:
individually for each 4 KB page, stored in a translation table in local memory of Type 2 devices. Unlike other CPU-to-CPU memory coherency protocols, this arrangement only requires the host CPU memory controller to implement the cache agent; such asymmetric approach reduces implementation complexity and reduces latency.
582:
CXL 3.0 allows multiple Type 1 and Type 2 devices per each CXL root port; it also adds multi-level switching, helping implement device fabrics with non-tree topologies like mesh, ring, or spline/leaf. Each node can be a host or a device of any type. Type 3 devices can implement Global Fabric
Attached
423:
On August 2, 2022, the CXL Specification 3.0 was released, based on PCIe 6.0 physical interface and PAM-4 coding with double the bandwidth; new features include fabrics capabilities with multi-level switching and multiple device types per port, and enhanced coherency with peer-to-peer DMA and memory
578:
CXL 3.0 replaced bias modes with enhanced coherency semantics, allowing Type 2 and Type 3 devices to back invalidate the data in the host cache when the device has made a change to the local memory. Enhanced coherency also helps implement peer-to-peer transfers within a virtual hierarchy of devices
511:
CXL.cache and CXL.mem protocols operate with a common link/transaction layer, which is separate from the CXL.io protocol link and transaction layer. These protocols/layers are multiplexed together by an
Arbitration and Multiplexing (ARB/MUX) block before being transported over standard PCIe 5.0 PHY
359:
Consortiums announced plans to implement interoperability between the two technologies, with initial results presented in
January 2021. On November 10, 2021, Gen-Z specifications and assets were transferred to CXL, to focus on developing a single industry standard. At the time of this announcement,
450:
announced a 128 GB DDR5 based memory expansion module that allows for terabyte level memory expansion along with high performance for use in data centres and potentially next generation PCs. An updated 512 GB version based on a proprietary memory controller was released on May 10, 2022.
570:
Type 2 devices implement two memory coherence modes, managed by device driver. In device bias mode, device directly accesses local memory, and no caching is performed by the CPU; in host bias mode, the host CPU's cache controller handles all access to device memory. Coherence mode can be set
411:
On
November 10, 2020, the CXL Specification 2.0 was released. The new version adds support for CXL switching, to allow connecting multiple CXL 1.x and 2.0 devices to a CXL 2.0 host processor, and/or pooling each device to multiple host processors, in
495:– based on PCIe 5.0 (and PCIe 6.0 after CXL 3.0) with a few enhancements, it provides configuration, link initialization and management, device discovery and enumeration, interrupts, DMA, and register I/O access using non-coherent loads/stores.
565:
Type 3 (CXL.io and CXL.mem) – allow the host to access and manage attached device memory, memory expansion boards and persistent memory. Devices provide host CPU with low-latency access to local DRAM or byte-addressable non-volatile
367:
specifications and assets were transferred to the CXL Consortium, which now includes companies behind memory coherent interconnect technologies such as OpenCAPI (IBM), Gen-Z (HPE), and CCIX (Xilinx) open standards, and proprietary
583:
Memory (GFAM) mode, which connects a memory device to a switch node without requiring direct host connection. Devices and hosts use Port Based
Routing (PBR) addressing mechanism that supports up to 4,096 nodes.
574:
CXL 2.0 added support for switching in tree-based device fabrics, allowing PCIe, CXL 1.1 and CXL 2.0 devices to form virtual hierarchies of single- and multi-logic devices that can be managed by multiple hosts.
579:
in the same coherency domain. It also supports memory sharing of the same memory segment between multiple devices, as opposed to memory pooling where each device was assigned a separate segment.
891:
847:
750:
501:– defines interactions between a host and a device, allows peripheral devices to coherently access and cache host CPU memory with a low latency request/response interface.
1310:
943:
420:
configurations; it also implements device integrity and data encryption. There is no bandwidth increase from CXL 1.x, because CXL 2.0 still utilizes PCIe 5.0 PHY.
507:– allows host CPU to coherently access device-attached memory with load/store commands for both volatile (RAM) and persistent non-volatile (flash memory) storage.
1347:
1430:
1194:
1169:
520:(CRC) value. CXL FLITs encapsulate PCIe standard Transaction Layer Packet (TLP) and Data Link Layer Packet (DLLP) data with a variable frame size format.
721:
562:
local memory. Devices can coherently access host CPU's memory and/or provide coherent or non-coherent access to device local memory from the host CPU.
823:
2327:
1141:
1030:
983:
2300:
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
1499:
1219:
2332:
1745:
1377:
1100:
915:
2273:
1447:
1329:
1252:
1902:
1271:
801:
608:
1233:
1765:
345:
1572:
1045:
666:"Synopsys Delivers Industry's First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs"
1487:
1460:
1087:
1953:
1624:
969:
947:
665:
2342:
1008:
1659:
1155:
542:
Type 2 (CXL.io, CXL.cache and CXL.mem) – coherently access host memory and device memory, general-purpose accelerators (
2006:
1845:
1775:
469:
1835:
349:
1933:
455:
1348:"Introduction to Compute Express Link (CXL): The CPU-To-Device Interconnect Breakthrough - Compute Express Link"
1725:
1514:
776:
2277:
1928:
1897:
408:
on accelerator devices with a cache coherent protocol. The CXL Specification 1.1 was released in June, 2019.
389:
1550:
591:
In May 2022 the first 512 GB devices became available with 4 times more storage than previous devices.
1875:
484:
The CXL transaction layer is composed of three dynamically multiplexed (they change accordingly to demand)
385:
373:
404:
On March 11, 2019, the CXL Specification 1.0 based on PCIe 5.0 was released. It allows host CPU to access
2201:
2140:
1995:
1800:
1565:
1088:
CXL Consortium and OpenCAPI Consortium Sign Letter of Intent to
Transfer OpenCAPI Specifications to CXL
535:
Type 1 (CXL.io and CXL.cache) – coherently access host memory, specialized accelerators (such as smart
513:
233:
2170:
848:"Compute Express Link Consortium (CXL) Officially Incorporates; Announces Expanded Board of Directors"
722:"Compute Express Link Consortium (CXL) Officially Incorporates; Announces Expanded Board of Directors"
539:, PGAS NIC, and NIC Atomics) with no local memory. Devices rely on coherent access to host CPU memory.
1855:
413:
543:
196:
capabilities allows CXL memory to overcome performance and socket packaging limitations of common
2308:
2283:
2175:
1830:
1448:
https://www.flashmemorysummit.com/Proceedings2019/08-07-Wednesday/20190807_CTRL-202A-1_Lender.pdf
1311:"CXL Consortium Showcases First Public Demonstrations of Compute Express Link Technology at SC21"
1076:
517:
162:
892:"AMD Joins Consortia to Advance CXL, a New High-Speed Interconnect for Breakthrough Performance"
1865:
693:
536:
249:
2337:
2129:
2082:
1938:
1710:
1558:
1170:"How do the new Intel Agilex FPGA family and the CXL coherent interconnect fabric intersect?"
559:
417:
293:
2125:
1978:
620:
297:
170:
126:
1195:"Samsung Unveils Industry-First Memory Module Incorporating New CXL Interconnect Standard"
8:
2037:
1592:
1488:
https://www.computeexpresslink.org/_files/ugd/0c1418_a8713008916044ae9604405d10a7773b.pdf
1431:"Introduction to Compute Express Link (CXL): The CPU-To-Device Interconnect Breakthrough"
257:
1581:
929:
473:
356:
341:
321:
305:
289:
2027:
1649:
1585:
1296:
1123:
301:
1253:"AMD Unveils Zen 4 CPU Roadmap: 96-Core 5nm Genoa in 2022, 128-Core Bergamo in 2023"
1760:
1890:
1740:
1720:
1595:
1063:
824:"CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel"
377:
333:
181:
1077:
OpenCAPI to Fold into CXL - CXL Set to Become
Dominant CPU Interconnect Standard
2191:
1885:
1810:
1735:
1639:
1614:
1142:"Compute Express Link (CXL) 3.0 Announced: Doubled Speeds and Flexible Fabrics"
673:
641:
225:
1407:
2321:
2263:
2150:
2042:
1990:
1973:
1755:
1654:
1644:
1619:
1580:
865:
729:
405:
217:
213:
189:
165:(CPU)-to-device and CPU-to-memory connections, designed for high performance
158:
2000:
1943:
1795:
1700:
177:
472:(SC21) by vendors including Intel, Astera, Rambus, Synopsys, Samsung, and
336:, among others, were contributing members. Industry partners include the
2268:
2247:
2165:
2010:
1948:
1923:
1850:
1634:
1629:
1500:"Samsung Electronics Introduces Industry's First 512GB CXL Memory Module"
1220:"Samsung Electronics Introduces Industry's First 512GB CXL Memory Module"
440:
193:
185:
173:
166:
26:
2087:
2121:
1820:
1609:
369:
176:(PCIe) physical and electrical interface and includes PCIe-based block
1031:"CXL™ Consortium and Gen-Z Consortium™ MoU Update: A Path to Protocol"
2145:
2135:
2102:
2097:
2032:
1907:
1695:
1680:
1675:
381:
248:, and officially incorporated in September 2019. As of January 2022,
245:
1543:
1378:"Compute Express Link Standard | DesignWare IP | Synopsys"
516:(FLIT) block consisting of four 16-byte data 'slots' and a two-byte
137:
2155:
2092:
1825:
1685:
1156:"Compute Express Link (CXL) 3.0 Debuts, Wins CPU Interconnect Wars"
599:
CXL memory controllers typically add about 200 ns of latency.
364:
329:
325:
309:
281:
273:
269:
265:
221:
212:. The CXL Consortium was formed in March 2019 by founding members
2288:
2242:
2226:
2052:
1870:
1815:
1750:
1705:
447:
337:
317:
1458:
2221:
2112:
2077:
2072:
2067:
2062:
1880:
1770:
1730:
1690:
393:
313:
285:
261:
253:
237:
229:
2206:
2117:
1101:"Finally, A Coherent Interconnect Strategy: CXL Absorbs Gen-Z"
427:
On
November 14, 2023, the CXL Specification 3.1 was released.
2216:
2107:
2047:
1985:
1958:
1840:
1790:
1715:
1330:"CXL Consortium Makes a Splash at Supercomputing 2021 (SC21)"
1272:"Intel Sapphire Rapids CXL with Emmitsburg PCH Shown at SC21"
916:"CXL Consortium and PCI-SIG Announce Marketing MOU Agreement"
701:
459:
436:
241:
209:
55:
1009:"CXL Consortium and Gen-Z Consortium Announce MOU Agreement"
984:"CXL Consortium and Gen-Z Consortium Announce MOU Agreement"
2211:
2196:
2057:
1968:
1963:
1805:
802:"Intel, Google and others join forces for CXL interconnect"
614:
555:
551:
547:
462:
197:
105:
86:
2160:
1785:
1780:
1056:
523:
CXL 3.0 introduces 256-byte FLIT in PAM-4 transfer mode.
277:
1372:
1370:
1368:
360:
70% of Gen-Z members already joined the CXL Consortium.
16:
Open standard processor interconnection for data centers
1409:
Introduction to
Compute Express Link™ (CXL™) Technology
531:
CXL is designed to support three primary device types:
1092:
1365:
264:
joined the founders on the board of directors, while
1483:
1481:
1459:Danny Volkind and Elad Shlisberg (June 15, 2022).
1452:
1422:
1226:
1124:"Compute Express Link (CXL): All you need to know"
1118:
1116:
1114:
200:memory when implementing high storage capacities.
1148:
970:"DMTF and CXL Consortium Establish Work Register"
944:"SNIA and CXL Consortium Form Strategic Alliance"
454:In 2021, CXL 1.1 support was announced for Intel
2319:
1478:
840:
1903:Coherent Accelerator Processor Interface (CAPI)
1321:
1269:
1111:
793:
355:On April 2, 2020, the Compute Express Link and
1441:
1405:
1134:
1099:Morgan, Timothy Prickett (November 23, 2021).
858:
208:The CXL technology was primarily developed by
1566:
1461:"CXL 1.1 vs CXL 2.0 – What's the difference?"
1212:
1429:Consortium, C. X. L. (September 23, 2019).
1250:
889:
161:interconnect for high-speed, high capacity
1573:
1559:
1428:
1328:Consortium, C. X. L. (December 16, 2021).
1327:
1263:
1044:Consortium, C. X. L. (November 10, 2021).
1043:
25:
1289:
817:
815:
1303:
609:Coherent Accelerator Processor Interface
192:(CXL.mem). The serial communication and
1502:(Press release). Samsung. May 10, 2022.
799:
2328:Computer-related introductions in 2019
2320:
1098:
812:
615:Universal Chiplet Interconnect express
1554:
1515:"Just How Bad Is CXL Memory Latency?"
1401:
1399:
1397:
1395:
1393:
1391:
777:"Just How Bad Is CXL Memory Latency?"
1512:
1270:Patrick Kennedy (December 7, 2021).
774:
512:using fixed-width 528 bit (66 byte)
1244:
890:Papermaster, Mark (July 18, 2019).
866:"Compute Express Link: Our Members"
821:
13:
1388:
989:. Beaverton, Oregon. April 2, 2020
470:ACM/IEEE Supercomputing Conference
465:"Genoa" and "Bergamo" processors.
430:
14:
2354:
2333:Peripheral Component Interconnect
1535:
946:. 3 November 2020. Archived from
399:
2304:
2303:
1251:Paul Alcorn (November 8, 2021).
800:Calvert, Will (March 13, 2019).
1506:
1492:
1340:
1187:
1162:
1081:
1070:
1037:
1023:
1001:
976:
962:
936:
922:
908:
883:
526:
169:computers. CXL is built on the
768:
743:
714:
686:
658:
634:
468:CXL devices were shown at the
62:
1:
1898:Intel Ultra Path Interconnect
1406:CXL Consortium (2021-04-02).
1234:"Intel Architecture Day 2021"
627:
1876:Intel QuickPath Interconnect
1866:Direct Media Interface (DMI)
694:"A Milestone in Moving Data"
479:
7:
1513:Mann, Tobias (2022-12-05).
1297:"CXL Put Through Its Paces"
775:Mann, Tobias (2022-12-05).
602:
10:
2359:
2343:Motherboard expansion slot
1861:Compute Express Link (CXL)
806:www.datacenterdynamics.com
594:
586:
439:announced their family of
234:Hewlett Packard Enterprise
203:
180:protocol (CXL.io) and new
39:; 5 years ago
2297:
2256:
2235:
2184:
2098:IEEE-1284 (parallel port)
2020:
2013:logical device interface)
1916:
1668:
1602:
414:distributed shared memory
132:
122:
72:
61:
51:
33:
24:
755:www.electronicdesign.com
554:) with high-performance
184:protocols for accessing
1064:"CXL Will Absorb Gen-Z"
518:cyclic redundancy check
163:central processing unit
1660:List of bus bandwidths
1352:computeexpresslink.org
1046:"Exploring the Future"
854:. September 17, 2019.
418:disaggregated storage
2103:IEEE-1394 (FireWire)
1841:PCI Extended (PCI-X)
1435:Compute Express Link
1418:– via YouTube.
1334:Compute Express Link
1299:. December 10, 2021.
1050:Compute Express Link
918:. 23 September 2021.
852:www.businesswire.com
726:www.businesswire.com
646:Compute Express Link
621:Data processing unit
396:(Nvidia) protocols.
298:Microchip Technology
151:Compute Express Link
20:Compute Express Link
1944:Parallel ATA (PATA)
930:"Industry Liaisons"
458:processors and AMD
363:On August 1, 2022,
258:Samsung Electronics
140:.computeexpresslink
21:
1851:PCI Express (PCIe)
1066:. 9 December 2021.
950:on 16 January 2022
488:on a single link:
435:On April 2, 2019,
306:Oracle Corporation
290:Marvell Technology
19:
2315:
2314:
2301:
2028:Apple Desktop Bus
2005:PCI Express (via
1964:Serial ATA (SATA)
1650:Network on a chip
1519:The Next Platform
1105:The Next Platform
781:The Next Platform
757:. 13 October 2021
670:finance.yahoo.com
514:Flow Control Unit
446:On May 11, 2021,
242:Intel Corporation
148:
147:
96:63.015 GB/s (×16)
2350:
2307:
2306:
2299:
1761:HP Precision Bus
1575:
1568:
1561:
1552:
1551:
1547:
1546:
1544:Official website
1529:
1528:
1526:
1525:
1510:
1504:
1503:
1496:
1490:
1485:
1476:
1475:
1473:
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1450:
1445:
1439:
1438:
1426:
1420:
1419:
1417:
1416:
1403:
1386:
1385:
1382:www.synopsys.com
1374:
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1338:
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1185:
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1166:
1160:
1159:
1158:. 2 August 2022.
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1021:
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1016:
1005:
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998:
996:
994:
988:
980:
974:
973:
972:. 14 April 2020.
966:
960:
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940:
934:
933:
926:
920:
919:
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905:
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690:
684:
683:
681:
680:
662:
656:
655:
653:
652:
638:
188:(CXL.cache) and
144:
141:
139:
115:121.0 GB/s (×16)
64:
47:
45:
40:
29:
22:
18:
2358:
2357:
2353:
2352:
2351:
2349:
2348:
2347:
2318:
2317:
2316:
2311:
2302:
2293:
2252:
2231:
2180:
2093:IEEE-488 (GPIB)
2016:
1912:
1891:Infinity Fabric
1721:Europe Card Bus
1664:
1598:
1579:
1542:
1541:
1538:
1533:
1532:
1523:
1521:
1511:
1507:
1498:
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1062:
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1057:
1042:
1038:
1033:. 24 June 2021.
1029:
1028:
1024:
1014:
1012:
1011:. April 2, 2020
1007:
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589:
529:
482:
474:Teledyne LeCroy
456:Sapphire Rapids
443:featuring CXL.
433:
431:Implementations
402:
394:NVLink/NVSwitch
378:Infinity Fabric
334:Western Digital
206:
136:
118:
112:7.563 GB/s (×1)
100:
99:
93:3.938 GB/s (×1)
77:
43:
41:
38:
17:
12:
11:
5:
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2209:
2204:
2202:Intel HD Audio
2199:
2194:
2192:ADAT Lightpipe
2188:
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2179:
2178:
2173:
2168:
2163:
2158:
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2148:
2143:
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1886:HyperTransport
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1640:Bus contention
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1615:Front-side bus
1612:
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1596:computer buses
1578:
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1536:External links
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882:
870:CXL Consortium
857:
839:
822:Cutress, Ian.
811:
792:
767:
742:
713:
698:Intel Newsroom
685:
674:Yahoo! Finance
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632:
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2264:Multidrop bus
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2171:External PCIe
2169:
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2159:
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2151:Parallel SCSI
2149:
2147:
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2043:Commodore bus
2041:
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2031:
2029:
2026:
2025:
2023:
2019:
2012:
2008:
2004:
2002:
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1989:
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985:
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486:sub-protocols
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461:
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452:
449:
444:
442:
438:
428:
425:
421:
419:
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409:
407:
406:shared memory
397:
395:
392:(Intel), and
391:
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231:
227:
223:
219:
218:Cisco Systems
215:
214:Alibaba Group
211:
201:
199:
195:
191:
190:device memory
187:
186:system memory
183:
179:
175:
172:
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164:
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159:open standard
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152:
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84:
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67:
60:
57:
54:
50:
36:
32:
28:
23:
2338:Serial buses
1860:
1796:TURBOchannel
1586:
1522:. Retrieved
1518:
1508:
1494:
1470:November 18,
1468:. Retrieved
1454:
1443:
1434:
1424:
1413:. Retrieved
1408:
1381:
1356:. Retrieved
1354:. 2019-09-23
1351:
1342:
1333:
1323:
1314:
1305:
1291:
1281:November 18,
1279:. Retrieved
1275:
1265:
1256:
1246:
1237:
1228:
1214:
1203:. Retrieved
1201:. 2021-05-11
1198:
1189:
1178:. Retrieved
1176:. 2019-05-03
1173:
1164:
1150:
1136:
1127:
1104:
1094:
1083:
1072:
1058:
1049:
1039:
1025:
1013:. Retrieved
1003:
991:. Retrieved
978:
964:
952:. Retrieved
948:the original
938:
924:
910:
899:. Retrieved
895:
885:
874:. Retrieved
869:
860:
851:
842:
831:. Retrieved
827:
805:
795:
784:. Retrieved
780:
770:
759:. Retrieved
754:
745:
734:. Retrieved
732:. 2019-09-17
725:
716:
705:. Retrieved
697:
688:
677:. Retrieved
669:
660:
649:. Retrieved
645:
636:
598:
590:
581:
577:
573:
569:
530:
527:Device types
522:
510:
504:
498:
492:
485:
483:
467:
453:
445:
441:Agilex FPGAs
434:
426:
422:
410:
403:
376:(Mellanox),
362:
354:
207:
178:input/output
154:
150:
149:
101:
82:
78:
34:Year created
2269:CoreConnect
2248:ExpressCard
2176:Thunderbolt
2166:Camera Link
1949:Bus and Tag
1635:Address bus
1630:Control bus
1625:Daisy chain
1466:. UnifabriX
751:"StackPath"
642:"ABOUT CXL"
174:PCI Express
167:data center
76:Full duplex
2322:Categories
2122:ACCESS.bus
2021:Peripheral
1821:InfiniBand
1816:HP GSC bus
1610:System bus
1524:2023-02-03
1415:2024-07-16
1358:2024-07-16
1205:2021-05-11
1180:2019-08-09
954:16 January
901:2020-09-25
876:2020-09-25
833:2019-08-09
786:2023-02-03
761:2023-02-03
736:2019-11-09
707:2019-11-09
679:2019-11-09
651:2019-08-09
628:References
390:Ultra Path
370:InfiniBand
65:of devices
52:Created by
2083:Lightning
2033:Atari SIO
1908:SpaceWire
1741:Zorro III
1681:S-100 bus
1676:SS-50 bus
1669:Standards
1589:standards
1582:Technical
1174:PSG@Intel
1015:April 11,
828:Anandtech
499:CXL.cache
480:Protocols
424:sharing.
386:QuickPath
382:Omni-Path
246:Microsoft
2309:Category
2284:Wishbone
2257:Embedded
2236:Portable
2156:Profibus
2088:DMX512-A
1974:Parallel
1826:Ethernet
1736:Zorro II
1686:Multibus
1587:de facto
603:See also
566:storage.
365:OpenCAPI
330:Synopsys
326:SK Hynix
310:Qualcomm
294:Mellanox
282:Keysight
274:Ericsson
270:Broadcom
222:Dell EMC
157:) is an
2289:SLIMbus
2243:PC Card
2227:TOSLINK
1917:Storage
1871:RapidIO
1751:FASTBUS
1706:STD Bus
1603:General
1315:HPCwire
1199:Samsung
595:Latency
587:Devices
505:CXL.mem
448:Samsung
380:(AMD),
338:PCI-SIG
322:Seagate
318:Renesas
236:(HPE),
204:History
194:pooling
133:Website
42: (
2222:S/PDIF
2113:1-Wire
2078:RS-485
2073:RS-423
2068:RS-422
2063:RS-232
1924:ST-506
1881:NVLink
1731:STEbus
1691:Unibus
1128:Rambus
872:. 2020
617:(UCIe)
611:(CAPI)
493:CXL.io
348:, and
332:, and
314:Rambus
302:Micron
286:Kioxia
262:Xilinx
254:Nvidia
238:Huawei
230:Google
171:serial
127:Serial
2217:McASP
2185:Audio
2130:SMBus
2126:PMBus
2108:UNI/O
2048:HP-IL
2001:SATAe
1986:ESCON
1959:HIPPI
1791:NuBus
1746:CAMAC
1716:Q-Bus
1711:SMBus
1696:VAXBI
1593:wired
1464:(PDF)
1238:Intel
987:(PDF)
702:Intel
623:(DPU)
460:Zen 4
437:Intel
357:Gen-Z
342:Gen-Z
210:Intel
123:Style
73:Speed
56:Intel
2274:AMBA
2212:MADI
2197:AES3
2058:MIDI
2011:NVMe
2007:AHCI
1969:SCSI
1954:DSSI
1929:ESDI
1806:SBus
1766:EISA
1701:MBus
1591:for
1584:and
1472:2022
1283:2022
1017:2020
995:2020
956:2022
556:GDDR
552:FPGA
548:ASIC
463:EPYC
416:and
384:and
374:RoCE
350:DMTF
346:SNIA
260:and
244:and
226:Meta
198:DIMM
142:.org
106:GT/s
104:(64
87:GT/s
85:(32
68:4096
44:2019
37:2019
2278:AXI
2207:I²S
2161:USB
2146:D²B
2141:SPI
2136:I3C
2118:I²C
2053:HIL
2038:DCB
2009:or
1996:SSA
1979:SAS
1939:SMD
1934:IPI
1856:AGP
1846:PXI
1836:PCI
1831:UPA
1811:VLB
1801:MCA
1786:VPX
1781:VXS
1776:VXI
1771:VME
1756:LPC
1726:ISA
560:HBM
558:or
550:or
544:GPU
537:NIC
278:IBM
266:ARM
250:AMD
155:CXL
138:www
108:):
102:3.x
89:):
83:2.0
79:1.x
63:No.
2324::
2128:,
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764:.
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654:.
388:/
153:(
46:)
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
