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The display hardware also provided an interface for a keyboard and mouse. Sixty times per second, the MDC wrote to the memory the position of the mouse and an unencoded bitmap representing the state of the keyboard. As a result of implementing the MDC as an I/O device, the
Firefly supported multiple
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While DEC used existing components for most of the I/O system, the display controller was designed specifically for the
Firefly by the project's engineers who felt that no existing product met their performance requirements. There were two displayer controllers, one providing color graphics, and the
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and over the MBus. Memory was implemented by one to four memory modules that connect to the MBus. The original
Firefly had a master memory module with a capacity of 4 MB and up to three slave memory modules of the same capacity for a memory capacity of 4 to 16 MB. Later Firefly systems used a memory
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The
Firefly contained a primary processor board and zero, one, two or three secondary processor boards. These processor boards were 8 by 10 inches large. The primary processor board contained a microprocessor, its floating-point coprocessor and cache, and the Q-Bus control logic. The secondary
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microprocessors, CVAX Floating Point Chips (floating-point coprocessors). The processor boards communicated with each other and the memory via the MBus. The components used in the processor boards of the original
Firefly were the same as those originally designed for the MicroVAX II system.
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run unmodified image on the
Firefly. In contrast to Ultrix, Topaz supported processes with multiple threads which could span multiple processors, and the Taos system could run both Ultrix and Topaz applications at the same time.
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I/O devices were connected to the system via the Q-Bus, whose 22-bit address space was mapped onto the 24-bit memory address space of the
Firefly by using mapping registers controlled by the master processor. The devices used
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module with a capacity of 32 MB, for a memory capacity of 32 to 128 MB. The memory access time in the original MicroVAX-based
Firefly was 400 ns, while the CVAX version had a memory access time of 200 ns.
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The monochrome display controller (MDC) was contained on a board half as large as the processor boards and was capable of achieving a resolution of 1024 by 768 pixels. It contained a 16-bit
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other monochrome graphics. These controllers operated by checking a work queue set up in the memory using DMA, providing fully symmetric access to the display hardware by all processors.
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to ensure cache coherency. The caches on the MicroVAX processor boards had a capacity of 16 KB (4,096 4-byte lines) and were implemented with eleven 2 KB (4-bit by 4,096-word)
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microprocessor clocked at 10 MHz with a 10 KB memory containing 2,048 40-bit words of microinstruction memory. A 1024 by 1024-pixel frame buffer was implemented with
187:(PAL) devices. The caches on CVAX processor boards differed only in the capacity: 64 KB (16,384 4-byte lines) and were implemented with 8 KB (4-bit by 16,384-word) SRAMs.
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The 29116 microprocessor periodically checked a work queue set up in the memory using DMA and executed commands from that queue. The commands performed
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processor boards each contained two microprocessors, their floating-point coprocessors and caches. The original
Firefly processor boards used the
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operations within the frame buffer, between the system memory and frame buffer and were also used to paint characters from the font cache.
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126:. The second version of the Firefly used faster CVAX 78034 microprocessors. It was later introduced as a product by DEC as the
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also supported
Firefly in a configuration with one CVAX and four Microvax-II CPUs in a BA123 chassis and QVSS?VCB01 graphics.
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microprocessors. The cache from each of the microprocessors kept a consistent view of the same main memory using a
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The caches in the Firefly were direct-mapped for simplicity and to support multiprocessing; they used the
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microprocessor and MicroVAX 78132 floating-point coprocessor, but later Firefly systems used the faster
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Originally, the system was designed to use Motorola 68010 processors within this general architecture.
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213:(DMA) to access the memory though the cache of the main processor. The Firefly's I/O devices were: a
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183:(TTL) devices. The cache control logic was implemented with fifteen devices, mostly consisting of
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Charles P. Thacker, Lawrence C. Stewart, Edwin H. Satterthwaite Jr. (30 December 1987).
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Processors in the Firefly communicated with the main memory through their individual
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specialized racked computer as only one of the microprocessors had access to a
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binary calling interface, allowed existing Ultrix binaries compiled for the
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extended language) was used to program both Topaz and its applications.
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Computer's descriptive message about VAX3520/40 Firefox Firefly product
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Evolving the UNIX System Interface to Support Multithreaded Programs
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display controllers in one system connected to multiple monitors.
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Two of the variants of the Firefly used system software called
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364:(Technical report). Digital Systems Research Center
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114:. The first version built contained up to seven
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150:interface that implemented the I/O subsystem.
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413:: CS1 maint: multiple names: authors list (
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861:Compaq Professional Workstation 1000 XP
398:"Firefly: A Multiprocessor Workstation"
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930:Computer-related introductions in 1984
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387:Paul R. McJones and Garret F. Swart, "
355:Thacker, Charles (22 September 1984).
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78:1024 by 768 pixel monochrome display
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110:, a research organization within
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244:with the rest available for the
815:DEC 7000 AXP and DEC 10000 AXP
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466:Digital Equipment Corporation
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337:protocol used by the Firefly.
215:monochrome display controller
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112:Digital Equipment Corporation
29:Digital Equipment Corporation
845:Digital Personal Workstation
759:Digital Personal Workstation
425:A Multiprocessor Workstation
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185:programmable array logic
358:The Firefly Workstation
108:Systems Research Center
32:Systems Research Center
716:VAX 7000 and VAX 10000
391:", 28 September 1987.
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876:List of VAX computers
225:Ethernet controller.
866:Itsy Pocket Computer
319:V (operating system)
211:direct memory access
138:Hardware description
128:VAXstation 3520/3540
61:V (operating system)
142:The Firefly was an
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86:Keyboard and mouse
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840:AlphaStation
825:DEC 2000 AXP
810:DEC 4000 AXP
805:DEC 3000 AXP
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612:DECSYSTEM-20
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366:. Retrieved
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835:AlphaServer
734:Rainbow 100
368:21 November
284:microkernel
248:or used to
179:and twenty
104:workstation
48:workstation
20:DEC Firefly
919:Categories
782:DECstation
749:DECstation
681:VAXstation
342:References
165:CVAX 78034
154:Processors
130:codenamed
691:VAXserver
468:computers
308:Modula-2+
25:Developer
894:Category
854:See also
706:VAX 9000
701:VAX 4000
696:VAX 6000
676:VAX 8000
671:MicroVAX
409:cite web
325:See also
312:Modula-2
303:MicroVAX
290:and the
267:Software
16:Computer
904:Commons
739:VAXmate
686:Firefly
573:DECmate
561:PDP-8/e
420:Alt URL
292:Trestle
288:the Nub
252:fonts.
234:Am29116
221:and an
132:Firefox
94:Firefly
75:Display
830:Multia
764:HiNote
754:Multia
666:VAX-11
630:PDP-11
622:16-bit
607:PDP-10
594:36-bit
578:PDP-14
568:PDP-12
544:LINC-8
531:12-bit
521:PDP-15
493:18-bit
333:- The
299:Ultrix
286:named
257:BitBlt
242:bitmap
197:caches
191:Memory
96:was a
67:Memory
59:Taos,
797:Alpha
744:DECpc
711:VAXft
602:PDP-6
556:PDP-8
551:PDP-5
516:PDP-9
511:PDP-7
506:PDP-4
501:PDP-1
401:(PDF)
362:(PDF)
310:, (a
273:Topaz
250:cache
238:VRAMs
223:DEQNA
219:RQDX3
177:SRAMs
148:Q-Bus
83:Input
774:MIPS
539:LINC
415:link
370:2021
277:Taos
92:The
38:Type
726:x86
658:VAX
475:PDP
204:I/O
921::
411:}}
407:{{
134:.
458:e
451:t
444:v
417:)
403:.
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