823:). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200 GB per second.
428:(ISA) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply
36:
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453:/s maximum 8-bit transfer capability at 5 MHz, but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the
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data per request, until the entire block of data has been transferred. By continually obtaining and releasing the control of the system bus, the DMA controller essentially interleaves instruction and data transfers. The CPU processes an instruction, then the DMA controller transfers one data value, and so on. Data is not transferred as quickly, but CPU is not idled for as long as in burst mode. Cycle stealing mode is useful for controllers that monitor data in real time.
485:) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were
2326:
176:
728:(NICs) to DMA directly to the Last level cache (L3 cache) of local CPUs and avoid costly fetching of the I/O data from system RAM. As a result, DDIO reduces the overall I/O processing latency, allows processing of the I/O to be performed entirely in-cache, prevents the available RAM bandwidth/latency from becoming a performance bottleneck, and may lower the power consumption by allowing RAM to remain longer in low-powered state.
276:, an entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of data in the data block before releasing control of the system buses back to the CPU, but renders the CPU inactive for relatively long periods of time. The mode is also called "Block Transfer Mode".
645:, which will in turn convert them to DDR operations and send them out on the memory bus. As a result, there are quite a number of steps involved in a PCI DMA transfer; however, that poses little problem, since the PCI device or PCI bus itself are an order of magnitude slower than the rest of the components (see
317:
Transparent mode takes the most time to transfer a block of data, yet it is also the most efficient mode in terms of overall system performance. In transparent mode, the DMA controller transfers data only when the CPU is performing operations that do not use the system buses. The primary advantage of
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signals, which are the two signals controlling the interface between the CPU and the DMA controller. However, in cycle stealing mode, after one unit of data transfer, the control of the system bus is deasserted to the CPU via BG. It is then continually requested again via BR, transferring one unit of
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system, also known as a first-party DMA system, the CPU and peripherals can each be granted control of the memory bus. Where a peripheral can become a bus master, it can directly write to system memory without the involvement of the CPU, providing memory address and control signals as required. Some
401:
segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1,
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for DMA writes or cache flush for DMA reads. Non-coherent systems leave this to software, where the OS must then ensure that the cache lines are flushed before an outgoing DMA transfer is started and invalidated before a memory range affected by an incoming DMA transfer is accessed. The OS must make
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incorporates a DMA engine for each of its 9 processing elements including one Power processor element (PPE) and eight synergistic processor elements (SPEs). Since the SPE's load/store instructions can read/write only its own local memory, an SPE entirely depends on DMAs to transfer data to and from
210:
that can be written and read by the CPU. These include a memory address register, a byte count register, and one or more control registers. Depending on what features the DMA controller provides, these control registers might specify some combination of the source, the destination, the direction of
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Each DMA channel has a 16-bit address register and a 16-bit count register associated with it. To initiate a data transfer the device driver sets up the DMA channel's address and count registers together with the direction of the data transfer, read or write. It then instructs the DMA hardware to
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problems. Imagine a CPU equipped with a cache and an external memory that can be accessed directly by devices using DMA. When the CPU accesses location X in the memory, the current value will be stored in the cache. Subsequent operations on X will update the cached copy of X, but not the external
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issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to
218:
to transfer, and the memory address to use. The CPU then commands the peripheral device to initiate a data transfer. The DMA controller then provides addresses and read/write control lines to the system memory. Each time a byte of data is ready to be transferred between the peripheral device and
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transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised
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the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory
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from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including
114:, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an
549:
of computer systems with DMA functionality, represent electronic signaling lines between the CPU and DMA controller. Each DMA channel has one
Request and one Acknowledge line. A device that uses DMA must be configured to use both lines of the assigned DMA channel.
318:
transparent mode is that the CPU never stops executing its programs and the DMA transfer is free in terms of time, while the disadvantage is that the hardware needs to determine when the CPU is not using the system buses, which can be complex. This is also called "
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if several devices request bus ownership simultaneously, since there can only be one bus master at one time. When the component is granted ownership, it will issue normal read and write commands on the PCI bus, which will be claimed by the PCI bus controller.
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Therefore, high bandwidth devices such as network controllers that need to transfer huge amounts of data to/from system memory will have two interface adapters to the AHB: a master and a slave interface. This is because on-chip buses like AHB do not support
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is used in systems in which the CPU should not be disabled for the length of time needed for burst transfer modes. In the cycle stealing mode, the DMA controller obtains access to the system bus the same way as in burst mode, using
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sure that the memory range is not accessed by any running threads in the meantime. The latter approach introduces some overhead to the DMA operation, as most hardware requires a loop to invalidate each cache line individually.
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or multibuffering. For example, the on-chip memory is split into two buffers; the processor may be operating on data in one, while the DMA engine is loading and storing data in the other. This allows the system to avoid
758:) can write/read I/O registers or (less commonly) local memory blocks inside the device. A master interface can be used by the device to perform DMA transactions to/from system memory without heavily loading the CPU.
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parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main
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DMA allows the transfer of data to and from multiple memory areas in a single DMA transaction. It is equivalent to the chaining together of multiple simple DMA requests. The motivation is to off-load multiple
621:") and request to read from and write to system memory. More precisely, a PCI component requests bus ownership from the PCI bus controller (usually PCI host bridge, and PCI to PCI bridge), which will
664:(DAC) mechanism, if implemented on both the PCI bus and the device itself, enables 64-bit DMA addressing. Otherwise, the operating system would need to work around the problem by either using costly
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inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel.
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DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's
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developer Andrew Grover performed benchmarks using I/OAT to offload network traffic copies and found no more than 10% improvement in CPU utilization with receiving workloads.
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processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the
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1464:
754:. AMBA defines two kinds of AHB components: master and slave. A slave interface is similar to programmed I/O through which the software (running on embedded CPU, e.g.
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the transfer (reading from the I/O device or writing to the I/O device), the size of the transfer unit, and/or the number of bytes to transfer in one burst.
751:
146:
DMA can also be used for "memory to memory" copying or moving of data within memory. DMA can offload expensive memory operations, such as large copies or
660:(PAE), a 36-bit addressing mode. In such a case, a device using DMA with a 32-bit address bus is unable to address memory above the 4 GB line. The new
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Similarly, if the cached copy of X is not invalidated when a device writes a new value to the memory, then the CPU will operate on a stale value of X.
139:. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels. Similarly, a
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the bus or alternating the direction of any line on the bus. Like PCI, no central DMA controller is required since the DMA is bus-mastering, but an
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To carry out an input, output or memory-to-memory operation, the host processor initializes the DMA controller with a count of the number of
1440:
1297:"Achieving Lowest Latencies at Highest Message Rates with Intel Xeon Processor E5-2600 and Solarflare SFN6122F 10 GbE Server Adapter"
2321:
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
346:. If the cache is not flushed to the memory before the next time a device tries to access X, the device will receive a stale value of X.
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the main memory and local memories of other SPEs. Thus the DMA acts as a primary means of data transfer among cores inside this
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This issue can be addressed in one of two ways in system design: Cache-coherent systems implement a method in hardware, called
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Hybrids also exist, where the secondary L2 cache is coherent while the L1 cache (typically on-CPU) is managed by software.
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architecture has no central DMA controller, unlike ISA. Instead, A PCI device can request control of the bus ("become the
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below the middle of the image are the DMA controller (l.) and - unusual - an extra dedicated DMA controller (r.) for the
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running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB
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memory, the DMA controller increments its internal address register until the full block of data is transferred.
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instead of system RAM. As a result, CPU caches are used as the primary source and destination for I/O, allowing
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413:", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.
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measures must be provided to put the processor into a hold condition so that bus contention does not occur.
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696:(I/OAT), which can offload memory copying from the main CPU, freeing it to do other work. In 2006, Intel's
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Internally, a multichannel DMA engine is usually present in the device to perform multiple concurrent
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819:(note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the
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44:
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2196:
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104:
99:) is a feature of computer systems that allows certain hardware subsystems to access main system
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Standard DMA, also called third-party DMA, uses a DMA controller. A DMA controller can generate
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61:
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A modern x86 CPU may use more than 4 GB of memory, either utilizing the native 64-bit mode of
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Further performance-oriented enhancements to the DMA mechanism have been introduced in Intel
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processor) may benefit from software overlapping DMA memory operations with processing, via
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could still easily outstrip the 8237), as well as the development of further evolutions to (
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1999:
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8:
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modes), Parallel Port (ECP capable port), certain SoundBlaster Clones like the OPTi 928
357:
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140:
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934:
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356:, whereby external writes are signaled to the cache controller which then performs a
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operations, from the CPU to a dedicated DMA engine. An implementation example is the
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743:
343:
1911:
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1012:"DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7"
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100:
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regardless of the system's actual address space or amount of installed memory.
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397:/8088-standard) megabyte of RAM, and were limited to addressing single 64
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As an example of DMA engine incorporated in a general-purpose CPU, some Intel
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2011:
1994:
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1518:, from A. F. Harvey and Data Acquisition Division Staff NATIONAL INSTRUMENTS
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1964:
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804:(in contrast to cache-coherent CMP architectures such as Intel's cancelled
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1969:
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prevented use of large (and fast, but uninterruptible) block transfers.
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infrared controller when FIR (fast infrared) mode is selected, and an
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1928:
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820:
750:, typical system bus infrastructure is a complex on-chip bus such as
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964: – Electronic communication subsystem on an integrated circuit
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cards that needed to maintain full hardware compatibility with the
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only), user hardware for all others, usually sound card 16-bit DMA
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1198:
1148:"Bus Specifics - Writing Device Drivers for Oracle® Solaris 11.3"
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709:
673:
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410:
1244:"Intel Data Direct I/O (Intel DDIO): Frequently Asked Questions"
633:-based PC, the southbridge will forward the transactions to the
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1568:, Embedded Linux Conference 2014, San Jose, by Laurent Pinchart
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is required in case of multiple masters present on the system.
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begin the transfer. When the transfer is complete, the device
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and initiate memory read or write cycles. It contains several
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2006:
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1355:"Cell Multiprocessor Communication Network: Built for Speed"
1219:
Overview of I/OAT on Linux, with links to several benchmarks
919: – An integrated circuit for rapid data synchronization
443:
2232:
2217:
2078:
1989:
1984:
1826:
1071:. McGraw-Hill International Book Company. p. 426-427.
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to provide address translation services if one is present.
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561:
502:
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1172:"Physical Address Extension — PAE Memory and Windows"
409:. This prevented it from being used as a general-purpose "
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1806:
1801:
931: – Cyberattack exploiting high-speed expansion ports
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511:
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devices on motherboards that often integrated a built-in
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of which channel 0 in the PC (& XT) was dedicated to
227:
135:. DMA is also used for intra-chip data transfer in some
939:
Pages displaying short descriptions of redirect targets
906:
Pages displaying short descriptions of redirect targets
720:) feature, allowing the DMA "windows" to reside within
1174:. Microsoft Windows Hardware Development Central. 2005
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CPU/bus architecture), could only address the first (
990:
Pages displaying wikidata descriptions as a fallback
854:μPD71071, capable of addressing a 16M-byte of memory
851:μPD71037, capable of addressing a 64K-byte of memory
925: – High-performance input/output architecture
1006:
1004:
222:Some examples of buses using third-party DMA are
2340:
1465:"pPD71037 Direct Memory Access (DMA) Controller"
982: – Data transfer method for ATA Hard drives
913: – MCU hardware feature for task offloading
461:meant that PIO transfers even by the 16-bit-bus
1924:Coherent Accelerator Processor Interface (CAPI)
1323:
976: – Low-level hardware direct memory access
442:monopolise the bus approximately every 15
1042:(2nd ed.). Osborne McGraw Hill. pp.
1001:
958: – Computer memory management methodology
1587:
1346:
1206:
534:interrupt and data copy tasks from the CPU.
1270:
1119:
1016:Universidad Nacional de la Plata, Argentina
904: – Computer storage interface standard
567:User hardware, usually sound card 8-bit DMA
449:Due to their lagging performance (1.6
198:in the first series of this computer model.
1594:
1580:
1418:"Z80® DMA Direct Memory Access Controller"
888:, at the expense of needing a predictable
777:operations as programmed by the software.
1326:"Pushing the Limits of Kernel Networking"
1273:"Pushing the Limits of Kernel Networking"
1085:
970: – Process of device status sampling
738:Advanced Microcontroller Bus Architecture
668:(DOS/Windows nomenclature) also known as
80:Learn how and when to remove this message
1516:DMA Fundamentals on Various PC Platforms
1129:PC Architecture for Technicians: Level 1
1029:
174:
43:This article includes a list of general
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1035:
14:
2341:
1541:, Jonathan Corbet, Alessandro Rubini,
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1069:Computer Architecture and Organization
279:
1575:
1192:Corbet, Jonathan (December 8, 2005).
1066:
988: – Microsoft DMA access standard
946: – Specialized computer hardware
692:chipsets include a DMA engine called
262:
1441:"Sharp 1986 Semiconductor Data Book"
816:
553:16-bit ISA permitted bus mastering.
29:
1093:"Intel 8237 & 8237-2 Datasheet"
937: – Method of CPU communication
424:(more familiarly retronymed as the
312:
110:Without DMA, when the CPU is using
24:
1395:"Am9517A Multimode DMA Controller"
952: – Processing data technology
826:
545:. These symbols, seen on hardware
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49:it lacks sufficient corresponding
25:
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1559:
1539:Linux Device Drivers, 3rd Edition
1526:Linux Device Drivers, 2nd Edition
2325:
2324:
1566:Mastering the DMA and IOMMU APIs
791:As an example usage of DMA in a
342:memory version of X, assuming a
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34:
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911:Autonomous peripheral operation
590:Cascade to PC/XT DMA controller
186:computer (1990). The two large
1324:Alexander Duyck (2015-08-19).
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1113:
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556:Standard ISA DMA assignments:
426:Industry Standard Architecture
170:
13:
1:
1919:Intel Ultra Path Interconnect
1553:DMA Modes & Bus Mastering
1353:Kistler, Michael (May 2006).
1213:Grover, Andrew (2006-06-01).
995:
858:
848:LH0083, compatible to Z80 DMA
793:multiprocessor-system-on-chip
726:network interface controllers
320:Hidden DMA data transfer mode
267:
165:
1897:Intel QuickPath Interconnect
1887:Direct Media Interface (DMI)
676:/Linux), or it could use an
7:
1194:"Memory copies in hardware"
974:Remote direct memory access
895:
694:I/O Acceleration Technology
367:
152:I/O Acceleration Technology
27:Feature of computer systems
10:
2385:
1882:Compute Express Link (CXL)
1548:DMA and Interrupt Handling
1528:, Alessandro Rubini &
1508:
1271:Rashid Khan (2015-09-29).
1120:Intel Corp. (2003-04-25),
968:Polling (computer science)
784:
735:
658:Physical Address Extension
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2277:
2256:
2205:
2119:IEEE-1284 (parallel port)
2041:
2034:logical device interface)
1937:
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1623:
1489:"µPD71071 DMA Controller"
869:digital signal processors
752:AMBA High-performance Bus
647:list of device bandwidths
1215:"I/OAT on LinuxNet wiki"
683:
154:. DMA is of interest in
780:
703:
583:modes, and replaced by
559:
473:) or replacements for (
112:programmed input/output
105:central processing unit
64:more precise citations.
2359:Computer storage buses
1681:List of bus bandwidths
1535:Memory Mapping and DMA
1067:Hayes, John.P (1978).
1036:Osborne, Adam (1980).
731:
712:processors with their
641:on the CPU die) using
608:
491:Sound Blaster standard
385:), there was only one
372:
199:
2364:Hardware acceleration
1122:"Chapter 12: ISA Bus"
944:Hardware acceleration
890:memory access pattern
815:DMA in Cell is fully
795:, IBM/Sony/Toshiba's
787:Cell (microprocessor)
629:As an example, on an
178:
137:multi-core processors
103:independently of the
2124:IEEE-1394 (FireWire)
1862:PCI Extended (PCI-X)
986:Virtual DMA Services
950:In-memory processing
662:Double Address Cycle
192:magneto-optical disc
141:processing circuitry
93:Direct memory access
1965:Parallel ATA (PATA)
1333:linuxfoundation.org
1100:JKbox RC702 subsite
806:general-purpose GPU
381:(and the follow-up
280:Cycle stealing mode
188:integrated circuits
160:in-memory computing
1872:PCI Express (PCIe)
1543:Greg Kroah-Hartman
1494:. p. 940(5g1)
1470:. p. 832(5b1)
1373:10.1109/MM.2006.49
564:Refresh (obsolete)
525:Scatter-gather or
358:cache invalidation
263:Modes of operation
208:hardware registers
200:
194:used instead of a
2336:
2335:
2322:
2049:Apple Desktop Bus
2026:PCI Express (via
1985:Serial ATA (SATA)
1671:Network on a chip
1446:. p. 255-269
1044:5–64 through 5–93
962:Network on a chip
956:Memory management
935:Memory-mapped I/O
867:and DMA (such as
865:scratchpad memory
744:systems-on-a-chip
635:memory controller
238:; however, their
90:
89:
82:
16:(Redirected from
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1782:HP Precision Bus
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1284:
1283:
1268:
1262:
1261:
1259:
1258:
1248:
1240:
1234:
1233:
1231:
1230:
1221:. Archived from
1210:
1204:
1203:
1189:
1183:
1182:
1180:
1179:
1168:
1162:
1161:
1159:
1158:
1144:
1138:
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1135:
1126:
1117:
1111:
1110:
1108:
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1097:
1089:
1083:
1082:
1064:
1058:
1057:
1033:
1027:
1026:
1024:
1022:
1008:
991:
940:
907:
877:double buffering
863:Processors with
748:embedded systems
543:Data acknowledge
439:segment boundary
377:In the original
344:write-back cache
337:DMA can lead to
334:
313:Transparent mode
240:host controllers
204:memory addresses
85:
78:
74:
71:
65:
60:this article by
51:inline citations
38:
37:
30:
21:
2384:
2383:
2379:
2378:
2377:
2375:
2374:
2373:
2349:Computer memory
2339:
2338:
2337:
2332:
2323:
2314:
2273:
2252:
2201:
2114:IEEE-488 (GPIB)
2037:
1933:
1912:Infinity Fabric
1742:Europe Card Bus
1685:
1619:
1600:
1562:
1557:
1530:Jonathan Corbet
1511:
1506:
1497:
1495:
1491:
1487:
1486:
1482:
1473:
1471:
1467:
1463:
1462:
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1425:
1423:
1420:
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1397:
1393:
1392:
1388:
1351:
1347:
1338:
1336:
1328:
1322:
1318:
1309:
1307:
1299:
1295:
1294:
1290:
1281:
1279:
1269:
1265:
1256:
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1246:
1242:
1241:
1237:
1228:
1226:
1211:
1207:
1190:
1186:
1177:
1175:
1170:
1169:
1165:
1156:
1154:
1152:docs.oracle.com
1146:
1145:
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1124:
1118:
1114:
1104:
1102:
1095:
1091:
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1086:
1079:
1065:
1061:
1054:
1034:
1030:
1020:
1018:
1010:
1009:
1002:
998:
989:
938:
905:
898:
886:burst transfers
861:
829:
827:DMA Controllers
789:
783:
740:
734:
714:Data Direct I/O
706:
686:
611:
606:
537:DRQ stands for
501:controller, an
420:, the enhanced
375:
370:
339:cache coherency
328:
326:Cache coherency
315:
282:
270:
265:
252:
196:hard disk drive
173:
168:
162:architectures.
156:network-on-chip
86:
75:
69:
66:
56:Please help to
55:
39:
35:
28:
23:
22:
15:
12:
11:
5:
2382:
2372:
2371:
2366:
2361:
2356:
2351:
2334:
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2313:
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2307:
2302:
2292:
2287:
2281:
2279:
2275:
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2271:
2266:
2260:
2258:
2254:
2253:
2251:
2250:
2245:
2240:
2235:
2230:
2225:
2223:Intel HD Audio
2220:
2215:
2213:ADAT Lightpipe
2209:
2207:
2203:
2202:
2200:
2199:
2194:
2189:
2184:
2179:
2174:
2169:
2164:
2159:
2154:
2136:
2131:
2126:
2121:
2116:
2111:
2106:
2101:
2096:
2091:
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2081:
2076:
2071:
2066:
2061:
2056:
2051:
2045:
2043:
2039:
2038:
2036:
2035:
2024:
2019:
2014:
2009:
2004:
2003:
2002:
1997:
1987:
1982:
1977:
1972:
1967:
1962:
1957:
1952:
1947:
1941:
1939:
1935:
1934:
1932:
1931:
1926:
1921:
1916:
1915:
1914:
1907:HyperTransport
1904:
1899:
1894:
1889:
1884:
1879:
1874:
1869:
1864:
1859:
1854:
1849:
1844:
1839:
1834:
1829:
1824:
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1814:
1809:
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1799:
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1759:
1754:
1749:
1744:
1739:
1734:
1729:
1724:
1719:
1714:
1709:
1704:
1699:
1693:
1691:
1687:
1686:
1684:
1683:
1678:
1673:
1668:
1663:
1661:Bus contention
1658:
1653:
1648:
1643:
1638:
1636:Front-side bus
1633:
1627:
1625:
1621:
1620:
1617:computer buses
1599:
1598:
1591:
1584:
1576:
1570:
1569:
1561:
1560:External links
1558:
1556:
1555:
1550:
1545:
1532:
1522:mmap() and DMA
1519:
1512:
1510:
1507:
1505:
1504:
1480:
1456:
1432:
1409:
1386:
1345:
1316:
1304:solarflare.com
1288:
1263:
1235:
1205:
1184:
1163:
1139:
1112:
1084:
1077:
1059:
1052:
1028:
999:
997:
994:
993:
992:
983:
977:
971:
965:
959:
953:
947:
941:
932:
926:
920:
914:
908:
897:
894:
882:memory latency
860:
857:
856:
855:
852:
849:
846:
843:
838:
835:
828:
825:
821:standard sense
817:cache coherent
797:Cell processor
785:Main article:
782:
779:
775:scatter-gather
736:Main article:
733:
730:
705:
702:
685:
682:
670:bounce buffers
666:double buffers
610:
607:
605:
604:
601:
598:
591:
588:
579:(obsoleted by
574:
568:
565:
558:
404:dynamic memory
374:
371:
369:
366:
327:
324:
314:
311:
287:cycle stealing
281:
278:
269:
266:
264:
261:
251:
248:
172:
169:
167:
164:
148:scatter-gather
125:graphics cards
88:
87:
42:
40:
33:
26:
18:DMA controller
9:
6:
4:
3:
2:
2381:
2370:
2367:
2365:
2362:
2360:
2357:
2355:
2352:
2350:
2347:
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2344:
2331:
2317:
2311:
2308:
2306:
2303:
2300:
2296:
2293:
2291:
2288:
2286:
2285:Multidrop bus
2283:
2282:
2280:
2276:
2270:
2267:
2265:
2262:
2261:
2259:
2255:
2249:
2246:
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2241:
2239:
2236:
2234:
2231:
2229:
2226:
2224:
2221:
2219:
2216:
2214:
2211:
2210:
2208:
2204:
2198:
2195:
2193:
2192:External PCIe
2190:
2188:
2185:
2183:
2180:
2178:
2175:
2173:
2172:Parallel SCSI
2170:
2168:
2165:
2163:
2160:
2158:
2155:
2152:
2148:
2144:
2140:
2137:
2135:
2132:
2130:
2127:
2125:
2122:
2120:
2117:
2115:
2112:
2110:
2107:
2105:
2102:
2100:
2097:
2095:
2092:
2090:
2087:
2085:
2082:
2080:
2077:
2075:
2072:
2070:
2067:
2065:
2064:Commodore bus
2062:
2060:
2057:
2055:
2052:
2050:
2047:
2046:
2044:
2040:
2033:
2029:
2025:
2023:
2020:
2018:
2015:
2013:
2012:Fibre Channel
2010:
2008:
2005:
2001:
1998:
1996:
1993:
1992:
1991:
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1983:
1981:
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1718:
1715:
1713:
1710:
1708:
1705:
1703:
1700:
1698:
1695:
1694:
1692:
1688:
1682:
1679:
1677:
1676:Plug and play
1674:
1672:
1669:
1667:
1666:Bus mastering
1664:
1662:
1659:
1657:
1654:
1652:
1649:
1647:
1644:
1642:
1641:Back-side bus
1639:
1637:
1634:
1632:
1629:
1628:
1626:
1622:
1618:
1615:
1611:
1609:
1604:
1597:
1592:
1590:
1585:
1583:
1578:
1577:
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1567:
1564:
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1554:
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1544:
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1523:
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1514:
1513:
1490:
1484:
1466:
1460:
1442:
1436:
1419:
1413:
1396:
1390:
1382:
1378:
1374:
1370:
1366:
1362:
1361:
1356:
1349:
1334:
1327:
1320:
1305:
1298:
1292:
1278:
1274:
1267:
1252:
1245:
1239:
1225:on 2016-05-05
1224:
1220:
1216:
1209:
1201:
1200:
1195:
1188:
1173:
1167:
1153:
1149:
1143:
1130:
1123:
1116:
1101:
1094:
1088:
1080:
1078:0-07-027363-4
1074:
1070:
1063:
1055:
1049:
1045:
1041:
1040:
1032:
1017:
1013:
1007:
1005:
1000:
987:
984:
981:
978:
975:
972:
969:
966:
963:
960:
957:
954:
951:
948:
945:
942:
936:
933:
930:
927:
924:
921:
918:
915:
912:
909:
903:
902:AT Attachment
900:
899:
893:
891:
887:
883:
878:
874:
870:
866:
853:
850:
847:
844:
842:
839:
836:
834:
831:
830:
824:
822:
818:
813:
811:
807:
803:
798:
794:
788:
778:
776:
771:
769:
765:
759:
757:
753:
749:
745:
739:
729:
727:
723:
719:
715:
711:
701:
699:
695:
691:
681:
679:
675:
671:
667:
663:
659:
655:
650:
648:
644:
640:
636:
632:
627:
624:
620:
616:
603:User hardware
602:
600:User hardware
599:
596:
592:
589:
586:
582:
578:
575:
572:
569:
566:
563:
560:
557:
554:
551:
548:
544:
540:
535:
533:
528:
523:
521:
515:
513:
508:
504:
500:
496:
492:
488:
487:Sound Blaster
484:
480:
476:
472:
468:
464:
460:
456:
452:
447:
445:
440:
436:
431:
427:
423:
419:
414:
412:
408:
405:
400:
396:
392:
388:
384:
380:
365:
362:
359:
355:
350:
347:
345:
340:
335:
333:
323:
321:
310:
307:
305:
299:
297:
290:
288:
277:
275:
260:
257:
256:bus mastering
250:Bus mastering
247:
245:
244:bus mastering
241:
237:
233:
229:
225:
220:
217:
212:
209:
205:
197:
193:
189:
185:
181:
177:
163:
161:
157:
153:
149:
144:
142:
138:
134:
130:
129:network cards
126:
123:controllers,
122:
117:
113:
108:
106:
102:
98:
94:
84:
81:
73:
63:
59:
53:
52:
46:
41:
32:
31:
19:
2369:Input/output
1817:TURBOchannel
1607:
1538:
1525:
1496:. Retrieved
1483:
1472:. Retrieved
1459:
1448:. Retrieved
1435:
1424:. Retrieved
1412:
1401:. Retrieved
1389:
1367:(3): 10–23.
1364:
1358:
1348:
1337:. Retrieved
1332:
1319:
1308:. Retrieved
1306:. 2012-06-07
1303:
1291:
1280:. Retrieved
1276:
1266:
1255:. Retrieved
1253:. March 2012
1238:
1227:. Retrieved
1223:the original
1218:
1208:
1197:
1187:
1176:. Retrieved
1166:
1155:. Retrieved
1151:
1142:
1132:, retrieved
1128:
1115:
1103:. Retrieved
1099:
1087:
1068:
1062:
1038:
1031:
1019:. Retrieved
1015:
884:and exploit
862:
814:
790:
772:
760:
741:
717:
713:
710:Xeon E5
707:
698:Linux kernel
687:
656:CPU, or the
651:
628:
612:
555:
552:
542:
539:Data request
538:
536:
532:input/output
527:vectored I/O
524:
516:
448:
429:
415:
376:
363:
354:bus snooping
351:
348:
336:
329:
319:
316:
301:
293:
285:
283:
273:
271:
253:
221:
213:
201:
145:
109:
96:
92:
91:
76:
67:
48:
2354:Motherboard
2290:CoreConnect
2269:ExpressCard
2197:Thunderbolt
2187:Camera Link
1970:Bus and Tag
1656:Address bus
1651:Control bus
1646:Daisy chain
1335:. p. 5
923:Channel I/O
764:tri-stating
593:Hard Disk (
571:Floppy disk
541:; DACK for
499:floppy disk
430:controlling
296:Bus Request
180:Motherboard
171:Third-party
133:sound cards
62:introducing
2343:Categories
2143:ACCESS.bus
2042:Peripheral
1842:InfiniBand
1837:HP GSC bus
1631:System bus
1498:2024-01-05
1474:2024-01-06
1450:2024-01-13
1426:2024-01-07
1403:2024-01-06
1360:IEEE Micro
1339:2015-10-11
1310:2015-10-11
1282:2015-10-11
1277:redhat.com
1257:2015-10-11
1229:2006-12-12
1178:2008-04-07
1157:2020-12-18
1134:2015-01-27
1053:0931988349
996:References
929:DMA attack
859:Pipelining
841:Intel 8237
833:Intel 8257
722:CPU caches
639:integrated
637:(which is
631:Intel Core
619:bus master
573:controller
547:schematics
520:interrupts
387:Intel 8237
274:burst mode
268:Burst mode
166:Principles
121:disk drive
45:references
2104:Lightning
2054:Atari SIO
1929:SpaceWire
1762:Zorro III
1702:S-100 bus
1697:SS-50 bus
1690:Standards
1610:standards
1603:Technical
623:arbitrate
577:Hard disk
522:the CPU.
507:IEEE 1284
495:Super I/O
418:IBM PC/AT
416:With the
304:Bus Grant
116:interrupt
2330:Category
2305:Wishbone
2278:Embedded
2257:Portable
2177:Profibus
2109:DMX512-A
1995:Parallel
1847:Ethernet
1757:Zorro II
1707:Multibus
1608:de facto
1105:20 April
1021:20 April
896:See also
871:and the
810:Larrabee
368:Examples
230:(before
184:NeXTcube
70:May 2023
2310:SLIMbus
2264:PC Card
2248:TOSLINK
1938:Storage
1892:RapidIO
1772:FASTBUS
1727:STD Bus
1624:General
1537:, from
1524:, from
1509:Sources
1381:7735690
1199:LWN.net
917:Blitter
845:Z80 DMA
768:arbiter
674:FreeBSD
411:Blitter
407:refresh
234:), and
107:(CPU).
58:improve
2243:S/PDIF
2134:1-Wire
2099:RS-485
2094:RS-423
2089:RS-422
2084:RS-232
1945:ST-506
1902:NVLink
1752:STEbus
1712:Unibus
1379:
1075:
1050:
837:Am9517
654:x86-64
493:; and
422:AT bus
379:IBM PC
101:memory
47:, but
2238:McASP
2206:Audio
2151:SMBus
2147:PMBus
2129:UNI/O
2069:HP-IL
2022:SATAe
2007:ESCON
1980:HIPPI
1812:NuBus
1767:CAMAC
1737:Q-Bus
1732:SMBus
1717:VAXBI
1614:wired
1492:(PDF)
1468:(PDF)
1444:(PDF)
1421:(PDF)
1398:(PDF)
1377:S2CID
1329:(PDF)
1300:(PDF)
1251:Intel
1247:(PDF)
1125:(PDF)
1096:(PDF)
684:I/OAT
678:IOMMU
467:386SX
459:80186
455:80386
435:80286
395:i8086
391:i8088
383:PC/XT
254:In a
216:words
182:of a
2295:AMBA
2233:MADI
2218:AES3
2079:MIDI
2032:NVMe
2028:AHCI
1990:SCSI
1975:DSSI
1950:ESDI
1827:SBus
1787:EISA
1722:MBus
1612:for
1605:and
1107:2019
1073:ISBN
1048:ISBN
1023:2019
980:UDMA
873:Cell
781:Cell
746:and
718:DDIO
704:DDIO
690:Xeon
595:PS/2
585:UDMA
562:DRAM
503:IrDA
481:and
471:EISA
465:and
302:BG (
300:and
294:BR (
289:mode
284:The
242:use
236:SATA
232:USB4
224:PATA
158:and
131:and
2299:AXI
2228:I²S
2182:USB
2167:D²B
2162:SPI
2157:I3C
2139:I²C
2074:HIL
2059:DCB
2030:or
2017:SSA
2000:SAS
1960:SMD
1955:IPI
1877:AGP
1867:PXI
1857:PCI
1852:UPA
1832:VLB
1822:MCA
1807:VPX
1802:VXS
1797:VXI
1792:VME
1777:LPC
1747:ISA
1369:doi
812:).
802:CPU
756:ARM
742:In
732:AHB
649:).
643:DMI
615:PCI
609:PCI
581:PIO
512:RAM
483:PCI
479:VLB
475:MCA
463:286
373:ISA
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