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665:, later headed Cray Research. Cray developed the XMP line of supercomputers, using pipelining for both multiply and add/subtract functions. Later, Star Technologies added parallelism (several pipelined functions working in parallel), developed by Roger Chen. In 1984, Star Technologies added the pipelined divide circuit developed by James Bradley. By the mid-1980s, pipelining was used by many different companies around the world.
1199:, dealt with hazards by simply warning the programmer; in this case, that one or more instructions following the branch would be executed whether or not the branch was taken. This could be useful; for instance, after computing a number in a register, a conditional branch could be followed by loading into the register a value more useful to subsequent computations in both the branch and the non-branch case.
758:), or declares that the second instruction uses an old value rather than the desired value (in the example above, the processor might counter-intuitively copy the unincremented value), or declares that the value it uses is undefined. The programmer may have unrelated work that the processor can do in the meantime; or, to ensure correct results, the programmer may insert
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In the illustration at right, in cycle 3, the processor cannot decode the purple instruction, perhaps because the processor determines that decoding depends on results produced by the execution of the green instruction. The green instruction can proceed to the
Execute stage and then to the Write-back
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When operating efficiently, a pipelined computer will have an instruction in each stage. It is then working on all of those instructions at the same time. It can finish about one instruction for each cycle of its clock. But when a program switches to a different sequence of instructions, the pipeline
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In a pipelined computer, the control unit arranges for the flow to start, continue, and stop as a program commands. The instruction data is usually passed in pipeline registers from one stage to the next, with a somewhat separated piece of control logic for each stage. The control unit also assures
907:
Pipelining keeps all portions of the processor occupied and increases the amount of useful work the processor can do in a given time. Pipelining typically reduces the processor's cycle time and increases the throughput of instructions. The speed advantage is diminished to the extent that execution
805:
A branch out of the normal instruction sequence often involves a hazard. Unless the processor can give effect to the branch in a single time cycle, the pipeline will continue fetching instructions sequentially. Such instructions cannot be allowed to take effect because the programmer has diverted
359:
A pipelined model of computer is often the most economical, when cost is measured as logic gates per instruction per second. At each instant, an instruction is in only one pipeline stage, and on average, a pipeline stage is less costly than a multicycle computer. Also, when made well, most of the
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However, a pipelined computer is usually more complex and more costly than a comparable multicycle computer. It typically has more logic gates, registers and a more complex control unit. In a like way, it might use more total energy, while using less energy per instruction. Out of order CPUs can
351:
due to the added overhead of the pipelining process itself. Also, even though the electronic logic has a fixed maximum speed, a pipelined computer can be made faster or slower by varying the number of stages in the pipeline. With more stages, each stage does less work, and so the stage has fewer
944:
To the right is a generic pipeline with four stages: fetch, decode, execute and write-back. The top gray box is the list of instructions waiting to be executed, the bottom gray box is the list of instructions that have had their execution completed, and the middle white box is the pipeline.
454:
The
Xelerated X10q Network Processor has a pipeline more than a thousand stages long, although in this case 200 of these stages represent independent CPUs with individually programmed instructions. The remaining stages are used to coordinate accesses to memory and on-chip function
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Compared to environments where the programmer needs to avoid or work around hazards, use of a non-pipelined processor may make it easier to program and to train programmers. The non-pipelined processor also makes it easier to predict the exact timing of a given sequence of
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By making each dependent step simpler, pipelining can enable complex operations more economically than adding complex circuitry, such as for numerical calculations. However, a processor that declines to pursue increased speed with pipelining may be simpler and cheaper to
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Programs written for a pipelined processor deliberately avoid branching to minimize possible loss of speed. For example, the programmer can handle the usual case with sequential execution and branch only on detecting unusual cases. Using programs such as
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pipelined computer's logic is in use most of the time. In contrast, out of order computers usually have large amounts of idle logic at any given instant. Similar calculations usually show that a pipelined computer uses less energy per instruction.
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A processor with an implementation of branch prediction that usually makes correct predictions can minimize the performance penalty from branching. However, if branches are predicted poorly, it may create more work for the processor, such as
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When the bubble moves out of the pipeline (at cycle 6), normal execution resumes. But everything now is one cycle late. It will take 8 cycles (cycle 1 through 8) rather than 7 to completely execute the four instructions shown in colors.
335:
This arrangement lets the CPU complete an instruction on each clock cycle. It is common for even-numbered stages to operate on one edge of the square-wave clock, while odd-numbered stages operate on the other edge. This allows more
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that the instruction in each stage does not harm the operation of instructions in other stages. For example, if two stages must use the same piece of data, the control logic assures that the uses are done in the correct sequence.
328:: Fetch the instruction, fetch the operands, do the instruction, write the results. A pipelined computer usually has "pipeline registers" after each stage. These store information from the instruction and calculations so that the
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The model of sequential execution assumes that each instruction completes before the next one begins; this assumption is not true on a pipelined processor. A situation where the expected result is problematic is known as a
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stage as scheduled, but the purple instruction is stalled for one cycle at the Fetch stage. The blue instruction, which was due to be fetched during cycle 3, is stalled for one cycle, as is the red instruction after it.
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Because of the bubble (the blue ovals in the illustration), the processor's Decode circuitry is idle during cycle 3. Its
Execute circuitry is idle during cycle 4 and its Write-back circuitry is idle during cycle 5.
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that require execution to slow below its ideal rate. A non-pipelined processor executes only a single instruction at a time. The start of the next instruction is delayed not based on hazards but unconditionally.
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lets the programmer measure how often particular branches are actually executed and gain insight with which to optimize the code. In some cases, a programmer can handle both the usual case and unusual case with
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As the pipeline is made "deeper" (with a greater number of dependent steps), a given step can be implemented with simpler circuitry, which may let the processor clock run faster. Such pipelines may be called
785:
An additional data path can be added that routes a computed value to a future instruction elsewhere in the pipeline before the instruction that produced it has been fully retired, a process called
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Note, however, that, even with the bubble, the processor is still able - at least in this case - to run through the sequence of instructions much faster than a non-pipelined processor could.
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between instructions, but a pipelining processor overlaps instructions, so executing an uninterruptible instruction renders portions of ordinary instructions uninterruptible too. The
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if it can fetch an instruction on every cycle. Thus, if some instructions or conditions require delays that inhibit fetching new instructions, the processor is not fully pipelined.
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A conditional branch is even more problematic. The processor may or may not branch, depending on a calculation that has not yet occurred. Various processors may stall, may attempt
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can configure their on-chip cache memories for data-only fetches, or as part of their ordinary memory address space, and avoid such difficulties with self-modifying instructions.
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If the processor has the 5 steps listed in the initial illustration (the 'Basic five-stage pipeline' at the start of the article), instruction 1 would be fetched at time
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The processor can locate other instructions which are not dependent on the current ones and which can be immediately executed without hazards, an optimization known as
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A pipelined processor's need to organize all its work into modular steps may require the duplication of registers, which increases the latency of some instructions.
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can be problematic on a pipelined processor. In this technique, one of the effects of a program is to modify its own upcoming instructions. If the processor has an
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A pipelined processor may deal with hazards by stalling and creating a bubble in the pipeline, resulting in one or more cycles in which nothing useful happens.
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Pipelined processors commonly use three techniques to work as expected when the programmer assumes that each instruction completes before the next one begins:
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In some early DSP and RISC processors, the documentation advises programmers to avoid such dependencies in adjacent and nearly adjacent instructions (called
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such as vector processors and array processors. One of the early supercomputers was the Cyber series built by
Control Data Corporation. Its main architect,
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In the fourth clock cycle (the green column), the earliest instruction is in MEM stage, and the latest instruction has not yet entered the pipeline.
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within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming
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language might not raise these concerns, as the compiler could be designed to generate machine code that avoids hazards.
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739:. It seems that the first instruction would not have incremented the value by then. The above code invokes a hazard.
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279:(IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back).
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a single-core system using an infinite loop in which an uninterruptible instruction was always in the pipeline.
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2008:
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672:'s 470 series general purpose mainframe had a 7-step pipeline, and a patented branch prediction circuit.
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Much of the design of a pipelined computer prevents interference between the stages and reduces stalls.
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the incorrect code path that has begun execution before resuming execution at the correct location.
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Generic 4-stage pipeline; the colored boxes represent instructions independent of each other
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usually do more instructions per second because they can do several instructions at once.
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1230:"Xelerated's Xtraordinary NPU — World's First 40Gb/s Packet Processor Has 200 CPUs"
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sometimes must discard the data in process and restart. This is called a "stall."
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The number of dependent steps varies with the machine architecture. For example:
1260:"Xelerated Brings Programmable 40 Gbits/S Technology to the Mainstream Ethernet"
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The green instruction's results are written back to the register file or memory
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691:. Imagine the following two register instructions to a hypothetical processor:
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Many designs include pipelines as long as 7, 10 and even 20 stages (as in the
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project proposed the terms Fetch, Decode, and
Execute that have become common.
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Early pipelined processors without any of these heuristics, such as the
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and the modification will not take effect. Some processors such as the
813:, and may be able to begin to execute two different program sequences (
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610: in this section. Unsourced material may be challenged and removed.
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cores from Intel, used in the last
Pentium 4 models and their
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The green instruction is executed (actual operation is performed)
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into the code, partly negating the advantages of pipelining.
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with different parts of instructions processed in parallel.
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1970:
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Pipelining was not limited to supercomputers. In 1976, the
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1340:"Konrad Zuse's Legacy: The Architecture of the Z1 and Z3"
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project, though a simple version was used earlier in the
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1413:. hpc.serc.iisc.ernet.in. September 2000. Archived from
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In a pipelined computer, instructions flow through the
1307:
Design of
Computers and Other Complex Digital Devices
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An instruction may be uninterruptible to ensure its
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The execution of all four instructions is completed
487:. Unsourced material may be challenged and removed.
51:. Unsourced material may be challenged and removed.
304:into a series of sequential steps (the eponymous "
1390:"CMSC 411 Lecture 19, Pipelining Data Forwarding"
657:Pipelining began in earnest in the late 1970s in
16:Method of improving instruction-level parallelism
3402:
1074:The execution of purple instruction is completed
1411:"High performance computing, Notes of class 11"
1053:The execution of green instruction is completed
1092:The execution of blue instruction is completed
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1107:The execution of red instruction is completed
1002:The purple instruction is fetched from memory
987:The green instruction is fetched from memory
975:Four instructions are waiting to be executed
2478:Computer performance by orders of magnitude
1453:Counterflow Pipeline Processor Architecture
451:derivatives, have a long 31-stage pipeline.
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1480:
1466:
1303:
1227:
1328:
1273:John Paul Shen, Mikko H. Lipasti (2004).
626:Learn how and when to remove this message
547:Learn how and when to remove this message
315:
111:Learn how and when to remove this message
1137:
950:
898:
806:control to another part of the program.
332:of the next stage can do the next step.
1438:Branch Prediction in the Pentium Family
1348:IEEE Annals of the History of Computing
1266:
704:and its execution would be complete at
638:Seminal uses of pipelining were in the
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1056:The purple instruction is written back
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439:The later "Prescott" and "Cedar Mill"
356:and could run at a higher clock rate.
343:than a multicycle computer at a given
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1334:
1142:A bubble in cycle 3 delays execution.
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404:Instruction decode and register fetch
2449:Floating-point operations per second
1077:The blue instruction is written back
711:. Instruction 2 would be fetched at
608:adding citations to reliable sources
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485:adding citations to reliable sources
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49:adding citations to reliable sources
20:
1095:The red instruction is written back
13:
1228:Glaskowsky, Peter (Aug 18, 2003).
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1035:The purple instruction is executed
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14:
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1448:ArsTechnica article on pipelining
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1017:The purple instruction is decoded
3375:Semiconductor device fabrication
1059:The blue instruction is executed
999:The green instruction is decoded
782:, in which no work is performed.
694:1: add 1 to R5 2: copy R5 to R6
584:
461:
296:is a technique for implementing
25:
3350:History of general-purpose CPUs
1577:Nondeterministic Turing machine
1370:from the original on 2022-07-03
1080:The red instruction is executed
1038:The blue instruction is decoded
1020:The blue instruction is fetched
742:Writing computer programs in a
595:needs additional citations for
472:needs additional citations for
426:each have a two-stage pipeline.
36:needs additional citations for
1530:Deterministic finite automaton
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1297:
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1062:The red instruction is decoded
1041:The red instruction is fetched
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682:Hazard (computer architecture)
1:
2321:Simultaneous and heterogenous
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948:The execution is as follows:
298:instruction-level parallelism
3005:Integrated memory controller
2987:Translation lookaside buffer
2186:Memory dependence prediction
1629:Random-access stored program
1582:Probabilistic Turing machine
909:
875:Uninterruptible instructions
765:
7:
3411:Superscalar microprocessors
2461:Synaptic updates per second
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800:
10:
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2865:Heterogeneous architecture
1787:Orthogonal instruction set
1557:Alternating Turing machine
1545:Quantum cellular automaton
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823:flushing from the pipeline
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568:A processor is said to be
308:") performed by different
3355:Microprocessor chronology
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3318:Dynamic frequency scaling
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718:and would be complete at
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125:Basic five-stage pipeline
3370:Hardware security module
2713:Digital signal processor
2690:Graphics processing unit
2502:Graphics processing unit
1281:McGraw-Hill Professional
1178:
496:"Instruction pipelining"
60:"Instruction pipelining"
3323:Dynamic voltage scaling
3106:Memory address register
3000:Branch target predictor
2964:Address generation unit
2707:Physics processing unit
2496:Central processing unit
2455:Transactions per second
2443:Instructions per second
2366:Array processing (SIMT)
1510:Stored-program computer
1276:Modern Processor Design
851:Self-modifying programs
322:central processing unit
3416:Instruction processing
3129:Hardwired control unit
3011:Memory management unit
2976:Memory management unit
2725:Secure cryptoprocessor
2719:Tensor Processing Unit
2701:Vision processing unit
2435:Cycles per instruction
2429:Instructions per cycle
2376:Associative processing
2067:Instruction pipelining
1489:Processor technologies
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794:out-of-order execution
316:Concept and motivation
294:instruction pipelining
3212:Sum-addressed decoder
2958:Arithmetic logic unit
2085:Classic RISC pipeline
2039:Epiphany architecture
1886:Motorola 68000 series
1234:Microprocessor Report
1173:Classic RISC pipeline
1141:
954:
899:Design considerations
396:classic RISC pipeline
3333:Performance per watt
2911:replacement policies
2577:Package on a package
2467:Performance per watt
2371:Pipelined processing
2141:Tomasulo's algorithm
1946:Clipper architecture
1802:Application-specific
1515:Finite-state machine
864:prefetch input queue
604:improve this article
481:improve this article
290:computer engineering
45:improve this article
3365:Digital electronics
3018:Instruction decoder
2970:Floating-point unit
2624:Soft microprocessor
2571:System in a package
2146:Reservation station
1676:Transport-triggered
1338:(April–June 1997).
1304:Sunggu Lee (2000).
940:Illustrated example
856:self-modifying code
774:The pipeline could
424:PIC microcontroller
413:Register write back
347:, but may increase
127:
3237:Integrated circuit
3081:Processor register
2735:Baseband processor
2080:Operand forwarding
1540:Cellular automaton
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1134:Bubble (computing)
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846:Special situations
787:operand forwarding
670:Amdahl Corporation
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2896:Scratchpad memory
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2730:Network processor
2659:Network on a chip
2614:Ultra-low-voltage
2565:Multi-chip module
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2181:Branch prediction
2158:Register renaming
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1856:Quantum computing
1851:VISC architecture
1733:Secondary storage
1649:Microarchitecture
1609:Register machines
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854:The technique of
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1505:Abstract machine
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3401:
3400:
3399:
3394:
3380:Tick–tock model
3338:
3294:
3283:
3223:
3207:Address decoder
3161:
3115:
3111:Program counter
3086:Status register
3067:
3022:
2982:Load–store unit
2949:
2942:
2869:
2838:
2739:
2696:Image processor
2671:
2664:
2634:
2628:
2604:Microcontroller
2594:Embedded system
2582:
2482:
2415:
2404:
2342:
2292:
2190:
2167:
2151:Re-order buffer
2122:
2103:Data dependency
2089:
2048:
1878:
1872:
1771:
1770:Instruction set
1764:
1750:Multiprocessing
1718:Cache hierarchy
1711:Register/memory
1635:
1535:Queue automaton
1491:
1486:
1434:
1429:
1420:
1418:
1409:
1408:
1404:
1395:
1393:
1388:
1387:
1383:
1373:
1371:
1367:
1342:
1333:
1329:
1322:
1302:
1298:
1291:
1271:
1267:
1258:
1257:
1253:
1243:
1241:
1226:
1222:
1218:
1213:
1212:
1207:
1203:
1197:Hewlett-Packard
1190:
1186:
1181:
1164:
1136:
1130:
1128:Pipeline bubble
942:
901:
848:
815:eager execution
803:
768:
752:
737:
730:
723:
716:
709:
703:
695:
684:
678:
632:
621:
615:
612:
601:
589:
578:
570:fully pipelined
564:superpipelines.
553:
542:
536:
533:
490:
488:
478:
466:
381:
379:Number of steps
318:
310:processor units
136:
133:
117:
106:
100:
97:
54:
52:
42:
30:
17:
12:
11:
5:
3429:
3419:
3418:
3413:
3396:
3395:
3393:
3392:
3387:
3385:Pin grid array
3382:
3377:
3372:
3367:
3362:
3357:
3352:
3346:
3344:
3340:
3339:
3337:
3336:
3330:
3325:
3320:
3315:
3310:
3305:
3299:
3297:
3289:
3288:
3285:
3284:
3282:
3281:
3276:
3271:
3266:
3261:
3256:
3255:
3254:
3249:
3244:
3233:
3231:
3225:
3224:
3222:
3221:
3219:Barrel shifter
3216:
3215:
3214:
3209:
3202:Binary decoder
3199:
3198:
3197:
3187:
3182:
3177:
3171:
3169:
3163:
3162:
3160:
3159:
3154:
3146:
3141:
3136:
3131:
3125:
3123:
3117:
3116:
3114:
3113:
3108:
3103:
3098:
3093:
3091:Stack register
3088:
3083:
3077:
3075:
3069:
3068:
3066:
3065:
3064:
3063:
3058:
3048:
3043:
3038:
3032:
3030:
3024:
3023:
3021:
3020:
3015:
3014:
3013:
3002:
2997:
2992:
2991:
2990:
2984:
2973:
2967:
2961:
2954:
2952:
2941:
2940:
2935:
2930:
2925:
2920:
2919:
2918:
2913:
2908:
2903:
2898:
2893:
2883:
2877:
2875:
2871:
2870:
2868:
2867:
2862:
2857:
2852:
2846:
2844:
2840:
2839:
2837:
2836:
2835:
2834:
2824:
2819:
2814:
2809:
2804:
2799:
2794:
2789:
2784:
2779:
2774:
2769:
2764:
2759:
2753:
2751:
2745:
2744:
2741:
2740:
2738:
2737:
2732:
2727:
2722:
2716:
2710:
2704:
2698:
2693:
2687:
2685:AI accelerator
2682:
2676:
2674:
2666:
2665:
2663:
2662:
2656:
2651:
2648:Multiprocessor
2645:
2638:
2636:
2630:
2629:
2627:
2626:
2621:
2616:
2611:
2606:
2601:
2599:Microprocessor
2596:
2590:
2588:
2587:By application
2581:
2580:
2574:
2568:
2562:
2557:
2552:
2547:
2542:
2537:
2532:
2530:Tile processor
2527:
2522:
2517:
2512:
2511:
2510:
2499:
2492:
2490:
2484:
2483:
2481:
2480:
2475:
2470:
2464:
2458:
2452:
2446:
2440:
2439:
2438:
2426:
2420:
2418:
2410:
2409:
2406:
2405:
2403:
2402:
2401:
2400:
2390:
2385:
2384:
2383:
2378:
2373:
2368:
2358:
2352:
2350:
2344:
2343:
2341:
2340:
2335:
2330:
2325:
2324:
2323:
2318:
2316:Hyperthreading
2308:
2302:
2300:
2298:Multithreading
2294:
2293:
2291:
2290:
2285:
2280:
2279:
2278:
2268:
2267:
2266:
2261:
2251:
2250:
2249:
2244:
2234:
2229:
2228:
2227:
2222:
2211:
2209:
2202:
2196:
2195:
2192:
2191:
2189:
2188:
2183:
2177:
2175:
2169:
2168:
2166:
2165:
2160:
2155:
2154:
2153:
2148:
2138:
2132:
2130:
2124:
2123:
2121:
2120:
2115:
2110:
2105:
2099:
2097:
2091:
2090:
2088:
2087:
2082:
2077:
2075:Pipeline stall
2071:
2069:
2060:
2054:
2053:
2050:
2049:
2047:
2046:
2041:
2036:
2031:
2028:
2027:
2026:
2024:z/Architecture
2021:
2016:
2011:
2003:
1998:
1993:
1988:
1983:
1978:
1973:
1968:
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1958:
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1730:
1728:Virtual memory
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1559:
1552:Turing machine
1549:
1548:
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1542:
1537:
1532:
1527:
1522:
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1499:
1493:
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1433:
1432:External links
1430:
1428:
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1320:
1296:
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1262:. 31 May 2003.
1251:
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1132:Main article:
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937:
936:
932:
931:Predictability
928:
927:
923:
919:
918:
914:
913:
905:
900:
897:
896:
895:
888:Cyrix coma bug
876:
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871:
852:
847:
844:
802:
799:
798:
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783:
767:
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680:Main article:
677:
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659:supercomputers
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24:
15:
9:
6:
4:
3:
2:
3428:
3417:
3414:
3412:
3409:
3408:
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3257:
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3243:
3240:
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3235:
3234:
3232:
3230:
3226:
3220:
3217:
3213:
3210:
3208:
3205:
3204:
3203:
3200:
3196:
3193:
3192:
3191:
3188:
3186:
3183:
3181:
3180:Demultiplexer
3178:
3176:
3173:
3172:
3170:
3168:
3164:
3158:
3155:
3153:
3150:
3147:
3145:
3142:
3140:
3137:
3135:
3132:
3130:
3127:
3126:
3124:
3122:
3118:
3112:
3109:
3107:
3104:
3102:
3101:Memory buffer
3099:
3097:
3096:Register file
3094:
3092:
3089:
3087:
3084:
3082:
3079:
3078:
3076:
3074:
3070:
3062:
3059:
3057:
3054:
3053:
3052:
3049:
3047:
3044:
3042:
3039:
3037:
3036:Combinational
3034:
3033:
3031:
3029:
3025:
3019:
3016:
3012:
3009:
3008:
3006:
3003:
3001:
2998:
2996:
2993:
2988:
2985:
2983:
2980:
2979:
2977:
2974:
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2968:
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2959:
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2951:
2945:
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2926:
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2914:
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2909:
2907:
2904:
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2899:
2897:
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2887:
2884:
2882:
2879:
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2866:
2863:
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2856:
2853:
2851:
2848:
2847:
2845:
2841:
2833:
2830:
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2828:
2825:
2823:
2820:
2818:
2815:
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2800:
2798:
2795:
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2780:
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2768:
2765:
2763:
2760:
2758:
2755:
2754:
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2733:
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2711:
2708:
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2699:
2697:
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2649:
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2556:
2553:
2551:
2548:
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2543:
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2531:
2528:
2526:
2523:
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2518:
2516:
2513:
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2500:
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2139:
2137:
2136:Scoreboarding
2134:
2133:
2131:
2129:
2125:
2119:
2118:False sharing
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2100:
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2015:
2012:
2010:
2007:
2006:
2004:
2002:
1999:
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1911:Stanford MIPS
1909:
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1772:architectures
1767:
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1751:
1748:
1746:
1743:
1741:
1740:Heterogeneous
1738:
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1716:
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1691:Memory access
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1624:Random-access
1622:
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1610:
1607:
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1604:Stack machine
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1550:
1546:
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1528:
1526:
1523:
1521:
1520:with datapath
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1506:
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1502:
1500:
1498:
1494:
1490:
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1469:
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1460:
1454:
1451:
1449:
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1436:
1435:
1417:on 2013-12-27
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1391:
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1362:
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1341:
1337:
1331:
1323:
1321:9780130402677
1317:
1313:
1312:Prentice Hall
1309:
1308:
1300:
1292:
1290:9780070570641
1286:
1282:
1278:
1277:
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1205:
1198:
1195:processor of
1194:
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1155:
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1016:
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1007:
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993:
992:
986:
985:
984:
981:
980:
974:
973:
972:
969:
968:
964:
961:
960:
953:
949:
946:
935:instructions.
933:
930:
929:
924:
921:
920:
916:
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911:
906:
903:
902:
893:
889:
885:
881:
877:
874:
873:
869:
865:
861:
857:
853:
850:
849:
843:
841:
836:
835:code coverage
832:
826:
824:
818:
816:
812:
807:
795:
791:
788:
784:
781:
777:
773:
772:
771:
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747:
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740:
738:
731:
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710:
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683:
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664:
660:
655:
653:
649:
645:
641:
630:
627:
619:
609:
605:
599:
598:
593:This section
591:
587:
582:
581:
573:
571:
566:
565:
551:
548:
540:
529:
526:
522:
519:
515:
512:
508:
505:
501:
498: –
497:
493:
492:Find sources:
486:
482:
476:
475:
470:This article
468:
464:
459:
458:
453:
450:
446:
442:
438:
435:
432:
428:
425:
421:
417:
412:
410:Memory access
409:
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83:
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76:
72:
69:
65:
62: –
61:
57:
56:Find sources:
50:
46:
40:
39:
34:This article
32:
28:
23:
22:
19:
3390:Chip carrier
3328:Clock gating
3247:Mixed-signal
3144:Write buffer
3121:Control unit
2933:Clock signal
2672:accelerators
2654:Cypress PSoC
2311:Simultaneous
2236:
2128:Out-of-order
2066:
1760:Neuromorphic
1641:Architecture
1599:Belt machine
1592:Zeno machine
1525:Hierarchical
1419:. Retrieved
1415:the original
1405:
1394:. Retrieved
1384:
1372:. Retrieved
1352:
1346:
1330:
1306:
1299:
1275:
1268:
1254:
1242:. Retrieved
1237:
1233:
1223:
1204:
1187:
1156:
1152:
1148:
1145:
947:
943:
926:manufacture.
827:
819:
808:
804:
779:
769:
753:
741:
733:
726:
719:
712:
705:
698:
696:
685:
667:
663:Seymour Cray
656:
637:
622:
613:
602:Please help
597:verification
594:
569:
567:
563:
560:
543:
537:October 2020
534:
524:
517:
510:
503:
491:
479:Please help
474:verification
471:
387:The 1956–61
382:
374:
370:
366:
362:
358:
334:
319:
302:instructions
293:
287:
280:
107:
98:
88:
81:
74:
67:
55:
43:Please help
38:verification
35:
18:
3175:Multiplexer
3139:Data buffer
2850:Single-core
2822:bit slicing
2680:Coprocessor
2535:Coprocessor
2416:performance
2338:Cooperative
2328:Speculative
2288:Distributed
2247:Superscalar
2232:Instruction
2200:Parallelism
2173:Speculative
2005:System/3x0
1877:Instruction
1654:Von Neumann
1567:Post–Turing
1355:(2): 5–16.
1336:Rojas, RaĂşl
908:encounters
833:to analyze
756:delay slots
750:Workarounds
644:IBM Stretch
398:comprises:
389:IBM Stretch
354:logic gates
330:logic gates
132:Clock cycle
3405:Categories
3295:management
3190:Multiplier
3051:Logic gate
3041:Sequential
2948:Functional
2928:Clock rate
2901:Data cache
2874:Components
2855:Multi-core
2843:Core count
2333:Preemptive
2237:Pipelining
2220:Bit-serial
2163:Wide-issue
2108:Structural
2030:Tilera ISA
1996:MicroBlaze
1966:ETRAX CRIS
1861:Comparison
1706:Load–store
1686:Endianness
1421:2014-02-08
1396:2020-01-22
1379:(12 pages)
1374:2022-07-03
1240:(8): 12–14
1216:References
1168:Wait state
965:Execution
884:interrupts
868:Zilog Z280
616:March 2019
507:newspapers
345:clock rate
341:throughput
135:Instr. No.
71:newspapers
3229:Circuitry
3149:Microcode
3073:Registers
2916:coherence
2891:CPU cache
2749:Word size
2414:Processor
2058:Execution
1961:DEC Alpha
1939:Power ISA
1755:Cognitive
1562:Universal
880:atomicity
766:Solutions
654:in 1941.
640:ILLIAC II
445:Pentium D
434:Pentium 4
420:Atmel AVR
3167:Datapath
2860:Manycore
2832:variable
2670:Hardware
2306:Temporal
1986:OpenRISC
1681:Cellular
1671:Dataflow
1664:modified
1365:Archived
1244:20 March
1162:See also
801:Branches
744:compiled
441:NetBurst
422:and the
306:pipeline
101:May 2016
3343:Related
3274:Quantum
3264:Digital
3259:Boolean
3157:Counter
3056:Quantum
2817:512-bit
2812:256-bit
2807:128-bit
2650:(MPSoC)
2635:on chip
2633:Systems
2451:(FLOPS)
2264:Process
2113:Control
2095:Hazards
1981:Itanium
1976:Unicore
1934:PowerPC
1659:Harvard
1619:Pointer
1614:Counter
1572:Quantum
1193:PA-RISC
922:Economy
910:hazards
780:bubbles
676:Hazards
576:History
521:scholar
407:Execute
349:latency
85:scholar
3279:Switch
3269:Analog
3007:(IMC)
2978:(MMU)
2827:others
2802:64-bit
2797:48-bit
2792:32-bit
2787:24-bit
2782:16-bit
2777:15-bit
2772:12-bit
2609:Mobile
2525:Stream
2520:Barrel
2515:Vector
2504:(GPU)
2463:(SUPS)
2431:(IPC)
2283:Memory
2276:Vector
2259:Thread
2242:Scalar
2044:Others
1991:RISC-V
1956:SuperH
1925:Power
1921:MIPS-X
1896:PDP-11
1745:Fabric
1497:Models
1318:
1287:
890:would
689:hazard
523:
516:
509:
502:
494:
455:units.
87:
80:
73:
66:
58:
3335:(PPW)
3293:Power
3185:Adder
3061:Array
3028:Logic
2989:(TLB)
2972:(FPU)
2966:(AGU)
2960:(ALU)
2950:units
2886:Cache
2767:8-bit
2762:4-bit
2757:1-bit
2721:(TPU)
2715:(DSP)
2709:(PPU)
2703:(VPU)
2692:(GPU)
2661:(NoC)
2644:(SoC)
2579:(PoP)
2573:(SiP)
2567:(MCM)
2508:GPGPU
2498:(CPU)
2488:Types
2469:(PPW)
2457:(TPS)
2445:(IPS)
2437:(CPI)
2208:Level
2019:S/390
2014:S/370
2009:S/360
1951:SPARC
1929:POWER
1812:TRIPS
1780:Types
1368:(PDF)
1343:(PDF)
1179:Notes
962:Clock
904:Speed
776:stall
528:JSTOR
514:books
431:Intel
92:JSTOR
78:books
3313:ACPI
3046:Glue
2938:FIFO
2881:Core
2619:ASIP
2560:CPLD
2555:FPOA
2550:FPGA
2545:ASIC
2398:SPMD
2393:MIMD
2388:MISD
2381:SWAR
2361:SIMD
2356:SISD
2271:Data
2254:Task
2225:Word
1971:M32R
1916:MIPS
1879:sets
1846:ZISC
1841:NISC
1836:OISC
1831:MISC
1824:EPIC
1819:VLIW
1807:EDGE
1797:RISC
1792:CISC
1701:HUMA
1696:NUMA
1316:ISBN
1285:ISBN
1246:2017
892:hang
831:gcov
760:NOPs
500:news
449:Xeon
447:and
418:The
394:The
252:MEM
226:MEM
200:MEM
174:MEM
64:news
3308:APM
3303:PMU
3195:CPU
3152:ROM
2923:Bus
2540:PAL
2215:Bit
2001:LMC
1906:ARM
1901:x86
1891:VAX
1357:doi
606:by
483:by
338:CPU
288:In
274:EX
271:ID
268:IF
249:EX
246:ID
243:IF
229:WB
223:EX
220:ID
217:IF
203:WB
197:EX
194:ID
191:IF
177:WB
171:EX
168:ID
165:IF
47:by
3407::
3242:3D
1363:.
1353:19
1351:.
1345:.
1314:.
1310:.
1283:.
1279:.
1238:18
1236:.
1232:.
1114:9
1102:8
1087:7
1069:6
1048:5
1027:4
1009:3
994:2
982:1
970:0
842:.
652:Z3
648:Z1
436:).
292:,
257:5
234:4
210:3
186:2
162:1
157:7
154:6
151:5
148:4
145:3
142:2
139:1
1481:e
1474:t
1467:v
1444:)
1440:(
1424:.
1399:.
1377:.
1359::
1324:.
1293:.
1248:.
796:.
789:.
736:3
734:t
729:5
727:t
722:6
720:t
715:2
713:t
708:5
706:t
702:1
699:t
629:)
623:(
618:)
614:(
600:.
550:)
544:(
539:)
535:(
525:·
518:·
511:·
504:·
477:.
114:)
108:(
103:)
99:(
89:·
82:·
75:·
68:·
41:.
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