25:
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with a line size of 64 bytes. The I-cache is located on the ICU chip. The data cache, referred to as the "D-cache" by IBM, is 32 KB in size for RIOS.9 configurations and 64 KB in size for RIOS-1 configurations. The D-cache is four-way set associative with a line size of 128 bytes. The D-cache employs
989:
implemented through four identical data-cache units (DCU), each containing 16 KB of data cache. The cache and the buses that connect the DCU to the other chips are ECC protected. The DCUs also provide the interface to the memory. If two DCUs are present (RIOS.9 configuration), the memory bus is 64
652:
was considered a commercial failure and was not used in high-end workstations), it was the first to implement the then new POWER instruction set architecture and it was IBM's first successful RISC processor. For computing firsts, the POWER1 would be known for being the first CPU to implement some
940:
The FXU is responsible for decoding and executing all fixed-point instructions and floating-point load and store instructions. For execution, the FXU contains the POWER1's fixed-point register file, an arithmetic logic unit (ALU) for general instructions, and a dedicated fixed-point multiply and
1043:
link, which are intended to connect RS/6000 systems together. The optical links were not supported at the time of the RS/6000's release. The I/O unit contains approximately 0.5 million transistors, with 0.3 million used for logic and 0.2 million used for memory, on a die measuring approximately
622:. The POWER1+ was clocked slightly higher than the original POWER1, at frequencies of 25, 33 and 41 MHz, while the POWER1++ took the microarchitecture to its highest frequencies — 25, 33, 41.6, 45, 50 and 62.5 MHz. In September 1993, the POWER1 and its variants was succeeded by the
1018:
devices is arbitrated by the SCU. Although the DCUs provide the means to perform memory scrubbing, it is the SCU that controls the process. The SCU contains approximately 0.23 million transistors, all of them for logic, on a die measuring approximately 130 mm.
757:
the CPU higher, which was difficult to do with such a large multi-chip design. IBM used clustering to overcome this disadvantage in POWER1 systems, allowing them to effectively function as if they were multiprocessing systems, a concept proven by the popularity of
746:
a store-back scheme, where data that is to be stored is written to the cache instead of the memory in order to reduce the number of writes destined for the memory. The store-back scheme is used to prevent the CPU from monopolizing access to the memory.
874:
featured by the POWER1, assuming that it is a RIOS-1 configuration, is 6.9 million, with 2.04 million used for logic and 4.86 million used for memory. The die area of all the chips combined is 1,284 mm. The total number of signal pins is 1,464.
969:
instructions, which contributed to the POWER1's high floating point performance. In most processors, a multiply and an add, which is common in technical and scientific floating-point code, cannot be executed in one cycle, as in the POWER1. Use of
912:
were also supported by using a prediction bit in the branch instructions, with the results discarded before being saved if the branch was not taken. The alternate instruction would be buffered and discarded if the branch was taken. Consequently,
618:. The POWER1 received two upgrades, one in 1991, with the introduction of the POWER1+ and in 1992, with the introduction of POWER1++. These upgraded versions were clocked higher than the original POWER1, made possible by improved
907:
The BPU was capable of dispatching multiple instructions to the fixed and floating point instructions queues while it was executing a program flow control instruction (up to four simultaneously and out of order). Speculative
990:
bits wide, and if four DCUs are present (RIOS-1 configuration), the memory bus is 128 bits wide. The memory interface portion of the DCUs provide three features that improves the reliability and availability of the memory:
941:
divide unit. It also contains instruction buffers that receive both fixed- and floating-point instructions from the ICU, passing on the floating-point instructions to the FPU, and a 128-entry two-way set-associative D-
855:, the PCB has eight planes for routing wires, four for power and ground and four for signals. There are two signal planes on each side of the board, while the four power and ground planes are in the center.
928:. The rest of the fields could be used by other instructions. The loop register is a counter for "decrement and branch on zero" loops with no branch penalty, a feature similar to those found in some
1002:. Each DCU contains approximately 1.125 million transistors, with 0.175 million used for logic and 0.95 million used for SRAM, on a die measuring approximately 130 mm² (11.3 × 11.3 mm).
977:
The floating-point register file is also located on the FPU chip. It contains 32 64-bit floating-point registers, six rename registers and two registers that are used by divide instructions.
945:
for address translation. The FXU contains approximately 0.5 million transistors, with 0.25 million used for logic and 0.25 used for memory, on a die measuring approximately 160 mm.
844:. The RIOS-1 configuration has four DCUs, the intended amount, and was clocked at up to 40 MHz, whereas the RIOS.9 CPU had two DCUs and was clocked at lower frequencies.
543:
723:
is 52 bits long. The larger virtual address space was chosen because it was beneficial for the performance of applications, allowing each one to have a large 4
766:
microprocessors, the lack of multiprocessing was passed on to these later POWER processors. Multiprocessing was not supported until the introduction of the
896:, the condition code register and a loop register. The ICU contains 0.75 million transistors with 0.2 million used for logic and 0.55 million used for
999:
924:
The condition code register has eight field sets, with the first two reserved for fixed and floating point instructions and the seventh for
536:
741:
hierarchy with separate instruction and data caches. The instruction cache, referred to as the "I-cache" by IBM, is 8 KB in size and is
995:
1170:
Montoye, R. K.; Hokenek, E.; Runyon, S. L. (January 1990). "Design of the IBM RISC System/6000 floating-point execution unit".
1054:
673:
576:
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118:
812:
The POWER1 is a multi-chip CPU built from separate chips that are connected to each other by buses. The POWER1 consists of an
590:, before introduction of successors required the original name to be replaced with one that used the same naming scheme (POWER
1277:— Relevant parts: Chapter 3 (how the POWER architecture is meant to be implemented), Chapters 4 and 5 (describes the POWER1).
491:
1295:
1233:
Bakoglu, H. B.; Grohoski, G. F.; Montoye, R. K. (January 1990). "The IBM RISC System/6000 processor: Hardware overview".
501:
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The POWER1's I/O interfaces are implemented by the I/O unit, which contains an I/O channel controller (IOCC) and two
476:
68:
46:
39:
619:
568:
1300:
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unit. Due to its modular design, IBM was able to create two configurations by simply varying the number of DCUs,
644:
The POWER1 is notable as it represented a number of firsts for IBM and computing in general. It was IBM's first
1270:
1010:
The POWER1 is controlled by the SCU chip. All communications between the ICU, FXU and DCU chips as well as the
637:, a radiation-hardened variant of the RSC for space applications. An indirect derivative of the POWER1 is the
1039:
transactions between the Micro
Channel adapters and the system memory. The two SLAs each implement a serial
1290:
942:
113:
1149:"GCC 4.5 Release Series — Changes, New Features, and Fixes - GNU Project - Free Software Foundation (FSF)"
897:
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1032:
759:
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909:
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The POWER1's floating point unit executes floating-point instructions issue by the ICU. The FPU is
929:
33:
966:
688:
564:
974:
also means that the data is only rounded once, improving the precision of the result slightly.
971:
658:
144:
50:
1212:
Grohoski, G. F. (January 1990). "Machine organization of the IBM RISC System/6000 processor".
848:
817:
704:
1191:
Oehler, R. R.; Groves, R. D. (January 1990). "IBM RISC System/6000 processor architecture".
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954:
735:
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8:
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712:
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753:, and as such was disadvantaged, as the only way performance could be improved was by
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829:
654:
638:
443:
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395:
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The ICU contains the instruction cache, referred to as the "I-cache" by IBM and the
633:(RSC), feature-reduced single-chip variant for entry-level RS/6000 systems, and the
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1200:
1179:
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991:
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851:(PCB), using through-hole technology. Due to the large number of chips with wide
750:
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processors that followed it, measuring in hundreds of different implementations.
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863:
626:(known briefly as the "RIOS2"), an evolution of the POWER1 microarchitecture.
1284:
1040:
716:
481:
195:
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1148:
641:, a feature-reduced variant of the RSC intended for consumer applications.
611:
471:
185:
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170:
866:(CPGA) packages that can have up to 300 pins and dissipate a maximum of 4
691:
removed support for POWER1 (RIOS) and POWER2 (RIOS2) in the 4.5 release.
662:
594:) as its successors in order to differentiate it from the newer designs.
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16:
Multi-chip CPU by IBM implementing the POWER instruction set architecture
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321:
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process with three layers of interconnect. The chips are packaged in
825:
813:
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681:
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The POWER1 was also the origin for the highly successful families of
486:
152:
763:
703:
two-way superscalar CPU. It contains three major execution units, a
602:
The POWER1 was introduced in 1990, with the introduction of the IBM
762:
based on the POWER1. As the POWER1 was the basis of the POWER2 and
724:
649:
375:
858:
The chips that make up the POWER1 are fabricated in a 1.0 ÎĽm
1114:
1108:
1072:
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783:
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Although the POWER1 was a high-end design, it was not capable of
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measures approximately 160 mm (12.7 Ă— 12.7 mm).
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715:(FPU). Although the POWER1 is a 32-bit CPU with a 32-bit
615:
572:
1165:
1232:
1169:
614:, which featured the POWER1 clocked at 20, 25 or 30
965:(64-bit) instructions. It is capable of performing
921:are dealt with without incurring branch penalties.
648:processor intended for high-end applications (the
1282:
883:
661:, a technique that improves the performance of
1005:
847:The chips are mounted on the “CPU planar”, a
629:The direct derivatives of the POWER1 are the
537:
1190:
948:
1261:Weiss, Shlomo; Smith, James Edward (1994).
665:processors but was previously reserved for
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807: (Each line represents a 32-bit bus.)
796: (Each line represents a 32-bit bus.)
544:
530:
1031:adapters (SLAs). The IOCC implements the
935:
805:The chip complex of the RIOS.9 processor
794:The chip complex of the RIOS-1 processor
69:Learn how and when to remove this message
1211:
980:
800:
789:
782:A POWER CPU from an entry-level desktop
777:
32:This article includes a list of general
1235:IBM Journal of Research and Development
1214:IBM Journal of Research and Development
1193:IBM Journal of Research and Development
1172:IBM Journal of Research and Development
773:
1283:
1055:IBM POWER Instruction Set Architecture
582:(ISA). It was originally known as the
586:or, when in an abbreviated form, the
160:NXP (formerly Freescale and Motorola)
1035:interface and controls both I/O and
694:
18:
13:
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870:of heat each. The total number of
38:it lacks sufficient corresponding
14:
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23:
1053:Instruction set architectures:
108:Architecture and classification
1141:
1:
1134:
892:(BPU). The BPU contains the
884:Instruction-cache unit (ICU)
580:instruction set architecture
7:
1296:Superscalar microprocessors
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1022:
10:
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1006:Storage-control unit (SCU)
597:
949:Floating-point unit (FPU)
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99:
91:
86:
878:
167:PowerPC e series (2006)
985:The POWER1 has a 64 KB
932:such as the TMS320C30.
743:two-way set associative
620:semiconductor processes
53:more precise citations.
1301:32-bit microprocessors
1119:Scalable POWERparallel
936:Fixed-point unit (FXU)
890:branch processing unit
864:ceramic pin grid array
809:
798:
787:
659:out-of-order execution
300:PowerPC series (1992)
981:Data-cache unit (DCU)
849:printed circuit board
804:
793:
781:
575:that implemented the
1123:Related technology:
774:Physical description
584:RISC System/6000 CPU
467:OpenPOWER Foundation
114:Instruction set
1291:IBM microprocessors
1265:. Morgan Kaufmann.
1247:10.1147/rd.341.0012
1226:10.1147/rd.341.0037
1205:10.1147/rd.341.0023
1184:10.1147/rd.341.0059
926:vector instructions
824:(FPU), a number of
822:floating point unit
713:floating point unit
87:General information
83:
1113:Computer Systems:
972:fused multiply–add
832:unit (SCU) and an
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760:SP1 supercomputers
520:historic in italic
348:RAD series (1997)
204:Qor series (2008)
81:
1263:POWER and PowerPC
814:instruction-cache
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695:Microarchitecture
655:register renaming
610:and POWERstation
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516:Cancelled in gray
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1069:RISC Single Chip
992:memory scrubbing
963:double precision
959:single precision
957:and can execute
915:subroutine calls
818:fixed-point unit
806:
795:
734:CPU that uses a
730:The POWER1 is a
717:physical address
705:fixed-point unit
699:The POWER1 is a
687:The open source
631:RISC Single Chip
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751:multiprocessing
727:address range.
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1067:Processors:
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1000:bit steering
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967:multiply-add
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711:(BPU) and a
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606:POWERserver
601:
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37:
1153:gcc.gnu.org
1125:PowerPC 601
1041:fibre optic
1029:serial link
872:transistors
709:branch unit
663:superscalar
639:PowerPC 601
588:RS/6000 CPU
100:Designed by
51:introducing
1285:Categories
1272:1558602798
1135:References
987:data cache
919:interrupts
900:. The ICU
826:data-cache
732:big-endian
667:mainframes
569:fabricated
562:multi-chip
434:PWRficient
34:references
1063:Power ISA
955:pipelined
820:(FXU), a
770:in 1998.
707:(FXU), a
682:Power ISA
487:Power.org
482:Blue Gene
153:Power ISA
130:Successor
119:POWER ISA
1048:See also
1023:I/O unit
910:branches
755:clocking
653:form of
410:Espresso
403:Broadway
92:Launched
1115:RS/6000
1109:Power10
1073:RAD6000
1059:PowerPC
784:RS/6000
678:PowerPC
635:RAD6000
608:servers
604:RS/6000
598:History
507:AltiVec
364:RAD5500
353:RAD6000
337:(2010)
292:Power10
213:Qorivva
149:PowerPC
125:History
47:improve
1269:
1105:POWER9
1101:POWER8
1097:POWER7
1093:POWER6
1089:POWER5
1085:POWER4
1081:POWER3
1077:POWER2
1012:memory
842:RIOS.9
840:and a
838:RIOS-1
768:POWER3
719:, its
701:32-bit
624:POWER2
558:POWER1
380:(1996)
378:series
359:RAD750
287:POWER9
282:POWER8
277:POWER7
272:POWER6
266:POWER5
259:POWER4
252:POWER3
245:POWER2
238:POWER1
151:, and
134:POWER2
82:POWER1
36:, but
879:Chips
853:buses
739:cache
674:POWER
577:POWER
560:is a
444:Xenon
428:Titan
419:Other
396:Gekko
231:Power
208:QorIQ
196:e6500
191:e5500
145:POWER
1267:ISBN
1129:RS64
1014:and
998:and
930:DSPs
917:and
898:SRAM
860:CMOS
764:P2SC
680:and
657:and
650:ROMP
646:RISC
556:The
502:CHRP
497:PReP
492:PAPR
477:RISC
450:X704
439:Cell
376:RS64
322:74xx
186:e600
181:e500
176:e300
171:e200
95:1990
1243:doi
1222:doi
1201:doi
1180:doi
1037:DMA
1016:I/O
996:ECC
943:TLB
902:die
834:I/O
616:MHz
573:IBM
571:by
565:CPU
343:A2O
340:A2I
329:970
316:7xx
311:4xx
305:6xx
223:IBM
103:IBM
1287::
1239:34
1237:.
1218:34
1216:.
1197:34
1195:.
1176:34
1174:.
1151:.
1127:,
1117:,
1107:,
1103:,
1099:,
1095:,
1091:,
1087:,
1083:,
1079:,
1075:,
1071:,
1061:,
1057:,
994:,
725:GB
676:,
669:.
518:,
335:A2
147:,
1275:.
1249:.
1245::
1228:.
1224::
1207:.
1203::
1186:.
1182::
1155:.
868:W
592:n
545:e
538:t
531:v
72:)
66:(
61:)
57:(
43:.
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