710:(P2SC) was released in October 1996 as the successor of the POWER2. It was a single-chip implementation of the eight-chip POWER2, integrating 15 million transistors on a 335 mm die manufactured in IBM's 0.29 μm five-layer metal CMOS-6S process. The first version ran at 120 or 135 MHz, nearly twice as fast as the POWER2 at 71.5 MHz, with the memory and I/O buses running at half speed to support the higher clock frequency. IBM claimed that the performance of this version was 5.5 SPECint95_base and 14.5 SPECfp95_base. A faster 160 MHz part fabricated in the 0.25 μm CMOS-6S2 process was announced at the Microprocessor Forum in October 1997.
25:
629:
667:
89:
687:. The cache tags were contained on the storage control unit chip. The POWER2+ has a narrower 64- or 128-bit memory bus and a smaller 64 or 128 KB data cache. As there is less cache, the data cache unit chips are smaller as a result, and the revised storage control unit chip is also smaller. A goal for the six-chip configuration was to reduce cost, and therefore the chips are packaged in a
700:
678:
was introduced in May 1994 as the POWER2+. Transaction processing workloads benefited from the addition of a L2 cache with capacities of 512 KB, 1 MB and 2 MB. This cache was implemented off-package with industry-standard burst SRAMs. The cache was connected to the POWER2+ via a 64-
649:
integrated circuits, depending on the amount of data cache (the 256 KB configuration required eight chips). The partitioning of the design was identical to that of the POWER1: an instruction cache unit chip, a fixed-point unit chip, a floating-point unit chip, a storage control unit chip, and
653:
The eight-chip configuration contains a total of 23 million transistors and a total die area of 1,215 mm. The chips are manufactured by IBM in its 0.72 μm CMOS process, which features a 0.45 μm effective channel length; and one layer of polysilicon and four layers of metal
636:
Improvements over the POWER1 included enhancements to the POWER instruction set architecture (consisting of new user and system instructions and other system-related features), higher clock rates (55 to 71.5 MHz), an extra
717:(TLB) capacities were halved to 128 KB and 256 entries, respectively, and a rarely used feature that locked entries in the TLB was not implemented in order to fit the original design onto a single die.
613:. When the Alpha 21064A was introduced in 1993, the POWER2 lost the lead and became second. IBM claimed that the performance for a 62.5 MHz POWER2 was 73.3 SPECint92 and 134.6 SPECfp92.
565:
645:, a larger 32 KB instruction cache, and a larger 128 or 256 KB data cache. The POWER2 was a multi-chip design consisting of six or eight
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513:
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911:
Hicks, T. N.; Fry, R. E.; Harvey, P. E. (September 1994). "POWER2 floating-point unit: Architecture and implementation".
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39:
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1021:
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Barreh, J. I.; Golla, R. T.; Arimilli, L. B.; Jordan, P. J. (September 1994). "POWER2 instruction cache unit".
954:
Shippy, D. J.; Griffith, T. W. (September 1994). "POWER2 fixed-point, data cache, and storage control units".
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714:
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125:
789:"GCC 4.5 Release Series — Changes, New Features, and Fixes - GNU Project - Free Software Foundation (FSF)"
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729:
518:
984:
White, S. W.; Dhawan, S. (September 1994). "POWER2: Next generation of the RISC System/6000 family".
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at chess in 1997. However, the computer's chess-playing capabilities were a result of its
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systems. When introduced, the POWER2 was the fastest microprocessor, surpassing the
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937:
885:
733:
892:
Gwennap, Linley (4 October 1993). "IBM Regains
Performance Lead with Power2".
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883:
DeTar, Jim (22 August 1994). "IBM details Power2+; DEC bares new Alpha AXP".
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The P2SC was not a complete copy of the POWER2, the L1 data cache and data
679:(for low-end systems) or 128-bit bus (for high-end systems). The cache was
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removed support for POWER1 (RIOS) and POWER2 (RIOS2) in the 4.5 release.
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Gwennap, Linley (26 August 1996). "IBM Crams POWER2 onto Single Chip".
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Statt, Paul (January 1994). "Power2 Takes the Lead--For Now".
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line in 1998. A notable use of the P2SC was the 30-node IBM
1028:— Chapter 6 describes the POWER2 architecture and processor
471:
699:
853:
826:"IBM LAUNCHES BRAND NEW CHIP FAMILY FOR THE RS/6000 LINE"
591:
944:
Shippy, David (9 August 1994). "The Power2+ Processor".
874:Ball, Richard (15 October 1997). "Chipville USA".
654:interconnect. The chips are packaged in a ceramic
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674:An improved version of the POWER2 optimized for
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658:(MCM) that measures 64 mm by 64 mm.
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1012:Weiss, Shlomo; Smith, James Edward (1994).
983:
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605:, debuting in September 1993 within IBM's
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87:
69:Learn how and when to remove this message
824:Smith, Norris Parker (11 October 1996).
724:as IBM's flagship microprocessor on the
698:
691:connect (SBC) package instead of a MCM.
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627:
32:This article includes a list of general
986:IBM Journal of Research and Development
956:IBM Journal of Research and Development
913:IBM Journal of Research and Development
856:IBM Journal of Research and Development
732:supercomputer that beat world champion
1047:Computer-related introductions in 1993
1034:
754:IBM POWER Instruction Set Architecture
601:. The POWER2 was the successor of the
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182:NXP (formerly Freescale and Motorola)
16:1993 family of microprocessors by IBM
931:Lineback, J. Robert (28 June 1993).
683:, had a 128-byte line size, and was
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650:two or four data cache unit chips.
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1005:
933:"IBM readies RISC Progeny in Unix"
38:it lacks sufficient corresponding
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120:Architecture and classification
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744:chips, rather than the P2SCs.
720:The P2SC was succeeded by the
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632:The MCM of a POWER2 processor
715:translation lookaside buffer
599:instruction set architecture
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1052:Superscalar microprocessors
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695:POWER2 Super Chip (P2SC)
189:PowerPC e series (2006)
53:more precise citations.
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676:transaction processing
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322:PowerPC series (1992)
904:Microprocessor Report
895:Microprocessor Report
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594:that implemented the
489:OpenPOWER Foundation
126:Instruction set
1042:IBM microprocessors
1016:. Morgan Kaufmann.
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968:10.1147/rd.385.0503
925:10.1147/rd.385.0525
868:10.1147/rd.385.0537
643:floating point unit
582:, originally named
99:General information
83:
877:Electronics Weekly
740:running on custom
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542:historic in italic
370:RAD series (1997)
226:Qor series (2008)
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1014:POWER and PowerPC
708:POWER2 Super Chip
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947:Hot Chips 6
835:21 December
830:hocwire.com
793:gcc.gnu.org
689:solder ball
647:semi-custom
624:Description
611:Alpha 21064
142:Predecessor
112:Designed by
51:introducing
1036:Categories
1023:1558602798
848:References
814:White 1994
456:PWRficient
93:POWER2 MCM
34:references
730:Deep Blue
588:processor
509:Power.org
504:Blue Gene
175:Power ISA
152:Successor
131:POWER ISA
748:See also
432:Espresso
425:Broadway
104:Launched
726:RS/6000
703:A P2SC+
662:POWER2+
607:RS/6000
586:, is a
529:AltiVec
386:RAD5500
375:RAD6000
359:(2010)
314:Power10
235:Qorivva
171:PowerPC
137:History
47:improve
1020:
769:POWER3
764:POWER1
722:POWER3
603:POWER1
580:POWER2
402:(1996)
400:series
381:RAD750
309:POWER9
304:POWER8
299:POWER7
294:POWER6
288:POWER5
281:POWER4
274:POWER3
267:POWER2
260:POWER1
173:, and
156:POWER3
146:POWER1
82:POWER2
36:, but
775:Notes
596:POWER
584:RIOS2
466:Xenon
450:Titan
441:Other
418:Gekko
253:Power
230:QorIQ
218:e6500
213:e5500
167:POWER
1018:ISBN
977:Byte
837:2021
742:VLSI
641:and
578:The
524:CHRP
519:PReP
514:PAPR
499:RISC
472:X704
461:Cell
398:RS64
344:74xx
208:e600
203:e500
198:e300
193:e200
107:1993
994:doi
964:doi
921:doi
864:doi
592:IBM
365:A2O
362:A2I
351:970
338:7xx
333:4xx
327:6xx
245:IBM
115:IBM
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