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The UltraSPARC required a mandatory external secondary cache. The cache is unified, has a capacity of 512 KB to 4 MB and is direct-mapped. It can return data in a single cycle. The external cache is implemented with synchronous SRAMs clocked at the same frequency as the microprocessor, as ratios were
277:
The execution units were simplified relative to the SuperSPARC to achieve higher clock frequencies - an example of a simplification is that the ALUs were not cascaded, unlike the SuperSPARC, to avoid restricting clock frequency.
333:(DSP) with some features missing such as three levels of metal instead of four and a 0.55 feature size, before it was used to fabricate the UltraSPARC to avoid a repeat of the fabrication problems encountered with
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The floating-point unit consists of five functional units. One executes floating point adds and subtracts, one multiplies, one divides and square-roots. Two units are for executing SIMD instructions defined by the
289:, of which the UltraSPARC has eight, the actual number of registers is 144. The register file has seven read and three write ports. The integer register file provides registers to two
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The UltraSPARC has two levels of cache, primary and secondary. There are two primary caches, one for instructions and one for data. Both have a capacity of 16 KB.
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process as Texas
Instruments claimed it did not scale well to 0.5 ÎĽm processes and offered little performance improvement. The process was perfected on TI's MVP
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and the load/store unit. The two ALUs can both execute arithmetic, logic and shift instructions but only one can execute multiply and divide instructions.
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301:(VIS). The floating-point register file contains thirty-two 64-bit registers. It has five read ports and three write ports.
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It contained 3.8 million transistors. It was fabricated in Texas
Instruments' EPIC-3 process, a 0.5 ÎĽm
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Greenley, D. et al. (1995). "UltraSPARC: The next generation superscalar 64-bit SPARC".
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Gwennap, Linley (5 December 1994). "UltraSparc Adds
Multimedia Instructions".
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Gwennap, Linley (3 October 1994). "UltraSparc
Unleashes SPARC Performance".
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The UltraSPARC is packaged in a 521-contact plastic
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complementary metal–oxide–semiconductor
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313:not supported. It is accessed via the data bus.
46:but its sources remain unclear because it lacks
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285:has 32 64-bit entries. As the SPARC ISA uses
261:microprocessor that executes instructions in
16:Microprocessor developed by Sun Microsystems
1143:Common Development and Distribution License
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77:Learn how and when to remove this message
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265:. It includes a nine-stage integer
101:A 200 MHz UltraSPARC microprocessor
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257:The UltraSPARC is a four-issue
157:Architecture and classification
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1:
1178:Open Source University Meetup
1087:Sun Microsystems Laboratories
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243:instruction set architecture
152:143 MHz to 200 MHz
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1342:Superscalar microprocessors
1297:The Network is the Computer
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32:This article includes a
861:Ultra Port Architecture
174:Physical specifications
61:more precise citations.
1347:64-bit microprocessors
1148:Java Community Process
1015:StorageTek 5800 System
866:Visual Instruction Set
398:, Volume 8, Number 13.
299:Visual Instruction Set
291:arithmetic logic units
1337:SPARC microprocessors
1102:Project Looking Glass
404:Microprocessor Report
395:Microprocessor Report
1061:Visualization System
1056:Constellation System
389:: pp. 442–451.
163:Instruction set
1332:Sun microprocessors
949:Java Desktop System
107:General information
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836:Modular Datacenter
451:Acquired by Oracle
353:Related processors
234:and fabricated by
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34:list of references
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1266:Procom Technology
1246:Lighthouse Design
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1218:
1201:Andy Bechtolsheim
1020:StorageTek SL8500
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628:Blade workstation
253:Microarchitecture
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283:register file
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247:Marc Tremblay
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230:developed by
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67:November 2017
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1224:Acquisitions
1211:Vinod Khosla
1025:Open Storage
725:
623:Blade server
554:SPARCclassic
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311:
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281:The integer
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120:Discontinued
73:
64:
53:Please help
45:
1163:OpenSolaris
1066:Grid Engine
1044:Performance
974:Java System
944:OpenWindows
685:Cobalt Qube
670:JavaStation
317:Fabrication
259:superscalar
200:Predecessor
138:Performance
128:Designed by
59:introducing
1326:Categories
1281:Tarantella
1276:StorageTek
999:VirtualBox
964:StarOffice
726:UltraSPARC
721:SuperSPARC
716:microSPARC
699:Processors
690:Cobalt RaQ
611:Enterprise
380:References
359:SuperSPARC
335:SuperSPARC
224:UltraSPARC
204:SuperSPARC
148:clock rate
90:UltraSPARC
1168:OpenSPARC
1132:Community
1111:Education
994:GlassFish
821:Fireplane
211:Successor
1313:Category
1256:MySQL AB
1241:Gridware
1196:Bill Joy
1153:NetBeans
1097:Fortress
1092:picoJava
1080:Research
888:Software
826:LOM port
785:SPARC T5
780:SPARC T4
775:SPARC T3
458:Hardware
349:(PBGA).
267:pipeline
263:in-order
240:SPARC V9
168:SPARC V9
112:Launched
1290:Slogans
1173:OpenJDK
1008:Storage
969:iPlanet
934:SunView
900:Solaris
841:Neptune
711:MB86900
487:Sun386i
465:Systems
341:Package
245:(ISA).
195:History
55:improve
1271:SavaJe
1188:People
1071:Lustre
954:Studio
741:Gemini
327:BiCMOS
1123:BlueJ
1051:Cloud
984:MySQL
895:SunOS
811:Sun4d
804:Other
706:SPARC
658:X4500
653:T2000
616:10000
564:Ultra
559:Netra
492:Sun-4
482:Sun-3
477:Sun-2
472:Sun-1
305:Cache
226:is a
180:Cores
143:Max.
40:, or
1261:Pixo
1118:SCPs
959:Java
939:NeWS
927:ZFS+
910:NIS+
856:SPOT
831:MBus
816:SBus
795:MAJC
790:Rock
648:E25K
633:Fire
222:The
123:1997
115:1995
1035:ZFS
1030:QFS
989:xVM
922:ZFS
917:NFS
905:NIS
680:Ray
643:15K
638:12K
537:IPX
532:IPC
145:CPU
1328::
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Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
