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Address decoder

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The address decoder uses the different combinatorial logic to place the memory modules or chips in the address space of a processor. The memory modules often have a smaller capacity than the address space. In most cases, several modules can be used, even if they are completely identical in structure.
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bits and one or more outputs for device selection signals. When the address for a particular device appears on the address inputs, the decoder asserts the selection output for that device. A dedicated, single-output address decoder may be incorporated into each device on an address bus, or a single
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Such a memory cell consists of a fixed number of memory elements or bits. The address decoder is connected to an address bus and reads the address created there. Using a special switching logic, it uses this address to calculate which memory cell is to be accessed. It then selects that cell by
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can be used as address decoders. For example, when used as an address decoder, the 74154 provides four address inputs and sixteen (i.e., 2) device selector outputs. An address decoder is a particular use of a
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For this purpose, the memory modules or memory chips have selection inputs, usually referred to as chip select pin (CS) or chip enable pin (CE) pin. These inputs often have a negative logic function (
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An address decoder is also used to select the appropriate one of multiple memory modules or memory chips when a particular address is provided by the processor system's address bus.
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An address decoder is a commonly used component in microelectronics that is used to select memory cells in randomly addressable memory devices.
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Depending on the type of decoder, the logic used to select the memory cell can under certain circumstances be programmable.
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selecting it via a special control line. This line is also known as the select line. In dynamic memories (
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A single address decoder with n address input bits can serve up to 2 devices. Several members of the
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libraries. They are discussed in introductory textbooks in digital logic design.
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Address decoders are fundamental building blocks for systems that use
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It must be ensured that they differ in the address range.
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Address decoder selects the appropriate memory module
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Address decoder selects the storage cell in a memory
182:(2nd ed.). Ellis Horwood. pp. 489–494. 272: 255: 175: 41:address decoder may serve multiple devices. 262: 248: 15: 273: 179:Digital and microprocessor engineering 133: 131: 214: 128: 20:The four states of a 2-to-4 decoder 13: 14: 297: 218: 36:that has two or more inputs for 196: 169: 1: 121: 234:. You can help Knowledge by 7: 10: 302: 213: 286:Computer hardware stubs 203:Datasheet for 74HCT154 148:The Art of Electronics 21: 176:S. J. Cahill (1993). 19: 57:circuit known as a " 50:integrated circuits 26:digital electronics 22: 243: 242: 228:computer hardware 189:978-0-13-213398-2 162:978-0-521-37095-0 293: 281:Digital circuits 264: 257: 250: 222: 215: 205: 200: 194: 193: 173: 167: 166: 135: 113: 109: 301: 300: 296: 295: 294: 292: 291: 290: 271: 270: 269: 268: 211: 209: 208: 201: 197: 190: 174: 170: 163: 136: 129: 124: 111: 107: 101: 82: 30:address decoder 12: 11: 5: 299: 289: 288: 283: 267: 266: 259: 252: 244: 241: 240: 223: 207: 206: 195: 188: 168: 161: 126: 125: 123: 120: 100: 97: 81: 78: 55:binary decoder 34:binary decoder 9: 6: 4: 3: 2: 298: 287: 284: 282: 279: 278: 276: 265: 260: 258: 253: 251: 246: 245: 239: 237: 233: 230:article is a 229: 224: 221: 217: 216: 212: 204: 199: 191: 185: 181: 180: 172: 164: 158: 154: 150: 149: 144: 143:Winfield Hill 140: 139:Paul Horowitz 134: 132: 127: 119: 115: 104: 96: 93: 91: 85: 77: 75: 71: 67: 62: 60: 59:demultiplexer 56: 51: 47: 42: 39: 35: 31: 27: 18: 236:expanding it 225: 210: 198: 178: 171: 146: 116: 105: 102: 94: 86: 83: 63: 43: 29: 23: 46:7400 series 275:Categories 122:References 145:(1989). 153:685,766 38:address 186:  159:  226:This 66:buses 32:is a 28:, an 232:stub 184:ISBN 157:ISBN 141:and 90:DRAM 74:ASIC 72:and 70:FPGA 110:or 48:of 24:In 277:: 155:. 130:^ 112:CE 108:CS 263:e 256:t 249:v 238:. 192:. 165:.

Index


digital electronics
binary decoder
address
7400 series
integrated circuits
binary decoder
demultiplexer
buses
FPGA
ASIC
DRAM


Paul Horowitz
Winfield Hill
The Art of Electronics
685,766
ISBN
978-0-521-37095-0
Digital and microprocessor engineering
ISBN
978-0-13-213398-2
Datasheet for 74HCT154
Stub icon
computer hardware
stub
expanding it
v
t

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