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specification states that left audio is transmitted on the low cycle of the word select clock and the right channel is transmitted on the high cycle. It is typically synchronized to the falling edge of the serial clock, as the data is latched on the rising edge. The word select clock changes one bit clock period before the MSB is transmitted. This enables, for example, the receiver to store the previous word and clear the input for the next.
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The I²S connection was not intended to be used via cables, and most integrated circuits will not have the correct impedance for coaxial cables. As the impedance adaptation error associated with the different line lengths can cause differences in propagation delay between the clock line and data line,
262:
The word select clock lets the device know whether channel 1 (WS = 0) or channel 2 (WS = 1) is currently being sent, because I²S allows two channels to be sent on the same data line. It is a 50% duty-cycle signal that has the same frequency as the sample frequency. For stereo material, the I²S
152:(IC) components of an electronic device. An I²S bus separates clock and serial data signals, resulting in simpler receivers than those required for asynchronous communications systems that need to recover the clock from the data stream. Alternatively, I²S is spelled
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this can result in synchronization problems between the SCK, WS and data signals, mainly at high sampling frequencies and bitrates. As the I²S bus doesn't have any error detection mechanism, this can cause significant decoding errors.
254:, the number of bits per channel and the number of channels. So, for example, CD Audio with a sample frequency of 44.1 kHz, with 16 bits of precision and two channels (stereo) has a bit clock frequency of:
399:, Musica Pristina and Wyred4Sound use an HDMI connector. Dutch manufacturer Van Medevoort has implemented Q-link in some of its equipment, which transfers I²S over 4 RCA connectors (data, MCK, LRCK, BCK).
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551:
Clock source for the delta-sigma modulators and digital filters. ... It is the clock that is used by the audio codec ... to time and/or drive its own internal operation.
243:
Master clock (typically 256 x LRCLK); not part of the standard, but is commonly included for synchronizing the internal operation of the analog/digital converters
599:
Audio converters based on the delta-sigma (ΔΣ) architecture require an internal master clock that operates at a much faster rate than the target sample rate.
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Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
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In audio equipment, I²S is sometimes used as an external link between a CD player or digital audio streaming device and an external
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The bit clock pulses once for each discrete bit of data on the data lines. The bit clock frequency is the product of the
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176:) and was first revised June 5, 1996. The standard was last revised on February 17, 2022 and updated terms
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There is no standard interconnecting cable for this application. Some manufacturers simply provide three
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564:"PCM1781 (or any I2S DAC) clock sources - Audio Converters Forum - Audio Converters - TI E2E Community"
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228:); a.k.a. left-right clock (LRCLK) or frame sync (FS).; 0 = Left channel, 1 = Right channel
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517:"Technical Article MS-2275: Common Inter-IC Digital Interfaces for Audio Data Transfer"
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592:"Application Report SLAA469 Audio Serial Interface Configurations for Audio Codecs"
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The protocol standard was introduced in 1986 by
Philips Semiconductor (now
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324: in this section. Unsourced material may be challenged and removed.
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160:(pronounced eye-eye-ess). Despite a similar name, I²S is unrelated to
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As shown in the diagram, the protocol requires the following lines:
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True, the master (modulator) clock is not part of the I2S standard
144:
interface protocol for transmitting two-channel, digital audio as
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A serial communication protocol for two-channel digital audio
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Common inter-IC digital interfaces for audio data transfer
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Pages displaying short descriptions of redirect targets
467:. Philips Semiconductors. June 5, 1996. Archived from
239:The protocol may also include the following lines:
426: – Multiplexing technique for digital signals
411: – Synchronous serial communication interface
1429:
1013:Coherent Accelerator Processor Interface (CAPI)
26:"i2s" redirects here. Not to be confused with
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420: – Standardized digital audio interface
235:), a.k.a. SDATA, SDIN, SDOUT, DACDAT, ADCDAT
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340:Learn how and when to remove this message
312:Relevant discussion may be found on the
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140:, pronounced "eye-squared-ess") is a
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322:adding citations to reliable sources
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246:A multiplexed data line for upload
14:
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590:Arbona, Jorge (September 2010).
294:
486:"UM11732 I2S bus specification"
305:needs additional citations for
1438:Audio communications protocols
604:
583:
556:
258:44.1 kHz × 16 × 2 = 1.4112 MHz
134:Inter-Integrated Circuit Sound
1:
1008:Intel Ultra Path Interconnect
613:"I2S standards from PS Audio"
541:electronics.stackexchange.com
515:Lewis, Jerad (January 2012).
430:
986:Intel QuickPath Interconnect
976:Direct Media Interface (DMI)
611:McGowan, Paul (2010-04-02).
537:"MCLK in I2S audio protocol"
156:(pronounced eye-two-ess) or
7:
409:Serial peripheral interface
402:
354:digital-to-analog converter
221:), a.k.a. bit clock (BCLK).
84:; 38 years ago
10:
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971:Compute Express Link (CXL)
424:Time-division multiplexing
197:
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18:
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1208:IEEE-1284 (parallel port)
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1123:logical device interface)
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286:As an audio interconnect
19:Not to be confused with
387:connector. Others like
117:2 clock lines (SCK, WS)
770:List of bus bandwidths
646:I²S and STM32F4 Slides
522:. Analog Devices, Inc.
210:
205:
146:pulse-code modulation
69:Philips Semiconductor
1213:IEEE-1394 (FireWire)
951:PCI Extended (PCI-X)
318:improve this article
276:most significant bit
51:Serial communication
32:IS2 (disambiguation)
28:IIS (disambiguation)
1054:Parallel ATA (PATA)
648:- Auburn University
474:on January 2, 2007.
462:"I²S Specification"
391:(now defunct) used
43:
36:I2 (disambiguation)
1443:NXP Semiconductors
961:PCI Express (PCIe)
211:
174:NXP Semiconductors
150:integrated circuit
115:1 data line (SD) +
73:NXP Semiconductors
60:Production history
41:
1425:
1424:
1411:
1138:Apple Desktop Bus
1115:PCI Express (via
1074:Serial ATA (SATA)
760:Network on a chip
640:I²S Specification
350:
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131:
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71:, known today as
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634:External links
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393:DIN connectors
377:BNC connectors
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316:. Please help
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274:with the MSB (
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217:Serial clock (
207:Timing diagram
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148:(PCM) between
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1261:Parallel SCSI
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1153:Commodore bus
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1101:Fibre Channel
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765:Plug and play
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755:Bus mastering
753:
751:
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743:
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730:Back-side bus
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642:- Philips/NXP
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389:Audio Alchemy
386:
382:
381:8P8C ("RJ45")
378:
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309:
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303:This section
301:
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273:
270:, encoded as
269:
264:
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231:Serial data (
230:
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224:Word select (
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58:
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33:
29:
22:
1448:Serial buses
1316:
906:TURBOchannel
696:
620:. Retrieved
616:
606:
598:
585:
577:
571:. Retrieved
567:
558:
550:
544:. Retrieved
540:
493:. Retrieved
480:
469:the original
383:socket or a
374:
370:
351:
336:
330:October 2022
327:
307:verification
304:
265:
261:
249:
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232:
225:
218:
212:
191:
187:
182:
178:
171:
157:
153:
137:
133:
132:
1379:CoreConnect
1358:ExpressCard
1286:Thunderbolt
1276:Camera Link
1059:Bus and Tag
745:Address bus
740:Control bus
735:Daisy chain
368:standards.
252:sample rate
102:Data signal
1432:Categories
1232:ACCESS.bus
1131:Peripheral
931:InfiniBand
926:HP GSC bus
720:System bus
622:2022-09-11
573:2016-11-04
568:e2e.ti.com
546:2016-11-04
431:References
188:controller
1193:Lightning
1143:Atari SIO
1018:SpaceWire
851:Zorro III
791:S-100 bus
786:SS-50 bus
779:Standards
699:standards
692:Technical
314:talk page
106:Push-pull
1419:Category
1394:Wishbone
1367:Embedded
1346:Portable
1266:Profibus
1198:DMX512-A
1084:Parallel
936:Ethernet
846:Zorro II
796:Multibus
697:de facto
617:diyAudio
495:19 March
403:See also
397:PS Audio
266:Data is
122:Protocol
79:Designed
65:Designer
1399:SLIMbus
1353:PC Card
1337:TOSLINK
1027:Storage
981:RapidIO
861:FASTBUS
816:STD Bus
713:General
362:Toslink
358:AES/EBU
198:Details
168:History
87: (
42:I²S bus
1332:S/PDIF
1223:1-Wire
1188:RS-485
1183:RS-423
1178:RS-422
1173:RS-232
1034:ST-506
991:NVLink
841:STEbus
801:Unibus
418:S/PDIF
366:S/PDIF
268:signed
209:of I²S
192:target
179:master
142:serial
126:Serial
1327:McASP
1295:Audio
1240:SMBus
1236:PMBus
1218:UNI/O
1158:HP-IL
1111:SATAe
1096:ESCON
1069:HIPPI
901:NuBus
856:CAMAC
826:Q-Bus
821:SMBus
806:VAXBI
703:wired
595:(PDF)
520:(PDF)
491:. NXP
489:(PDF)
472:(PDF)
465:(PDF)
379:, an
280:first
183:slave
112:Width
34:, or
1384:AMBA
1322:MADI
1307:AES3
1168:MIDI
1121:NVMe
1117:AHCI
1079:SCSI
1064:DSSI
1039:ESDI
916:SBus
876:EISA
811:MBus
701:for
694:and
497:2022
385:DE-9
190:and
181:and
97:Data
89:1986
82:1986
47:Type
1388:AXI
1317:I²S
1271:USB
1256:D²B
1251:SPI
1246:I3C
1228:I²C
1163:HIL
1148:DCB
1119:or
1106:SSA
1089:SAS
1049:SMD
1044:IPI
966:AGP
956:PXI
946:PCI
941:UPA
921:VLB
911:MCA
896:VPX
891:VXS
886:VXI
881:VME
866:LPC
836:ISA
656:PDF
364:or
320:by
219:SCK
186:to
162:I²C
158:IIS
154:I2S
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